Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present application provide a storage capacitor capable of increasing a surface area of the storage capacitor by providing a first electrode having a column shape between a substrate and a second electrode, a semiconductor device including the same, and a method of manufacturing the same. According to embodiments of the present application, the storage capacitor includes a substrate, a first electrode having a column shape and disposed on the substrate, a first dielectric layer disposed between the substrate and the first electrode, a second electrode disposed on the substrate and the first electrode and covering a side surface and a top surface of the first electrode, a second dielectric layer disposed between the first electrode and the second electrode, and a third dielectric layer disposed between the substrate and the second electrode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0165724, filed on November 26, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to a method for manufacturing a semiconductor device, and more specifically, to a semiconductor device including a reservoir capacitor and a method for manufacturing the same. Background Technology

[0004] In semiconductor integrated circuit devices, high integration density, low voltage, and high speed are the main variables determining the performance of these devices. These devices require low voltage and various levels of power. However, it is well known that noise can be generated when power is supplied to semiconductor integrated circuit devices, and this noise can alter the device's signal transmission characteristics, including, for example, delay.

[0005] Therefore, capacitors, such as storage capacitors, are formed in the peripheral region of semiconductor integrated circuit devices to remove noise. Summary of the Invention

[0006] Embodiments of the present invention provide a semiconductor device including an improved storage capacitor having an increased surface area for improved noise suppression. The capacitor may employ a cylindrical first electrode disposed between a substrate and a second electrode. Embodiments of the present invention also provide a method for manufacturing the semiconductor device.

[0007] According to one embodiment of the present invention, a storage capacitor includes: a substrate; a first electrode having a cylindrical shape and disposed on the substrate; a first dielectric layer disposed between the substrate and the first electrode; a second electrode disposed on the substrate and the first electrode and covering a side surface and a top surface of the first electrode; a second dielectric layer disposed between the first electrode and the second electrode; and a third dielectric layer disposed between the substrate and the second electrode.

[0008] According to one embodiment of the present invention, a storage capacitor includes: a substrate including an active region defined by a device isolation layer and the device isolation layer; a plurality of trenches formed in the substrate and spaced apart from each other; a first dielectric layer covering the bottom surface and sidewalls of the trenches; a plurality of first electrodes partially buried in the trenches, located above the first dielectric layer, and having a columnar shape protruding above the substrate; a second dielectric layer covering the top surface and side surface of each first electrode; a third dielectric layer covering the portion of the substrate exposed between the first electrodes; and a second electrode formed on the second and third dielectric layers.

[0009] According to one embodiment of the present invention, a semiconductor device includes: a substrate including a cell region and a peripheral circuit region; a bit line structure including bit line contact plugs on the substrate of the cell region; a first electrode having a cylindrical shape and disposed on the substrate of the peripheral circuit region; a second electrode disposed on the substrate and the first electrode in the peripheral circuit region and covering the side surface and top surface of the first electrode; a second dielectric layer disposed between the first electrode and the second electrode; and a third dielectric layer disposed between the substrate and the second electrode.

[0010] According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming a capping layer on a substrate, the substrate including a cell region and a peripheral circuit region; forming bit line contact holes that expose the substrate by penetrating the capping layer of the cell region and peripheral trenches that expose the substrate by penetrating the capping layer of the peripheral circuit region; forming preliminary bit line contact plugs and a first electrode by gap-filling conductive material in the bit line contact holes and the peripheral trenches; forming a storage capacitor on the substrate of the peripheral circuit region, the storage capacitor including a first electrode having a cylindrical shape; and forming a bit line structure on the substrate of the cell region, the bit line structure including bit line contact plugs.

[0011] This invention improves capacitance by increasing the surface area of ​​the storage capacitor. This invention also improves the reliability of semiconductor devices by improving the capacitance of the storage capacitor.

[0012] These and other features and advantages of the present invention will become apparent to those skilled in the art from the following detailed description of exemplary embodiments of the invention in conjunction with the accompanying drawings. Attached Figure Description

[0013] Figure 1 This is a perspective view showing a storage capacitor of a semiconductor device according to an embodiment of the present invention.

[0014] Figure 2 This is a cross-sectional view showing a storage capacitor of a semiconductor device according to an embodiment of the present invention.

[0015] Figure 3 This is a plan view illustrating a semiconductor device according to an embodiment of the present invention.

[0016] Figure 4 This is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

[0017] Figures 5A to 18B These are plan and cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0018] The various embodiments described herein will be described with reference to cross-sectional views, plan views, and block diagrams, which serve as ideal schematic diagrams of the invention. Therefore, the structure of the drawings may be modified due to manufacturing techniques and / or tolerances. The various embodiments of the invention may not be limited to the specific structures shown in the drawings, but may include any variations in structure that may result from manufacturing processes. Furthermore, the shapes of any regions and areas shown in the drawings are intended to illustrate specific examples of the structure of various element regions and are not intended to limit the scope of the invention. For clarity of description, the dimensions and relative dimensions of the components shown in the drawings may be exaggerated. The same reference numerals refer to the same elements throughout, and "and / or" includes each combination of one or more of the listed items. In this specification, unless otherwise stated in common usage, the singular also includes the plural.

[0019] A semiconductor device according to one embodiment of the present invention may include a storage capacitor disposed in a peripheral circuit region of the semiconductor device. The storage capacitor may also be referred to as a "decoupling capacitor." A storage capacitor is a device used to filter noise present between various operating voltages (such as, for example, the positive supply voltage VDD and the ground voltage VSS). The higher the capacitance of the storage capacitor, the more stable the operating voltage can be supplied.

[0020] Figure 1 This is a perspective view showing a storage capacitor of a semiconductor device according to an embodiment of the present invention. Figure 2 This is a cross-sectional view showing a storage capacitor of a semiconductor device according to an embodiment of the present invention. Figure 1 and Figure 2 The same reference numerals in the figures indicate the same structure.

[0021] like Figure 1 and Figure 2As shown, the storage capacitor according to this embodiment may include: a substrate 101 including a plurality of trenches 112; a first electrode (LE) / 114′ having a cylindrical shape protruding above the substrate and partially buried in the trenches 112; a first dielectric layer 113 between the substrate 101 and the first electrode (LE) / 114′; a second electrode structure (UE) / 117 / 118′ / 119′ disposed on the substrate 101 and the first electrode (LE) / 114′ and covering the sidewalls and top surface of the first electrode (LE) / 114′; a second dielectric layer 115 between the first electrode (LE) / 114′ and the second electrode structure (UE) / 117 / 118′ / 119′; and a third dielectric layer 116 between the substrate 101 and the second electrode structure (UE) / 117 / 118′ / 119′. In addition, the storage capacitor may include first to third interconnects ML1, ML2, and ML3 for applying voltage to the substrate 101 and each electrode. Each interconnect may be electrically connected to the substrate 101 and / or each electrode via first to third contacts CT1, CT2, and CT3.

[0022] Substrate 101 may be a material suitable for semiconductor processes. Substrate 101 may include a semiconductor substrate. Substrate 101 may be made of a silicon-containing material. Substrate 101 may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. Substrate 101 may include other semiconductor materials such as germanium. Substrate 101 may include a group III / V semiconductor substrate, such as a compound semiconductor substrate such as gallium arsenide (GaAs). Substrate 101 may include a silicon-on-insulator (SOI) substrate.

[0023] A first dielectric layer 113 may be disposed between the substrate 101 and the first electrode (LE) / 114′. The first dielectric layer 113 may comprise silicon oxide. The first dielectric layer 113 may be formed by a thermal oxidation process. The first dielectric layer 113 may be formed to cover the side and bottom surfaces of the trench 112. The first dielectric layer 113 formed on the side surface of the trench 112 may have a sloping profile, the sloping profile increasing in thickness toward the bottom surface of the trench 112.

[0024] A first electrode (LE) / 114′ may be disposed between the substrate 101 and the second electrode structure (UE) / 117 / 118′ / 119′. The first electrode (LE) / 114′ may be configured to include a plurality of first electrodes (LE) / 114′ spaced apart from each other at regular intervals. The first electrodes (LE) / 114′ may be spaced apart from the substrate 101 and the second electrode structure (UE) / 117 / 118′ / 119′ by a first dielectric layer 113 and a second dielectric layer 115, respectively.

[0025] The second dielectric layer 115 can be disposed between the first electrode (LE) / 114′ and the second electrode structure (UE) / 117 / 118′ / 119′. The third dielectric layer 116 can be disposed between the substrate 101 and the second electrode structure (UE) / 117 / 118′ / 119′. The second dielectric layer 115 and the third dielectric layer 116 can comprise silicon oxide. The second dielectric layer 115 and the third dielectric layer 116 can be formed simultaneously. The second dielectric layer 115 and the third dielectric layer 116 can be formed by a thermal oxidation process.

[0026] The second electrode structure (UE) / 117 / 118′ / 119′ may include a conductive material. The second electrode structure (UE) / 117 / 118′ / 119′ may include a stacked structure of semiconductor materials and metallic materials.

[0027] The first to third interconnects ML1, ML2, and ML3 can be positioned at a horizontal height higher than the second electrode structure (UE) / 117 / 118′ / 119′. The first to third interconnects ML1, ML2, and ML3 can be positioned at the same horizontal height or at different horizontal heights. The first interconnect ML1 can be connected to multiple first electrodes 114′. The first contact CT1 can electrically connect the first interconnect ML1 and the multiple first electrodes 114′. The second interconnect ML2 can be connected to the second electrode structure (UE) / 117 / 118′ / 119′. The second contact CT2 can electrically connect the second electrode structure (UE) / 117 / 118′ / 119′ to the second interconnect ML2. The third interconnect ML3 can be connected to the substrate 101. The third contact CT3 can electrically connect the third interconnect ML3 and the substrate 101.

[0028] Impurity regions 120 can be formed on both sides of the storage capacitor and in the substrate 101.

[0029] As a comparative example, the capacitance of a conventional planar MOS capacitor consists of a substrate, a second electrode with a planar structure formed on the substrate, and a dielectric layer disposed between the substrate and the second electrode. In contrast, in the storage capacitor according to this embodiment, a cylindrical first electrode (LE) / 114′ is formed between the substrate 101 and the second electrode structure (UE) / 117 / 118′ / 119′. Therefore, the surface area of ​​the capacitor can be increased, thereby increasing the capacitance.

[0030] More specifically, the capacitance of the storage capacitor according to this embodiment can be the sum of a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first capacitor passes through a substrate 101, a first dielectric layer 113, and a first electrode (LE) / 114′; the second capacitor C2 passes through a second dielectric layer 115 and a second electrode structure (UE) / 117 / 118′ / 119′; and the third capacitor C3 passes through a substrate 101, a third dielectric layer 116, and a second electrode structure (UE) / 117 / 118′ / 119′.

[0031] Although the storage capacitor in this embodiment shows three or four first electrodes (LE) / 114′, the invention is not limited thereto. The number of first electrodes included in the storage capacitor, the spacing between the first electrodes, and the height and width of each first electrode can be adjusted as needed.

[0032] Figure 3 This is a plan view illustrating a semiconductor device according to an embodiment of the present invention. Figure 4 This is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. Figure 4 It is along Figure 3 The cross-sectional view of lines AA′, BB′ and CC′.

[0033] refer to Figure 3 The semiconductor device 100 may include: a cell region R1 in which a plurality of memory cells are formed; and a peripheral circuit region R2 in which a storage capacitor is formed. The cell region R1 and the peripheral circuit region R2 may be spaced apart by a device isolation layer 102 (see reference). Figure 4 ).

[0034] Cell area R1 may include word lines, bit lines, and capacitors. Cell area R1 is a storage cell area used to store data and can be driven by selecting word lines and bit lines.

[0035] Cell region R1 may include a plurality of active regions 103 defined by device isolation layer 102. Each active region 103 may be island-shaped, having a major axis and a minor axis. The active regions 103 may be spaced apart from each other at regular intervals by device isolation layer 102. Cell region R1 may include: bit line structures BL, etc., extending in a direction perpendicular to word lines; and word lines, which are formed by buried gate structures BG, i.e., extending in the direction of the major axis of active regions 103. Cell region R1 is a memory cell region for storing data and can be driven by selecting word lines and bit lines.

[0036] A peripheral circuit region R2 may be formed around the cell region R1 and includes circuitry for driving and controlling the memory cells. Specifically, according to an embodiment of the invention, the peripheral circuit region R2 may include a storage capacitor for filtering noise present between various operating voltages (such as positive power supply voltage VDD and ground voltage VSS). In this embodiment, for ease of description, a storage capacitor is shown.

[0037] refer to Figure 4 The semiconductor device according to an embodiment of the present invention may include a cell region R1 and a peripheral circuit region R2.

[0038] The cell region R1 may include a buried gate structure BG disposed in the substrate 101 and a bit line structure BL formed on the substrate 101.

[0039] The buried gate structure BG may include: a gate trench 105; a gate insulating layer 106 covering the bottom surface and sidewalls (also referred to as side surfaces) of the gate trench 105; a buried gate electrode 107 partially filling the gate trench 105 above the gate insulating layer 106; and a gate capping layer 108 formed above the buried gate electrode 107. Source / drain regions 109 and 110 may be formed in the substrate 101 on both sides of the buried gate structure BG.

[0040] The bit line structure BL may include a bit line contact plug 114, bit lines 118 and 119 above the bit line contact plug 114, and a bit line hard mask 120 above the bit lines 118 and 119. The bit line contact plug 114 may be connected to a source / drain region 109 formed between two adjacent buried gate structures BG.

[0041] The peripheral circuit region R2 can be separated from the cell region R1 by the device isolation layer 102. The storage capacitor of the peripheral circuit region R2 may include: a substrate 101, which includes a plurality of peripheral trenches 112; a first electrode 114', which is partially buried in the peripheral trenches 112 and has a cylindrical shape protruding above the substrate 101; a first dielectric layer 113, which is disposed between the substrate 101 and the first electrode 114'; a second electrode structure 117 / 118' / 119', which is disposed on the substrate 101 and the first electrode 114' and covers the side surface and top surface of the first electrode 114'; a second dielectric layer 115, which is disposed between the first electrode 114' and the second electrode structure 117 / 118' / 119'; and a third dielectric layer 116, which is disposed between the substrate 101 and the second electrode structure 117 / 118' / 119'. Furthermore, the storage capacitor may include a substrate 101 and first to third interconnects ML1, ML2, and ML3 for applying voltage to each electrode. The interconnects may be electrically connected to the substrate 101 and / or the electrodes via first to third contacts CT1, CT2, and CT3.

[0042] A first dielectric layer 113 may be disposed between the substrate 101 and the first electrode 114'. The first dielectric layer 113 may comprise silicon oxide. The first dielectric layer 113 may be formed by a thermal oxidation process. The first dielectric layer 113 may be formed to cover the side and bottom surfaces of the trench 112. The first dielectric layer 113 formed on the side surface of the trench 112 may have a sloping profile that increases in thickness toward the bottom surface of the trench 112.

[0043] A first electrode 114' may be disposed between the substrate 101 and the second electrode structures 117 / 118' / 119'. The first electrode 114' may be configured to include a plurality of first electrodes 114' spaced apart from each other at regular intervals. The first electrode 114' may be spaced apart from the substrate 101 and the second electrode structures 117 / 118' / 119' by a first dielectric layer 113 and a second dielectric layer 115.

[0044] The second dielectric layer 115 can be disposed between the first electrode 114' and the second electrode structures 117 / 118' / 119'. The third dielectric layer 116 can be disposed between the substrate 101 and the second electrode structures 117 / 118' / 119'. The second dielectric layer 115 and the third dielectric layer 116 can comprise silicon oxide. The second dielectric layer 115 and the third dielectric layer 116 can be formed simultaneously. The second dielectric layer 115 and the third dielectric layer 116 can be formed by a thermal oxidation process.

[0045] The second electrode structure 117 / 118′ / 119′ may include a conductive material. The second electrode structure 117 / 118′ / 119′ may include a stacked structure of semiconductor material and metal material.

[0046] The first to third interconnects ML1, ML2, and ML3 can be located at a horizontal height higher than the second electrode structures 117 / 118′ / 119′. The first to third interconnects ML1, ML2, and ML3 can be located at the same or different horizontal heights. The first interconnect ML1 can be connected to multiple first electrodes 114′. The first contact CT1 can electrically connect the first interconnect ML1 to the multiple first electrodes 114′. The second interconnect ML2 can be connected to the second electrode structures 117 / 118′ / 119′. The second contact CT2 can electrically connect the second electrode structures 117 / 118′ / 119′ to the second interconnect ML2. The third interconnect ML3 can be connected to the substrate 101. The third contact CT3 can electrically connect the third interconnect ML3 to the substrate 101. The third contact CT3 can contact the impurity region 120.

[0047] According to an embodiment of the present invention, the capacitance of the storage capacitor may be the sum of a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first capacitor passes through a substrate 101, a first dielectric layer 113, and a first electrode 114'. The second capacitor passes through a first electrode 114', a second dielectric layer 115, and a second electrode structure 117 / 118' / 119'. The third capacitor C3 passes through a substrate 101, a third dielectric layer 116, and a second electrode structure 117 / 118' / 119'.

[0048] The bit line contact plug 114 of cell region R1 and the first electrode 114' of peripheral circuit region R2 can be located at the same horizontal height. The bit line contact plug 114 of cell region R1 and the first electrode 114' of peripheral circuit region R2 can be formed of the same material. The bit line contact plug 114 and the first electrode 114' can be formed simultaneously by a single gap filling process.

[0049] Figures 5A to 18B These are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 5A to 18B In the diagram, the figures represented by "A" are planar figures, and the figures represented by "B" have cross-sectional views taken along lines AA′, BB′, and CC′ of the figure represented by A.

[0050] like Figure 5A and Figure 5B As shown, a substrate 11 may be provided, including a cell region R1 and a peripheral circuit region R2.

[0051] The substrate 11 may include a device isolation layer 12 and an active region 13 defined by the device isolation layer 12. The active regions 13 may be spaced apart from each other at regular intervals by the device isolation layer 12. The cell region R1 and the peripheral circuit region R2 may be spaced apart by the device isolation layer 12.

[0052] Substrate 11 may be a material suitable for semiconductor processes. Substrate 11 may include a semiconductor substrate. Substrate 11 may be made of a silicon-containing material. Substrate 11 may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. Substrate 11 may include other semiconductor materials such as germanium. Substrate 11 may include a group III / V semiconductor substrate, such as a compound semiconductor substrate such as gallium arsenide (GaAs). Substrate 11 may include a silicon-on-insulator (SOI) substrate.

[0053] Device isolation layer 12 can be formed using a shallow trench isolation (STI) process. The STI process may include etching a substrate 11 to form isolation trenches (reference numerals omitted). The isolation trenches are then filled with an insulating material, thus forming device isolation layer 12. Device isolation layer 12 may include silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition (CVD) or other deposition processes may be used to fill the isolation trenches with the insulating material. Planarization processes such as chemical mechanical polishing (CMP) may also be used.

[0054] Next, a buried gate structure BG can be formed in the substrate 11 of the cell region R1. The buried gate structure BG may include: a gate trench 15; a gate insulating layer 16 covering the bottom surface and sidewalls of the gate trench 15; a buried gate electrode 17 partially filling the gate trench 15 above the gate insulating layer 16; and a gate capping layer 18 formed above the buried gate electrode 17.

[0055] The method for forming a buried gate structure (BG) is as follows.

[0056] First, a gate trench 15 can be formed in the substrate 11 of the cell region R1. The gate trench 15 can have a linear shape intersecting the active region 13 and the device isolation layer 12. The gate trench 15 can be formed by an etching process that forms a mask pattern on the substrate 11 and uses the mask pattern as an etching mask. To form the gate trench 15, a hard mask layer 14 can be used as an etch barrier. The hard mask layer 14 can have a shape patterned by the mask pattern. The hard mask layer 14 can cover the entire surface of the substrate in the peripheral circuit region R2. The hard mask layer 14 can include silicon oxide. The hard mask layer 14 can include tetraethyl orthosilicate (TEOS). The bottom surface of the gate trench 15 can be at a higher level than the bottom surface of the device isolation layer 12.

[0057] A portion of the device isolation layer 12 in cell region R1 can be recessed to make the active region 13 below the gate trench 15 protrude. The device isolation layer 12 below the gate trench 15 can be selectively recessed. Therefore, a fin region can be formed below the gate trench 15. The fin region can be part of the channel region.

[0058] Next, a gate insulating layer 16 can be formed on the bottom surface and sidewalls of the gate trench 15. Before forming the gate insulating layer 16, etching damage on the surface of the gate trench 15 can be repaired. For example, the sacrificial oxide can be removed after forming a sacrificial oxide by thermal oxidation.

[0059] The gate insulating layer 16 can be formed by thermal oxidation. For example, the gate insulating layer 16 can be formed by oxidizing the bottom and sidewalls of the gate trench 15.

[0060] In another embodiment, the gate insulating layer 16 can be formed by a deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The gate insulating layer 16 may include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. The high-k material may include hafnium oxide. Hafnium-containing materials may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In another embodiment, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0061] In another embodiment, the gate insulating layer 16 can be formed by depositing liner polysilicon and then subjecting the liner polysilicon layer to free radical oxidation.

[0062] In another embodiment, the gate insulating layer 16 can be formed by radical oxidation of the silicon nitride liner layer after the silicon nitride liner layer has been formed.

[0063] Next, a buried gate electrode 17 can be formed on the gate insulating layer 16. To form the buried gate electrode 17, a recess process can be performed after forming a conductive layer to fill the gate trench 15. The recess process can be performed as an etch-back process, or as a chemical mechanical polishing (CMP) process followed by an etch-back process. The buried gate electrode 17 can have a recessed shape that partially fills the gate trench 15. That is, the top surface of the buried gate electrode 17 can be at a lower horizontal height than the top surface of the active region 13. The structure of the buried gate electrode 17 can include metal, metal nitride, or a combination thereof. For example, the buried gate electrode 17 can be formed from titanium nitride (TiN), tungsten (W), or a titanium nitride / tungsten (TiN / W) stack. The titanium nitride / tungsten (TiN / W) stack can have a structure in which titanium nitride is conformally formed and then the gate trench 15 is partially filled with tungsten. As a buried gate electrode 17, titanium nitride can be used alone, and this can be referred to as a buried gate electrode 17 with a "TiN-only" structure. A dual-gate structure of titanium nitride / tungsten (TiN / W) stack and polysilicon layer can be used as a buried gate electrode 17.

[0064] Next, capping layers 18 and 18A can be formed on the entire surface of the substrate including the buried gate electrode 17. Capping layers 18 and 18A may include an insulating material. Capping layers 18 and 18A may include silicon nitride. In another embodiment, capping layers 18 and 18A may include silicon oxide. In yet another embodiment, capping layers 18 and 18A may have a nitride-oxide-nitride (NON) structure.

[0065] The capping layers 18 and 18A can be divided into: a gate capping layer 18, the gaps of which fill the gate trench 15 on the buried gate electrode 17; and a protective capping layer 18A, which covers the top surface of the hard mask layer 14. The buried gate structure BG can be formed from the gate insulating layer 16, the buried gate electrode 17, and the gate capping layer 18.

[0066] The top surface of the protective capping layer 18A can be at a higher horizontal level than the top surface of the hard mask layer 14. The protective capping layer 18A can cover both the hard mask layer 14 and the buried gate structure BG.

[0067] Next, source / drain regions 19 and 20 can be formed on the substrate 11 on both sides of the buried gate structure BG. Source / drain regions 19 and 20 can be formed by a doping process such as implantation. Source / drain region 19 can be formed between adjacent buried gate structures BG and can be a region to be connected to a bit line contact plug. Source / drain region 20 can be formed outside the buried gate structure BG between the buried gate structure BG and the device isolation layer 12, and can be a region to be connected to a memory node contact plug.

[0068] like Figure 6A and Figure 6B As shown, multiple bit line contact holes 21 can be formed in the cell region R1, and multiple peripheral trenches 21′ can be formed in the peripheral circuit region R2.

[0069] Bit line contact holes 21 can be disposed between adjacent buried gate structures BG. Peripheral trenches 21' can be disposed in the active region 13 of the peripheral circuit region R2 and spaced apart from each other by regular intervals.

[0070] Bit line contact holes 21 and peripheral trenches 21' are formed by etching the protective capping layer 18A and the hard mask layer 14 using a contact mask. The bit line contact holes 21 and peripheral trenches 21' can be formed simultaneously. That is, the protective capping layer 18A and the hard mask layer 14 of the cell region R1 and the peripheral circuit region R2 can be etched simultaneously using a contact mask, which covers the cell region R1 and the peripheral circuit region R2, and defines the hole region and the peripheral trench region in the cell region R1 and the peripheral circuit region R2, respectively. In another embodiment, the bit line contact holes 21 and the peripheral trenches 21' can be formed sequentially using their respective mask processes.

[0071] A portion of the substrate 11 of cell region R1 can be exposed through bit line contact hole 21. Bit line contact hole 21 can have a diameter controlled to a predetermined linewidth. Bit line contact hole 21 can have a shape that exposes a portion of the active region 13 of cell region R1. Bit line contact hole 21 has a diameter larger than the width of the minor axis of the active region 13 of cell region R1. Therefore, in the etching process used to form bit line contact hole 21, a portion of the device isolation layer 12 and the active region 13 of cell region R1 can be etched. That is, the active region 13 and the device isolation layer 12 below bit line contact hole 21 can be recessed to a predetermined depth. Therefore, the bottom of bit line contact hole 21 can extend into substrate 11.

[0072] The substrate 11 of the peripheral circuit region R2 can be recessed to a predetermined depth by means of peripheral trenches 21'. In one embodiment of the invention, the linewidth of the peripheral trenches 21' can be smaller than the linewidth of the bit line contact holes 21. In another embodiment, the linewidth of the peripheral trenches 21' can be the same as or greater than the linewidth of the bit line contact holes 21. In this embodiment, the distance between adjacent peripheral trenches 21' can be smaller than the distance between adjacent bit line contact holes 21. In another embodiment, the distance between adjacent peripheral trenches 21' can be the same as or greater than the distance between adjacent bit line contact holes 21. The linewidth of the peripheral trenches 21', the depth of the peripheral trenches 21', and the number of peripheral trenches 21' disposed in the active region 13 of the peripheral circuit region R2 can be adjusted as needed.

[0073] like Figure 7A and Figure 7B As shown, a first dielectric layer 22 may be formed on the surface of the substrate 11 in the peripheral circuit region R2 exposed by the peripheral trench 21'. The first dielectric layer 22 may comprise silicon oxide. The first dielectric layer 22 may be formed by a thermal oxidation process. The first dielectric layer 22 may be formed by a rapid thermal annealing (RTA) process in an oxygen (O2) atmosphere. The first dielectric layer 22 may be formed locally on the surface of the substrate 11 in the peripheral trench 21'. Although the first dielectric layer 22 is shown to have the same thickness at the bottom and sidewalls of the peripheral trench 21', the thickness of the first dielectric layer 22 formed on the sidewalls of the peripheral trench 21' may be greater than the thickness of the first dielectric layer 22 formed at the bottom of the peripheral trench 21'. In another embodiment, the first dielectric layer 22 formed on the sidewalls of the peripheral trench 21' may have a sloping profile whose thickness increases as it approaches the bottom.

[0074] In this case, silicon oxide 22′ can also be formed on the surface of the substrate 11 of the cell region R1 exposed by the bit line contact hole 21.

[0075] like Figure 8A and Figure 8B As shown, a first cell opening mask 23 can be formed. The first cell opening mask 23 can cover the structure of the peripheral circuit region R2. The first cell opening mask 23 may include a photoresist.

[0076] Subsequently, the silicon oxide 22′ formed on the surface of the substrate 11 in the cell region R1 can be removed (see reference). Figure 6B ).

[0077] Subsequently, the first unit opening mask 23 can be removed.

[0078] like Figure 9A and Figure 9B As shown, the following can be formed: a preliminary bit line contact plug 24A, the gap of which fills the bit line contact hole 21 of the unit region R1; and a first electrode 24′, the gap of which fills the peripheral trench 21′ of the peripheral circuit region R2.

[0079] The process for forming the initial bit line contact plug 24A and the first electrode 24′ is as follows.

[0080] First, a plug conductive layer is formed on the protective capping layer 18A and bit line contact hole 21 of cell region R1, and a protective capping layer 18A and peripheral trench 21' of peripheral circuit region R2 can be formed. The plug conductive layer can be applied to the bit line contact plug of cell region R1 and the first electrode of peripheral circuit region R2. The plug conductive layer may include a material with etching selectivity relative to the protective capping layer 18A. The plug conductive layer may include silicon material. The plug conductive layer may include polysilicon. The plug conductive layer may include polysilicon doped with impurities.

[0081] Subsequently, the plug conductive layer can be etched, leaving it within the bit line contact hole 21 of cell region R1 and the peripheral trench 21' of peripheral circuit region R2. The plug conductive layer can be etched using an etch-back process or a CMP process. The etching stop target for the plug conductive layer can be the protective capping layer 18A. That is, the etching process can be performed until all plug conductive layers on the protective capping layer 18A are removed. After the etching process, a cleaning process can be performed.

[0082] like Figures 10A to 12B As shown, a cell protection layer 25 can be formed to cover the initial bit line contact plug 24A, as well as a protective cover layer 18A for cell region R1 and a protective cover layer 18A for peripheral circuit region R2. The cell protection layer 25 can be used to prevent oxidation of the initial bit line contact plug 24A in cell region R1. The cell protection layer 25 may include an insulating material. The cell protection layer 25 may include silicon nitride.

[0083] Subsequently, a peripheral aperture mask 26 can be formed on the cell protection layer 25 of cell region R1. The cell protection layer 25 of peripheral circuit region R2 can be exposed by the peripheral aperture mask 26. The peripheral aperture mask 26 may include a photoresist.

[0084] Subsequently, the cell protection layer 25 of the peripheral circuit region R2 is etched by using the peripheral opening mask 26.

[0085] Therefore, in the peripheral circuit region R2, the first electrode 24' and the protective cover layer 18A can be exposed.

[0086] Subsequently, the hard mask layer 14 and the protective capping layer 18A of the peripheral circuit region R2 are etched using the peripheral opening mask 26. Thus, the surface of the substrate 11 can be exposed in the peripheral circuit region R2. A portion of the first electrode 24' can be buried in the substrate 11, while the remainder can have a cylindrical shape protruding above the substrate 11.

[0087] Subsequently, the outer opening mask 26 can be removed.

[0088] like Figure 13A and Figure 13B As shown, a second dielectric layer 27 may be formed, which covers the top and side surfaces of the first electrode 24′; and a third dielectric layer 28, which covers the exposed surface of the substrate 11 of the peripheral circuit region R2.

[0089] The second dielectric layer 27 and the third dielectric layer 28 may comprise silicon oxide. The second dielectric layer 27 and the third dielectric layer 28 may be formed simultaneously via a thermal oxidation process. Alternatively, the second dielectric layer 27 and the third dielectric layer 28 may be formed in an oxygen (O2) atmosphere via a rapid thermal annealing (RTA) process.

[0090] like Figure 14A and Figure 14B As shown, the peripheral conductive layer 29A can be formed on the cell protection layer 25 of the cell region R1 and on the second dielectric layer 27 and the third dielectric layer 28 of the peripheral circuit region R2. The peripheral conductive layer 29A can be formed with a top surface at least at a horizontal height higher than the top surface of the first electrode 24'. The peripheral conductive layer 29A can include silicon material. The peripheral conductive layer 29A can include polycrystalline silicon. The peripheral conductive layer 29A can include polycrystalline silicon doped with impurities.

[0091] like Figures 15A to 16B As shown, a second cell opening mask 30 can be formed on the peripheral conductive layer 29A of the peripheral circuit region R2. The peripheral conductive layer 29A of the cell region R1 can be exposed by the second cell opening mask 30. The second cell opening mask 30 may include a photoresist.

[0092] Subsequently, the cell protection layer 25 and the peripheral conductive layer 29A of the cell region R1 can be etched using the second cell opening mask 30. Therefore, the peripheral conductive layer 29B can be retained only in the peripheral circuit region R2.

[0093] Therefore, in cell region R1, the protective cover layer 18A and the initial bit line contact plug 24A can be exposed.

[0094] The initial position line contact plug 24A can be recessed to a predetermined depth, such that the top surface of the initial position line contact plug 24A is positioned at a horizontal height lower than the top surface of the protective cover layer 18A.

[0095] Subsequently, the second unit opening mask 30 can be removed.

[0096] like Figures 17A to 18B As shown, bit line conductive layers 31A and 32A can be formed on the protective cover layer 18A and the initial bit line contact plug 24A of the cell region R1 and on the peripheral conductive layer 29B of the peripheral circuit region R2. Bit line conductive layers 31A and 32A can serve as bit lines in the cell region R1 and as second electrodes in the peripheral circuit region R2. Bit line conductive layers 31A and 32A can include metallic materials. Bit line conductive layers 31A and 32A can include metals, metal nitrides, metal silicides, or combinations thereof. For example, bit line conductive layers 31A and 32A can include a stacked structure of a barrier layer 31A and an electrode layer 32A.

[0097] The barrier layer 31A can be formed from multiple layers. For example, the barrier layer 31A can have a stacked structure of titanium (Ti), tungsten nitride (WN), and tungsten silicon nitride (WSiN). For example, the electrode layer 32A can include tungsten (W). The titanium (Ti) layer can be used as an adhesive layer. In addition, by forming the lower peripheral conductive layer 29B and the silicide (TiSi), the formation of silicon nitride between the tungsten nitride (WN) layer and the peripheral conductive layer 29B can be prevented. The tungsten nitride (WN) layer can be used to prevent tungsten (W) from diffusing from the electrode layer 32A to the lower peripheral conductive layer 29B. Furthermore, the lower titanium (Ti) layer and titanium nitride (TiN) can be formed to prevent boron from diffusing upward from the lower peripheral conductive layer 29B. The tungsten nitride (WN) layer can be used as a seed layer for increasing the grain size of the electrode layer 32A. That is, by forming a tungsten (W) layer on a tungsten nitride (WN) layer, the grain size of the tungsten layer increases, thereby reducing the resistance of the electrode layer 32A.

[0098] Subsequently, a bit line structure BL consisting of bit line contact plugs 24, bit lines 31 and 32, and a bit line hard mask 34 can be formed in the cell region R1, and a storage capacitor including second electrode structures 29, 31' and 32' can be formed in the peripheral circuit region R2.

[0099] The process of forming the bit line structure BL of the unit region R1 and the storage capacitor of the peripheral circuit region R2 is as follows.

[0100] First, a peripheral mask can be formed. The peripheral mask can cover the entire cell region R1 and the peripheral circuit region R2 above the bit line conductive layer 32A of the cell region R1, and define a storage capacitor region in the peripheral circuit region R2.

[0101] Subsequently, the third dielectric layer 28, the peripheral conductive layer 29B, and the bit line conductive layers 32A and 31A of the peripheral circuit region R2 exposed by the peripheral mask can be etched.

[0102] Therefore, the peripheral circuit region R2 may include: a substrate 11 including a plurality of peripheral trenches 21'; second electrode structures 29, 31', and 32' disposed on the substrate 11; a first dielectric layer to a third dielectric layer 22, 27, and 28 disposed between the substrate 11 and the second electrode structures 29, 31', and 32'; and a storage capacitor. The storage capacitor may be partially buried in the peripheral trenches 21' and includes a first electrode 24' having a cylindrical shape protruding above the substrate 11.

[0103] The first electrode 24' can be disposed between the substrate 11 and the second electrode structures 29, 31' and 32'. The first electrode 24' can be configured to include a plurality of first electrodes and can be configured to be spaced apart from each other at regular intervals. The first electrode 24' can be spaced apart from the substrate 11 and the second electrode structures 29, 31' and 32' through the first dielectric layer 22 and the second dielectric layer 27.

[0104] A first dielectric layer 22 may be disposed between the substrate 11 and the first electrode 24'. A second dielectric layer 27 may be disposed between the first electrode 24' and the second electrode structures 29, 31' and 32'. A third dielectric layer 28 may be disposed between the substrate 11 and the second electrode structures 29, 31' and 32'.

[0105] The capacitance of the storage capacitor according to this embodiment can be the sum of a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first capacitor is located through a substrate 11, a first dielectric layer 22, and a first electrode 24'. The second capacitor is located through a first electrode 24', a second dielectric layer 27, and second electrode structures 29, 31', and 32'. The third capacitor C3 is located through a substrate 11, a third dielectric layer 28, and second electrode structures 29, 31', and 32'. The number of first electrodes included in a single storage capacitor, as well as the height and linewidth of each first electrode, can be adjusted as needed.

[0106] Next, impurity regions 33 can be formed on both sides of the storage capacitor in the substrate 11.

[0107] Subsequently, a cell mask covering the entire peripheral circuit region R2 and defining the bit line region can be formed in cell region R1. Before forming the cell mask, a bit line hard mask layer can be formed on the bit line conductive layers 31A and 32A of cell region R1.

[0108] Subsequently, the bit line hard mask layer, bit line conductive layers 31A and 32A, and preliminary bit line contact plug 24A can be etched sequentially using a cell mask.

[0109] Therefore, a bitline structure BL, including bitline contact plugs 24, bitlines 31 and 32, and a bitline hard mask 34, can be formed in the cell region R1.

[0110] As a subsequent process, a capacitor can be formed on the bit line structure BL of cell region R1, and metal interconnects can be formed on the capacitor in cell region R1 and on the storage capacitor in peripheral circuit region R2. The metal interconnects can be connected to the capacitor and the storage capacitor, respectively. In this case, the metal interconnect connected to the storage capacitor in peripheral circuit region R2 may include… Figure 1 and Figure 2 The interconnects shown.

[0111] Various embodiments for solving the problems described above have been described, but it will be apparent to those skilled in the art that various changes and modifications can be made within the spirit of the invention.

Claims

1. A storage capacitor, comprising: Substrate, said substrate being made of semiconductor material; A first electrode, having a cylindrical shape and disposed on the substrate; A first dielectric layer is disposed between the substrate and the first electrode; The second electrode is disposed on the substrate and the first electrode and covers the side surface and top surface of the first electrode; A second dielectric layer is disposed between the first electrode and the second electrode; as well as A third dielectric layer is disposed between the substrate and the second electrode. The substrate includes at least one trench, wherein the first dielectric layer covers the side surface and bottom surface of the trench. The first electrode is partially buried in the at least one trench and has a cylindrical shape protruding above the substrate, such that the portion of the first electrode buried in the trench, the substrate, and the first dielectric layer between them form a capacitor.

2. The storage capacitor as claimed in claim 1, wherein, The first electrode has a smaller linewidth than the second electrode.

3. The storage capacitor as claimed in claim 1, wherein, The top surface of the first electrode is located at a lower horizontal height than the top surface of the second electrode.

4. The storage capacitor as claimed in claim 1, wherein, The bottom surface of the first electrode is located at a horizontal height lower than the top surface of the substrate.

5. The storage capacitor as claimed in claim 1, wherein, The first electrodes are configured in multiples and spaced apart from each other.

6. The storage capacitor as claimed in claim 1, wherein, The first electrode comprises polycrystalline silicon.

7. The storage capacitor as claimed in claim 1, wherein, The second electrode comprises a stacked structure of polycrystalline silicon and metal materials.

8. The storage capacitor as claimed in claim 1, wherein, The second dielectric layer and the third dielectric layer are continuous single layers.

9. The storage capacitor as claimed in claim 1, wherein, The first dielectric layer and the third dielectric layer comprise silicon oxide.

10. The storage capacitor of claim 1, further comprising: Impurity regions located on both sides of the storage capacitor within the substrate.

11. The storage capacitor of claim 1, further comprising: The first interconnect to the third interconnect are located at a horizontal height higher than the second electrode; A first plug, the first plug being electrically connected to the first interconnect and the first electrode; The second plug is electrically connected to the second interconnect and the second electrode; as well as A third plug is electrically connected to the third interconnect and the substrate.

12. A storage capacitor, comprising: A substrate made of a semiconductor material and including an active region defined by a device isolation layer and the device isolation layer; Multiple trenches are formed in the substrate and spaced apart from each other; A first dielectric layer covers the bottom surface and sidewalls of the trench; A plurality of first electrodes are partially buried in the trench, located above the first dielectric layer, and have a columnar shape protruding above the substrate, such that the portion of the first electrode buried in the trench, the substrate, and the first dielectric layer between them form a capacitor. A second dielectric layer covers the top and side surfaces of each of the first electrodes; A third dielectric layer covers the portion of the substrate exposed between the first electrodes; as well as The second electrode is formed on the second dielectric layer and the third dielectric layer.

13. The storage capacitor of claim 12, wherein, The plurality of first electrodes are spaced apart at regular intervals in the active region of the substrate.

14. The storage capacitor of claim 12, wherein, The first electrode has a smaller linewidth than the second electrode.

15. The storage capacitor of claim 12, wherein, The top surface of the first electrode is located at a lower horizontal height than the top surface of the second electrode.

16. The storage capacitor of claim 12, wherein, The bottom surface of each of the first electrodes is located at a horizontal height lower than the top surface of the substrate.

17. The storage capacitor of claim 12, wherein, The first electrode comprises polycrystalline silicon.

18. The storage capacitor of claim 12, wherein, The second electrode comprises a stacked structure of polycrystalline silicon and metal materials.

19. The storage capacitor of claim 12, wherein, The second dielectric layer and the third dielectric layer are continuous single layers.

20. The storage capacitor of claim 12, wherein, The first dielectric layer to the third dielectric layer comprise silicon oxide.

21. The storage capacitor of claim 12, further comprising: Impurity regions located on both sides of the storage capacitor within the substrate.

22. The storage capacitor of claim 12, further comprising: The first interconnect to the third interconnect are located at a horizontal height higher than the second electrode; A first plug, the first plug being electrically connected to the first interconnect and the first electrode; The second plug is electrically connected to the second interconnect and the second electrode; as well as A third plug is electrically connected to the third interconnect and the substrate.

23. A semiconductor device, comprising: A substrate, said substrate being made of semiconductor material and including cell regions and peripheral circuit regions; Bit line structure, the bit line structure including bit line contact plugs, the bit line contact plugs being on the substrate of the cell region; A first electrode, having a cylindrical shape and disposed on the substrate of the peripheral circuit region; The second electrode is disposed on the substrate and the first electrode in the peripheral circuit area, and covers the side surface and top surface of the first electrode; A second dielectric layer is disposed between the first electrode and the second electrode; as well as A third dielectric layer is disposed between the substrate and the second electrode. The substrate includes at least one trench. The first electrode is partially buried in the at least one trench and has a cylindrical shape protruding above the substrate. The first dielectric layer is disposed between the substrate and the first electrode, and covers the side and bottom surfaces of the trench, such that the portion of the first electrode buried in the trench, the substrate, and the first dielectric layer between them form a capacitor.

24. The semiconductor device of claim 23, wherein, The bit line contact plug and the first electrode are located at the same horizontal height.

25. The semiconductor device of claim 23, wherein, The first electrode has a smaller linewidth than the second electrode.

26. The semiconductor device of claim 23, wherein, The top surface of the first electrode is located at a lower horizontal height than the top surface of the second electrode.

27. The semiconductor device of claim 23, wherein, The bottom surface of the first electrode is located at a horizontal height lower than the top surface of the substrate.

28. The semiconductor device of claim 23, wherein, The first electrode comprises polycrystalline silicon.

29. The semiconductor device of claim 23, wherein, The second electrode comprises a stacked structure of polycrystalline silicon and metal materials.

30. The semiconductor device of claim 23, wherein, The second dielectric layer and the third dielectric layer are continuous single layers.

31. The semiconductor device of claim 23, further comprising: Impurity regions located on both sides of the second electrode within the substrate.

32. The semiconductor device of claim 23, further comprising: The first interconnect to the third interconnect are located at a horizontal height higher than the second electrode; A first plug, the first plug being electrically connected to the first interconnect and the first electrode; The second plug is electrically connected to the second interconnect and the second electrode; as well as A third plug is electrically connected to the third interconnect and the substrate.

33. The semiconductor device of claim 23, further comprising: A buried gate structure formed in the substrate of the cell region.

34. The semiconductor device of claim 23, further comprising: A capacitor disposed on the bit line structure in the cell region and connected to the substrate; as well as A metal interconnect is disposed on the capacitor and connected to the capacitor.

35. A method for manufacturing a semiconductor device, the method comprising: A capping layer is formed on a substrate made of semiconductor material and including cell regions and peripheral circuit regions; Bit line contact holes are formed to expose the substrate by penetrating the cover layer of the cell region, and peripheral trenches are formed to expose the substrate by penetrating the cover layer of the peripheral circuit region. A first dielectric layer is formed covering the bottom surface and sidewalls of the peripheral trench; A preliminary bit line contact plug and a first electrode are formed by filling the gaps in the bit line contact hole and the peripheral trench with conductive material, such that the first electrode is partially buried in the peripheral trench and has a cylindrical shape protruding above the substrate. A storage capacitor is formed on the substrate of the peripheral circuit area. The storage capacitor includes a first electrode having a cylindrical shape. The storage capacitor further includes a capacitor formed by a portion of the first electrode buried in the peripheral trench, the substrate, and the first dielectric layer between the two. as well as A bit line structure is formed on the substrate of the cell region, the bit line structure including bit line contact plugs.

36. The method of claim 35, wherein, The steps for forming the storage capacitor include: The first electrode is left in a cylindrical shape by removing the covering layer of the peripheral circuit area; A second dielectric layer is formed covering the top surface and sidewalls of the first electrode; A third dielectric layer is formed on the top surface of the substrate covering the peripheral circuit area; A conductive material is formed on the second dielectric layer and the third dielectric layer; and The third dielectric layer and portions of the conductive material are etched.

37. The method of claim 35, further comprising, before forming the covering layer: A buried gate structure is formed in the substrate of the cell region.

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