Controllable resistor circuit based on deep linear region MOSFET

Abstract

This disclosure provides a controllable resistor circuit based on a deep linear region MOSFET, comprising: a bottom-level controllable module and an extended-level controllable module. The bottom-level controllable module is configured to control the gate-source voltage of a first transistor operating in the deep linear region based on a constant current signal to regulate the first on-resistance of the first transistor, which is the bottom-level controllable resistor. The extended-level controllable module is configured to control the gate-source voltage of a second transistor operating in the deep linear region based on a constant current signal to regulate the second on-resistance of the second transistor, which is the extended-level controllable resistor, and the resistance value of the extended-level controllable resistor is equal to the resistance value of the bottom-level controllable resistor. The bottom-level controllable module and at least one extended-level controllable module are superimposed and integrated in series with the bottom-level controllable resistor and the extended-level controllable resistor. This solves the problem that during transient response, the MOSFET may deviate from the deep linear region, affecting the normal operation of the circuit system.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of integrated circuit technology, and more specifically, to a controllable resistor circuit based on a deep linear region MOS transistor. Background Technology

[0002] Resistors are commonly used components in switching power supplies, performing functions such as voltage division, current limiting, and filtering. In actual chips, resistors can be directly fabricated (passive resistors) or implemented using active devices (active resistors). In some applications, the resistance value needs to be flexibly controlled by an analog signal. Using passive resistors requires complex analog-to-digital converters to control the resistance value, increasing the circuit design complexity; therefore, active resistors are necessary. A common method for implementing active resistors is using a MOSFET operating in the deep linear region. When a MOSFET operates in the deep linear region, the drain current is a linear function of the drain-source voltage, and the channel between the drain and source is equivalent to a linear resistance. Therefore, an active resistor implemented using a MOSFET operating in the deep linear region can have its resistance value adjusted by changing the gate-source voltage.

[0003] like Figure 1 As shown, this is a traditional deep linear region MOSFET with an active controllable resistor of 100. Mp0, Mpc0, Mp1, Mpc1, and Rp form a cascode current mirror, mirroring the current Ib. The current Ib1 output by Mp1 and Mpc1 flows into Mnb1, generating a voltage Vgs. Mnb1 The gates of Mnb1 and Mn1 are connected, and Vgs Mnb1 =Vgs Mn1 Therefore, Vgs can be regulated by controlling Ib. Mn1 The magnitude of the drain current of MOSFET Mn1 operating in the linear region is:

[0004]

[0005] Where, μ n C ox Where is a constant, W is the width of Mn1, L is the length of Mn1, Vgs is the gate-source voltage of Mn1, Vth is the turn-on voltage of Mn1, and Vds is the drain-source voltage of Mn1.

[0006] When Vds << 2(Vgs - Vth), the MOS transistor Mn1 operates in the deep linear region, and formula (1) can be simplified to:

[0007]

[0008] According to formula (2), the drain current I D It is a linear function of the drain-source voltage Vds, such as Figure 2The figure shows the IV characteristic curve of a deep linear region MOSFET. This linear relationship indicates that the channel between the drain and source can be equivalent to a linear resistor. The active resistance from V1 to GND is denoted as R1, and the resistance of R1 is:

[0009]

[0010] Among them, Vgs Mn1 Vgs is the gate-source voltage of Mn1. According to formula (3), the active controllable resistor implemented by a MOS transistor operating in the deep linear region can be controlled by changing the gate-source voltage Vgs. Mn1 To adjust its resistance (the resistance of R1), when Vds increases from 0 to 0.2 (Vgs) Mn1 When Vth is -V, the resistance R1 changes by about 25%. Within this range, the resistance can be approximated as linear. Therefore, V1 needs to be less than 0.2 (Vgs). Mn1 -Vth), where V is the cutoff voltage of the deep linear region. Line =0.2(Vgs) Mn1 -Vth).

[0011] The inventors discovered that when applying the aforementioned traditional deep linear region MOSFET active resistors, during the transient response of some circuits, if the drain-source voltage Vds of the MOSFET increases, causing it to deviate from the deep linear region, the resistance value of the active resistor increases sharply, potentially affecting the normal operation of the circuit system. For example, when using the active resistor in a low dropout regulator (LDO) circuit to achieve dynamic zero-point compensation, such as... Figure 3 As shown, a dynamic zero is generated by connecting capacitor C and active resistor R1 in series. However, during the transient response, if the potential of node V0 rises rapidly (for example, from 1V to 4V), the voltage across capacitor C will not change abruptly, and the potential of node V1 will rise accordingly. The drain-source voltage Vds of MOSFET Mn1 will increase, causing it to deviate from the deep linear region. As a result, the resistance value of the active resistor (the value of R1) will increase sharply (by about three orders of magnitude). The dynamic zero compensation will then be unable to compensate for the stability of the loop, which may affect the normal operation of the circuit system. Summary of the Invention

[0012] The embodiments described in this article provide a controllable resistor circuit based on a deep linear region MOSFET. This is to address the problem that when a deep linear region MOSFET active resistor is used in the transient response process of some circuits, there is a risk that the MOSFET will deviate from the deep linear region, affecting the normal operation of the circuit system.

[0013] According to a first aspect of this disclosure, a controllable resistor circuit based on a deep linear region MOSFET is provided, comprising: a bottom controllable module and an extended layer controllable module, wherein the bottom controllable module is configured to control the gate-source voltage of a first transistor operating in the deep linear region based on a constant current signal to regulate a first on-resistance of the first transistor, the first on-resistance being a bottom controllable resistor; the extended layer controllable module is configured to control the gate-source voltage of a second transistor operating in the deep linear region based on the constant current signal to regulate a second on-resistance of the second transistor, the second on-resistance being an extended layer controllable resistor, the resistance value of the extended layer controllable resistor being equal to the resistance value of the bottom controllable resistor; the bottom controllable module and at least one extended layer controllable module are superimposed and integrated in a manner in which the bottom controllable resistor and the extended layer controllable resistor are connected in series.

[0014] Optionally, the underlying controllable module includes: a current source, a current mirror module, a first voltage clamping module, and a first transistor, wherein the current source is coupled between a ground terminal and the current mirror module and is configured to generate the constant current signal; the current mirror module is also coupled to a power supply voltage and the first voltage clamping module and is configured to mirror the constant current signal and output a first current signal; the first voltage clamping module is also coupled to the ground terminal and the first transistor and is configured to receive the first current signal and clamp the gate-source voltage of the first transistor based on the first current signal; a first terminal of the first transistor is coupled to the ground terminal, a second terminal of the first transistor serves as the voltage output terminal of the underlying controllable module, and a control terminal of the first transistor is coupled to the first voltage clamping module.

[0015] Optionally, the current mirror module includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first resistor, wherein the first terminals of the third transistor and the fifth transistor are both coupled to the power supply voltage; the second terminal of the third transistor is coupled to the first terminal of the fourth transistor; the second terminal of the fifth transistor is coupled to the first terminal of the sixth transistor; the control terminal of the third transistor and the control terminal of the fifth transistor are coupled to a first node; the second terminal of the fourth transistor is coupled to one end of the first resistor; the second terminal of the sixth transistor is coupled to the first voltage clamping module and outputs the first current signal; the control terminal of the fourth transistor and the control terminal of the sixth transistor are coupled to a second node; the first node is also coupled to one end of the first resistor; the second node is also coupled to the other end of the first resistor; and the other end of the first resistor is also coupled to the current source.

[0016] Optionally, the first voltage clamping module includes a seventh transistor, wherein the first terminal of the seventh transistor is coupled to one end of the current source, the first terminal of the first transistor, and the ground terminal, respectively; the second terminal of the seventh transistor is coupled to the current mirror module to receive the first current signal; and the control terminal of the seventh transistor is coupled to the second terminal of the seventh transistor and the control terminal of the first transistor, respectively.

[0017] Optionally, the extended layer controllable module includes: a current mirroring module, a second voltage clamping module, a reverse conduction suppression module, and a second transistor. The current mirroring module is coupled to the power supply voltage, the second voltage clamping module, and the underlying controllable module, and is configured to mirror the constant current signal to obtain a second current signal. The second voltage clamping module is also coupled to the second transistor and the reverse conduction suppression module, and is configured to receive the second current signal and clamp the gate-source voltage of the second transistor based on the second current signal. The reverse conduction suppression module is also coupled to the second transistor and is configured to prevent the second transistor from reverse conducting. The first terminal of the second transistor serves as the voltage input terminal of the extended layer controllable module, and the second terminal of the second transistor serves as the voltage output terminal of the extended layer controllable module.

[0018] Optionally, the current mirror module includes an eighth transistor and a ninth transistor, wherein the first terminal of the eighth transistor is coupled to the power supply voltage, the second terminal of the eighth transistor is coupled to the first terminal of the ninth transistor, and the control terminal of the eighth transistor is coupled to the first node; the second terminal of the ninth transistor is coupled to the second voltage clamping module to output the second current signal, and the control terminal of the ninth transistor is coupled to the second node.

[0019] Optionally, the second voltage clamping module includes a tenth transistor, wherein the first terminal of the tenth transistor is coupled to the output terminal of the reverse conduction suppression module, the second terminal of the tenth transistor is coupled to the current mirror module to receive the second current signal, and the control terminal of the tenth transistor is coupled to the second terminal of the tenth transistor and the control terminal of the second transistor, respectively.

[0020] Optionally, the reverse conduction suppression module is a buffer, which includes an amplifier. The non-inverting input of the amplifier is coupled to the first terminal of the second transistor, the inverting input of the amplifier is coupled to the output of the amplifier, and the output of the amplifier, as the output of the reverse conduction suppression module, is also coupled to the first terminal of the tenth transistor.

[0021] Optionally, the voltage input terminal of the extended layer controllable module is coupled to the voltage output terminal of the bottom layer controllable module or to the voltage output terminal of the previous stage extended layer controllable module; the voltage output terminal of the extended layer controllable module is coupled to the voltage input terminal of the next stage extended layer controllable module or serves as the voltage output terminal of the controllable resistor circuit based on the deep linear region MOS transistor.

[0022] Optionally, the first transistor is a P-type MOS transistor or an N-type MOS transistor, and the second transistor is a P-type MOS transistor or an N-type MOS transistor.

[0023] The controllable resistor circuit based on a deep linear region MOSFET disclosed in this embodiment includes a bottom controllable module and an extended layer controllable module. The bottom controllable module is configured to control the gate-source voltage of a first transistor operating in the deep linear region based on a constant current signal to regulate the first on-resistance of the first transistor, which is the bottom controllable resistor. The extended layer controllable module is configured to control the gate-source voltage of a second transistor operating in the deep linear region based on a constant current signal to regulate the second on-resistance of the second transistor, which is the extended layer controllable resistor. The resistance value of the extended layer controllable resistor is equal to the resistance value of the bottom controllable resistor. The bottom controllable module and at least one extended layer controllable module are superimposed and integrated in a manner where the bottom controllable resistor and the extended layer controllable resistor are connected in series. Each bottom-level controllable module and each extended-level controllable module contains MOSFETs operating in the deep linear region. By merging the bottom-level controllable module and at least one extended-level controllable module in a superimposed manner, it is possible to achieve the effect of superimposing N (N≥1) layers of MOSFETs operating in the deep linear region on the traditional deep linear region MOSFETs. Therefore, the range of the deep linear region can be increased, thereby reducing the risk of transient response causing the MOSFETs to deviate from the deep linear region, and thus ensuring the normal operation of the circuit system. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0025] Figure 1 This is an exemplary circuit diagram of a traditional deep linear region MOSFET with an active controllable resistor.

[0026] Figure 2 It is the IV characteristic curve of a deep linear region MOSFET;

[0027] Figure 3 It is Figure 1 An exemplary circuit diagram showing the active resistors used in an LDO circuit to achieve dynamic zero-point compensation.

[0028] Figure 4This is a schematic block diagram of a controllable resistor circuit based on a deep linear region MOSFET according to an embodiment of the present disclosure;

[0029] Figure 5 This is a schematic circuit diagram of a controllable resistor circuit based on a deep linear region MOSFET according to an embodiment of the present disclosure.

[0030] Figure 6 This is an exemplary circuit diagram of a controllable resistor circuit based on a deep linear region MOSFET according to an embodiment of the present disclosure;

[0031] Figure 7 This is an exemplary circuit diagram of another controllable resistor circuit based on a deep linear region MOSFET according to an embodiment of the present disclosure;

[0032] Figure 8 This is an exemplary circuit diagram of another controllable resistor circuit based on a deep linear region MOSFET according to an embodiment of the present disclosure;

[0033] Figure 9 According to embodiments of this disclosure Figure 8 A comparison chart of the controllable resistances of MOSFETs operating in the deep linear region with different layer counts;

[0034] The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0037] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0038] To address the issue that when a deep linear region MOSFET active resistor is used in the transient response of some circuits, there is a risk that the MOSFET may deviate from the deep linear region, affecting the normal operation of the circuit system, this disclosure considers increasing the range of the deep linear region to reduce the risk of the MOSFET deviating from the deep linear region. The controllable resistor circuit based on a deep linear region MOSFET of this disclosure will be described in detail below.

[0039] A controllable resistor circuit 200 based on a deep linear region MOSFET according to an embodiment of this disclosure includes: a bottom-layer controllable module 210 and an extended-layer controllable module 220, such as... Figure 4 As shown, the left frame contains the bottom controllable module 210, and the right frame contains the extension layer controllable module 220.

[0040] Among them, the bottom controllable module 210 is configured to control the gate-source voltage of the first transistor Mn1 operating in the deep linear region based on the constant current signal Ib to regulate the first on-resistance of the first transistor Mn1, and the first on-resistance is the bottom controllable resistor R1.

[0041] Specifically, the underlying controllable module 210 includes: a current source 211, a current mirror module 212, a first voltage clamping module 213, and a first transistor Mn1. The current source 211 is coupled between the ground terminal GND and the current mirror module 212, and is configured to generate a constant current signal Ib. The current mirror module 212 is also coupled to the power supply voltage VDD and the first voltage clamping module 213, and is configured to mirror the constant current signal Ib and output a first current signal Ib1. The first voltage clamping module 213 is also coupled to the ground terminal GND and the first transistor Mn1, and is configured to receive the first current signal Ib1 and clamp the gate-source voltage of the first transistor Mn1 based on the first current signal Ib1. The first terminal of the first transistor Mn1 is coupled to the ground terminal GND, the second terminal of the first transistor Mn1 serves as the voltage output terminal of the underlying controllable module 210, and the control terminal of the first transistor Mn1 is coupled to the first voltage clamping module 213. The first voltage clamping module 213 is designed to control the gate-source voltage of the first transistor Mn1 via the first current signal Ib1, thereby adjusting the resistance value of the underlying controllable resistor R1. Furthermore, the first current signal Ib1 is a mirror image of the constant current signal Ib, thus allowing control of the gate-source voltage of the first transistor Mn1 via the constant current signal Ib, and consequently, the resistance value of the underlying controllable resistor R1. It should also be noted that... Figure 4 The voltage output terminal of the mid-to-low-level controllable module 210 is node V1.

[0042] The extended layer controllable module 220 is configured to control the gate-source voltage of the second transistor Mn(N+1) operating in the deep linear region based on a constant current signal Ib, thereby regulating the second on-resistance of the second transistor Mn(N+1). This second on-resistance is an extended layer controllable resistor, and its value is equal to the value of the bottom layer controllable resistor R1. It should be noted that N represents the Nth extended layer controllable module 220. Because multiple extended layer controllable modules may exist when the bottom layer controllable module 210 and the extended layer controllable module 220 are superimposed and merged, a variable N is used to label the components and signals in different extended layer controllable modules 220 to distinguish them. For example, if there are three integrated controllable extension layer modules 220, and N takes values ​​of 1, 2, and 3 respectively, then the second transistor in the first controllable extension layer module 220 is Mn2, the second transistor in the second controllable extension layer module 220 is Mn3, and the second transistor in the third controllable extension layer module 220 is Mn3. The labeling of other components and signals in the controllable extension layer module 220 follows the same principle and will not be explained in detail later. Additionally, it should be noted that... Figure 4R(N+1) in the figure represents the total active resistance from the Nth extended layer controllable module 220 to the bottom controllable module 210, that is, the active resistance from the voltage output terminal V(N+1) of the Nth extended layer controllable module 220 to the ground terminal GND.

[0043] Specifically, the extended layer controllable module 220 includes: a current mirroring module 221, a second voltage clamping module 222, a reverse conduction suppression module 223, and a second transistor Mn(N+1). The current mirroring module 221 is coupled to the power supply voltage VDD, the second voltage clamping module 222, and the underlying controllable module 210. The current mirroring module 221 is configured to mirror the constant current signal Ib to obtain the second current signal Ib(N+1). The second voltage clamping module 222 is also coupled to the second transistor Mn(N+1) and the reverse conduction suppression module 223. The control module 222 is configured to receive the second current signal Ib(N+1) and clamp the gate-source voltage of the second transistor Mn(N+1) based on the second current signal Ib(N+1); the reverse conduction suppression module 223 is also coupled to the second transistor Mn(N+1) and is configured to prevent the second transistor Mn(N+1) from conducting in reverse; the first terminal of the second transistor Mn(N+1) serves as the voltage input terminal of the extended layer controllable module 220, and the second terminal of the second transistor Mn(N+1) serves as the voltage output terminal of the extended layer controllable module 220. The second voltage clamping module 222 is designed to control the gate-source voltage of the second transistor Mn(N+1) via the second current signal Ib(N+1), thereby adjusting the resistance value of the controllable resistor in the extended layer. Furthermore, the second current signal Ib(N+1) is also a mirror image of the constant current signal Ib, thus allowing control of the gate-source voltage of the second transistor Mn(N+1) via the constant current signal Ib, thereby adjusting the resistance value of the controllable resistor in the extended layer. It should also be noted that... Figure 4 The voltage output terminal of the controllable module 220 in the middle extension layer is node V(N+1), and the voltage input terminal is node V(N+1)'.

[0044] Each of the bottom-level controllable module 210 and each of the extended-layer controllable modules 220 contains a MOSFET operating in the deep linear region. After the bottom-level controllable module 210 and at least one extended-layer controllable module 220 are superimposed and fused together using a series connection between the bottom-level controllable resistor and the extended-layer controllable resistor, compared to… Figure 1 or Figure 3 A controllable resistor of 100Ω in the deep linear region of a MOSFET can increase the range of the deep linear region, thereby reducing the risk of the MOSFET deviating from the deep linear region due to transient response, and thus ensuring the normal operation of the circuit system.

[0045] Furthermore, such as Figure 5As shown, the current mirror module 212 includes: a third transistor Mp0, a fourth transistor Mpc0, a fifth transistor Mp1, a sixth transistor Mpc1, and a first resistor Rp. The first terminals of the third transistor Mp0 and the fifth transistor Mp1 are both coupled to the power supply voltage VDD. The second terminal of the third transistor Mp0 is coupled to the first terminal of the fourth transistor Mpc0, and the second terminal of the fifth transistor Mp1 is coupled to the first terminal of the sixth transistor Mpc1. The control terminals of the third transistor Mp0 and the fifth transistor Mp1 are coupled to the first node C. The second terminal of the fourth transistor Mpc0 is coupled to one end of the first resistor Rp, and the second terminal of the sixth transistor Mpc1 is coupled to the first voltage clamping module 213 and outputs a first current signal Ib1. The control terminals of the fourth transistor Mpc0 and the sixth transistor Mpc1 are coupled to the second node D. The first node C is also coupled to one end of the first resistor Rp, and the second node D is also coupled to the other end of the first resistor Rp. The other end of the first resistor Rp is also coupled to a current source 211. It should be noted that in this embodiment, the current mirror module 212 is a cascode current mirror. In addition, the width-to-length ratios of the third transistor Mp0 and the fifth transistor Mp1 are the same, as are the width-to-length ratios of the fourth transistor Mpc0 and the sixth transistor Mpc1.

[0046] like Figure 5 As shown, the first voltage clamping module 213 includes a seventh transistor Mnb1, wherein the first terminal of the seventh transistor Mnb1 is coupled to one terminal of the current source 211, the first terminal of the first transistor Mn1, and the ground terminal GND, respectively; the second terminal of the seventh transistor Mnb1 is coupled to the current mirror module 212 to receive the first current signal Ib1; and the control terminal of the seventh transistor Mnb1 is coupled to the second terminal of the seventh transistor Mnb1 and the control terminal of the first transistor Mn1, respectively.

[0047] like Figure 5 As shown, the current mirror module 221 includes an eighth transistor Mp(N+1) and a ninth transistor Mpc(N+1). The first terminal of the eighth transistor Mp(N+1) is coupled to the power supply voltage VDD, and the second terminal of the eighth transistor Mp(N+1) is coupled to the first terminal of the ninth transistor Mpc(N+1). The control terminal of the eighth transistor Mp(N+1) is coupled to the first node C. The second terminal of the ninth transistor Mpc(N+1) is coupled to the second voltage clamping module 222, outputting a second current signal Ib(N+1). The control terminal of the ninth transistor Mpc(N+1) is coupled to the second node D. It should be noted that the third transistor Mp0 and the eighth transistor Mp(N+1) have the same width-to-length ratio, and the fourth transistor Mpc0 and the ninth transistor Mpc(N+1) also have the same width-to-length ratio.

[0048] like Figure 5As shown, the second voltage clamping module 222 includes a tenth transistor Mnb(N+1), wherein the first terminal of the tenth transistor Mnb(N+1) is coupled to the output terminal of the reverse conduction suppression module 223, the second terminal of the tenth transistor Mnb(N+1) is coupled to the current mirror module 221 to receive the second current signal Ib(N+1), and the control terminal of the tenth transistor Mnb(N+1) is coupled to the second terminal of the tenth transistor Mnb(N+1) and the control terminal of the second transistor Mn(N+1), respectively. It should be noted that the width-to-length ratios of the first transistor Mn1, the second transistor Mn(N+1), the seventh transistor Mnb1, and the tenth transistor Mnb(N+1) are the same.

[0049] like Figure 5 As shown, the reverse conduction suppression module 223 is a buffer buffer BufferN, which includes an amplifier AN. The non-inverting input terminal of the amplifier AN is coupled to the first terminal of the second transistor Mn(N+1), the inverting input terminal of the amplifier AN is coupled to the output terminal of the amplifier AN, and the output terminal of the amplifier AN, as the output terminal of the reverse conduction suppression module 223, is also coupled to the first terminal of the tenth transistor Mnb(N+1).

[0050] Additionally, it should be noted that when the bottom-level controllable module 210 and at least one extended-layer controllable module 220 are superimposed and fused together in series with the bottom-level controllable resistor and the extended-layer controllable resistor, the voltage input terminal of the extended-layer controllable module 220 is coupled to the voltage output terminal of the bottom-level controllable module 210 or to the voltage output terminal of the preceding extended-layer controllable module 220. Specifically, if the extended-layer controllable module 220 is the first module to be superimposed and fused, then the voltage input terminal of the extended-layer controllable module 220 is coupled to the voltage output terminal of the bottom-level controllable module 210; if the extended-layer controllable module 220 is not the first module to be superimposed and fused, then the voltage input terminal of the extended-layer controllable module 220 is coupled to the voltage output terminal of the preceding extended-layer controllable module 220.

[0051] The voltage output terminal of the extended layer controllable module 220 is coupled to the voltage input terminal of the subsequent extended layer controllable module 220 or serves as the voltage output terminal of the controllable resistor circuit based on a deep linear region MOSFET. Specifically, if the extended layer controllable module 220 is not the last extended layer controllable module 220 in the stacked and fused configuration, then the voltage output terminal of the extended layer controllable module 220 is coupled to the voltage input terminal of the subsequent extended layer controllable module 220; if the extended layer controllable module 220 is the last extended layer controllable module 220 in the stacked and fused configuration, then the voltage output terminal of the extended layer controllable module 220 serves as the voltage output terminal of the controllable resistor circuit 200 based on a deep linear region MOSFET.

[0052] Furthermore, in order to illustrate the working principle of the controllable resistor circuit 200 based on a deep linear region MOS transistor in the embodiments of this disclosure. Figure 6 The present paper provides an exemplary circuit diagram of a controllable resistor circuit 200 based on a deep linear region MOSFET. Figure 6 This refers to the case where the bottom-level controllable module 210 and an extended-layer controllable module 220 are superimposed and merged. When there is only one extended-layer controllable module 220, N=1. During the superposition and fusion process, that is... Figure 5 The C and D nodes in the left and right boxes are coupled accordingly, and the V1 node in the left box is coupled to the V(N+1)', i.e., V2', in the right box. Figure 6 In the process, the current Ib2 output by Mp2 and Mpc2 flows into Mnb2, generating a voltage Vgs. Mnb2 (Gate-source voltage of Mnb2). The gates of Mnb2 and Mn2 are connected, and Buffer1 is connected in series between the sources of Mnb2 and Mn2. The gain of amplifier A1 in Buffer1 is high enough (>60dB) that V1 is approximately equal to V1n, therefore Vgs Mnb2 =Vgs Mn2 (Gate-source voltage of Mn2). While directly connecting the sources of Mnb2 and Mn2 can guarantee Vgs... Mnb2 =Vgs Mn2 However, when the V2 potential approaches GND, the current Ib2 cannot be completely released through Mn1, causing Mn2 to conduct in reverse. This will affect the use of the active resistor. Buffer1 can discharge the current Ib2 flowing into Mnb2 to GND, preventing Mn2 from conducting in reverse. Mp2 and Mpc2 mirror the current Ib, ensuring Ib = Ib1 = Ib2. Since Mnb1, Mn1, Mnb2, and Mn2 have the same width-to-length ratio, Vgs... Mnb1 =Vgs Mn1 =Vgs Mnb2 =Vgs Mn2 Since the current flowing through Mn2 and Mn1 is the same, their operating states are the same. Figure 1 or Figure 3 The principle is the same as that of the active resistor of a MOSFET operating in the deep linear region. The active resistance from V2 to GND can be denoted as R(N+1), or R2. The resistance value of R2 is:

[0053]

[0054] Where R1 is the active resistance from V1 to GND, μ n C ox Where W is a constant, L is the width of MOSFETs Mn2 and Mn1, and Vgs is a constant. Mn1 Vgs Mn2Vth is the gate-source voltage of Mn1 and Mn2, and Vth is the turn-on voltage of Mn1 and Mn2.

[0055] According to formula (4), R2 = 2 * R1, V2 = 2 * V1. Therefore, it is only necessary to satisfy V2 < [0.2(Vgs)]. Mn1 -Vth)+0.2(Vgs Mn2 -Vth)]=2V Line V Line yes Figure 1 or Figure 3 The cutoff voltage of the deep linear region of the MOSFET in the mid-to-deep linear region, i.e., the cutoff voltage of the deep linear region of the MOSFET operating in the deep linear region in the bottom controllable module 210, allows both Mn1 and Mn2 to operate in the deep linear region. Since resistor R2 can be approximated as linear, the range of the deep linear region can be doubled, and the active resistor value can be doubled as well. Vgs can be adjusted simultaneously by controlling Ib. Mn1 Vgs Mn2 The size of the resistor determines the value of resistor R2. Figure 6 The controllable resistor circuit 200 based on a deep linear region MOSFET is equivalent to a controllable resistor based on a double-layer deep linear region MOSFET. From the above... Figure 6 Analysis of the embodiments shows that after the bottom controllable module 210 and the extended layer controllable module 220 are superimposed and merged, the range of the deep linear region is doubled and the active resistor value is doubled.

[0056] Furthermore, Figure 7 The paper also provides an exemplary circuit diagram of another controllable resistor circuit 200 based on a deep linear region MOSFET. Figure 7 This refers to the case where the bottom controllable module 210 and two extended layer controllable modules 220 are superimposed and merged. When there are two extended layer controllable modules 220, N=1, N=2, N=1 is the first extended layer controllable module 220, and N=2 is the second extended layer controllable module 220. During superposition and fusion, the C nodes and D nodes in the first and second extended layer controllable modules 220 are coupled to the corresponding C nodes and D nodes in the bottom controllable module 210. The voltage input terminal V2' of the first extended layer controllable module is coupled to node V1, and the voltage output terminal V2 of the first extended layer controllable module is coupled to the voltage input terminal V3' of the second extended layer controllable module. The voltage output terminal V3 of the second extended layer controllable module serves as the voltage output terminal of the controllable resistor circuit based on the deep linear region MOSFET. Figure 7 In the diagram, the active resistance from V3 to GND is denoted as R(N+1), or R3, and the resistance value of R3 is:

[0057]

[0058] According to formula (5), R3 = 3 * R1, V3 = 3 * V1. Therefore, it is only necessary to satisfy V3 ​​< [0.2(Vgs)]. Mn1 -Vth)+0.2(Vgs Mn2 -Vth)+0.2(Vgs Mn3 -Vth)]=3V Line By ensuring that Mn1, Mn2, and Mn3 all operate in the deep linear region, resistor R3 can be approximated as linear. Therefore, the range of the deep linear region can be doubled, and the active resistor value can be doubled as well. Vgs can be adjusted simultaneously by controlling Ib. Mn1 Vgs Mn2 Vgs Mn3 The size of the resistor determines the value of resistor R3. Figure 7 The controllable resistor circuit 200 based on deep linear region MOSFETs is equivalent to a controllable resistor based on three layers of deep linear region MOSFETs. From the above... Figure 7 Analysis of the embodiments shows that after the bottom controllable module 210 and the two extended layer controllable modules 220 are superimposed and merged, the range of the deep linear region is doubled and the active resistor value is doubled.

[0059] from Figure 6 and Figure 7 As can be seen in the embodiments, for each additional controllable module 220 of the extended layer superimposed and fused, the range of the deep linear region doubles, and the resistance value of the active resistor doubles. Here, "doubles" refers to... Figure 1 This refers to the controllable active resistor in the circuit. The double figure, including those in the aforementioned embodiments, is relative to... Figure 1 This refers to the controllable active resistor in the circuit. Theoretically, it can be used to... Figure 1 By superimposing and fusing N (N≥1) layers of MOSFETs operating in the deep linear region on a single-layer deep linear region MOSFET (i.e., fusing N extended layer controllable modules 220 on the bottom controllable module 210), the deep linear region range can be increased by N times, and the active resistance value can be increased by N times. Furthermore, Figure 8 An exemplary circuit diagram is provided, showing how N extended layer controllable modules 220 are integrated on the bottom controllable module 210 to obtain a controllable resistor based on an N+1 layer MOSFET operating in the deep linear region. Each additional extended layer controllable module 220 doubles the range of the deep linear region; therefore, the number of layers of stacked extended layer controllable modules 220 can be continuously increased to expand the range of the deep linear region and the active resistor value. Figure 9 This is a comparison chart of the controllable resistance of MOSFETs with different layer counts operating in the deep linear region. Figure 9 In the diagram, R1 represents a controllable resistor based on a MOSFET operating in the deep linear region, V Line R1 represents the deep linear region cutoff voltage based on a single MOSFET operating in the deep linear region; R2 represents a controllable resistor based on two MOSFETs operating in the deep linear region, 2V.Line R3 represents the deep linear region cutoff voltage of a two-layer MOSFET operating in the deep linear region; R4 represents the controllable resistor of a three-layer MOSFET operating in the deep linear region, 3V. Line R represents the deep linear region cutoff voltage of a MOSFET operating in the deep linear region based on a three-layer MOSFET; R(N+1) represents the controllable resistance of a MOSFET operating in the deep linear region based on the N+1 layer. Figure 9 As can be seen, the more layers there are, the larger the deep linear region becomes, and the larger the active resistor value becomes, and it increases exponentially. Therefore, it can greatly reduce the risk of the MOSFET deviating from the deep linear region during transient response, thereby ensuring the normal operation of the circuit system.

[0060] Finally, it should be noted that in practical applications, in addition to the N-type MOS transistors in the aforementioned embodiments, the first and second transistors can also be P-type MOS transistors, and the underlying principle is the same.

[0061] In summary, the controllable resistor circuit 200 based on the deep linear region MOSFET in this embodiment can increase the range of the deep linear region, reduce the risk of the MOSFET deviating from the deep linear region due to transient response, and ensure the normal operation of the circuit system.

[0062] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0063] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0064] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0065] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A controllable resistor circuit based on a deep linear region MOSFET, characterized in that, include: Low-level controllable modules and extended-level controllable modules, The underlying controllable module is configured to control the gate-source voltage of a first transistor operating in the deep linear region based on a constant current signal to regulate the first on-resistance of the first transistor, where the first on-resistance is an underlying controllable resistor. The underlying controllable module includes a current source, a current mirror module, a first voltage clamping module, and the first transistor. The current source is coupled between a ground terminal and the current mirror module and is configured to generate the constant current signal. The current mirror module is also coupled to a power supply voltage. The first voltage clamping module is configured to mirror the constant current signal and output a first current signal. The first voltage clamping module is also coupled to the ground terminal and the first transistor and is configured to receive the first current signal and clamp the gate-source voltage of the first transistor based on the first current signal. A first terminal of the first transistor is coupled to the ground terminal, a second terminal of the first transistor serves as the voltage output terminal of the underlying controllable module, and a control terminal of the first transistor is coupled to the first voltage clamping module. The extended layer controllable module is configured to control the gate-source voltage of the second transistor operating in the deep linear region based on the constant current signal to regulate the second on-resistance of the second transistor. The second on-resistance is an extended layer controllable resistor, and the resistance value of the extended layer controllable resistor is equal to the resistance value of the bottom layer controllable resistor. The extended layer controllable module includes: a current mirroring module, a second voltage clamping module, a reverse conduction suppression module, and the second transistor. The current mirroring module is coupled to the power supply voltage, the second voltage clamping module, and the bottom layer controllable module, and is configured to mirror the constant current signal to obtain a second current signal. The second voltage clamping module is also coupled to the second transistor and the reverse conduction suppression module, and is configured to receive the second current signal and clamp the gate-source voltage of the second transistor based on the second current signal. The reverse conduction suppression module is also coupled to the second transistor and is configured to prevent the second transistor from reverse conducting. The first terminal of the second transistor serves as the voltage input terminal of the extended layer controllable module, and the second terminal of the second transistor serves as the voltage output terminal of the extended layer controllable module. The bottom controllable module and at least one of the extended layer controllable modules are superimposed and fused together in such a way that the bottom controllable resistor and the extended layer controllable resistor are connected in series.

2. The controllable resistor circuit based on a deep linear region MOS transistor according to claim 1, characterized in that, The current mirror module includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first resistor. Wherein, the first terminal of the third transistor and the first terminal of the fifth transistor are both coupled to the power supply voltage, the second terminal of the third transistor is coupled to the first terminal of the fourth transistor, the second terminal of the fifth transistor is coupled to the first terminal of the sixth transistor, and the control terminal of the third transistor and the control terminal of the fifth transistor are coupled to the first node; The second terminal of the fourth transistor is coupled to one end of the first resistor, the second terminal of the sixth transistor is coupled to the first voltage clamping module and outputs the first current signal, and the control terminal of the fourth transistor and the control terminal of the sixth transistor are coupled to the second node; The first node is also coupled to one end of the first resistor, the second node is also coupled to the other end of the first resistor, and the other end of the first resistor is also coupled to the current source.

3. The controllable resistor circuit based on a deep linear region MOS transistor according to claim 2, characterized in that, The first voltage clamping module includes: a seventh transistor. The first terminal of the seventh transistor is coupled to one terminal of the current source, the first terminal of the first transistor, and the ground terminal, respectively. The second terminal of the seventh transistor is coupled to the current mirror module to receive the first current signal. The control terminal of the seventh transistor is coupled to the second terminal of the seventh transistor and the control terminal of the first transistor, respectively.

4. The controllable resistor circuit based on a deep linear region MOS transistor according to claim 2, characterized in that, The mirror current module includes: an eighth transistor and a ninth transistor. Wherein, the first terminal of the eighth transistor is coupled to the power supply voltage, the second terminal of the eighth transistor is coupled to the first terminal of the ninth transistor, and the control terminal of the eighth transistor is coupled to the first node; The second terminal of the ninth transistor is coupled to the second voltage clamping module and outputs the second current signal. The control terminal of the ninth transistor is coupled to the second node.

5. The controllable resistor circuit based on a deep linear region MOS transistor according to claim 4, characterized in that, The second voltage clamping module includes: a tenth transistor, The first terminal of the tenth transistor is coupled to the output terminal of the reverse conduction suppression module, the second terminal of the tenth transistor is coupled to the mirror current module to receive the second current signal, and the control terminal of the tenth transistor is coupled to the second terminal of the tenth transistor and the control terminal of the second transistor, respectively.

6. The controllable resistor circuit based on a deep linear region MOS transistor according to claim 5, characterized in that, The reverse conduction suppression module is a buffer, which includes an amplifier. The non-inverting input terminal of the amplifier is coupled to the first terminal of the second transistor, the inverting input terminal of the amplifier is coupled to the output terminal of the amplifier, and the output terminal of the amplifier, as the output terminal of the reverse conduction suppression module, is also coupled to the first terminal of the tenth transistor.

7. The controllable resistor circuit based on a deep linear region MOS transistor according to claim 6, characterized in that, The voltage input terminal of the extended layer controllable module is coupled to the voltage output terminal of the bottom layer controllable module or to the voltage output terminal of the previous stage extended layer controllable module; the voltage output terminal of the extended layer controllable module is coupled to the voltage input terminal of the next stage extended layer controllable module or serves as the voltage output terminal of the controllable resistor circuit based on the deep linear region MOS transistor.

8. The controllable resistor circuit based on a deep linear region MOS transistor according to claim 7, characterized in that, The first transistor is a P-type MOS transistor or an N-type MOS transistor, and the second transistor is a P-type MOS transistor or an N-type MOS transistor.

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