digital to analog converter circuit

Abstract

Embodiments of this disclosure relate to digital-to-analog converter (DAC) circuits. According to one embodiment, a DAC includes: a W-2W current mirror comprising a plurality of first MOS transistors having a first width and a plurality of second MOS transistors having a second width twice the first width, wherein one of the plurality of second MOS transistors is coupled between the drains of adjacent MOS transistors of the plurality of first MOS transistors; and a body bias generator having a plurality of output nodes coupled to corresponding body nodes of the plurality of first MOS transistors, wherein the plurality of output nodes are configured to provide a voltage inversely proportional to temperature.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Italian application No. 102021000030134, filed on November 29, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This description relates to a current-controlled digital-to-analog converter (IDAC) that can be applied to memory devices such as phase-change memory (PCM) devices and / or general-purpose microcontrollers (GP MCUs). Background Technology

[0004] Phase-change memory (PCM) is a type of non-volatile memory (NVM), specifically a type of non-volatile random access memory (RAM). The material of conventional PCM cells is typically a chalcogenide alloy containing germanium (Ge), antimony (Sb), and tellurium (Te), known as GST (e.g., having the composition Ge₂Sb₂Te₅). Chalcogenide alloys can be reversibly and controlled to change phase (crystalline or amorphous) by a programming current passing through the memory cell and inducing a phase transition by appropriately heating the chalcogenide alloy (i.e., the memory storage element).

[0005] Traditionally, the heat generated by the programming current is used to rapidly heat and quench the alloy, making it amorphous (RESET state and RESET programming current pulse), or to hold the alloy within its crystallization temperature range for a period of time, thereby switching it to a (polycrystalline) crystalline state (SET state and SET programming current pulse). The use of two distinct phases of chalcogenide alloys in memory cells is based on the understanding that the crystalline phase has low resistance (e.g., according to the convention corresponding to logic 1 or SET state), while the amorphous phase has high resistance (e.g., according to the convention corresponding to 0 or RESET state).

[0006] Therefore, the SET and RESET operations of the storage cells in a phase-change memory are used to change the contents of the cell from "0" to "1" and vice versa, by applying a controlled programming current with a defined shape to allow the memory storage element to change its state from non-conductive (with high resistance) to conductive (with low resistance) and vice versa, by changing its morphology from amorphous to (polycrystalline) crystal and vice versa.

[0007] During the SET and RESET pulses, the programming current through the memory cell is expected to have a defined temporal behavior (e.g., a defined shape of the SET and / or RESET current pulses) to produce controlled temperature changes in the memory storage element. For example, Figure 1 The programming current I of the phase-change memory cell during the SET pulse. CELLAn example waveform diagram illustrating the expected behavior, which will produce a constant change in the temperature gradient and allow the storage element to switch to a polycrystalline state. The expected programming current I during the SET pulse. CELL The current increases rapidly from zero to a stable value I1, remains at that value for time interval T1P, and then slowly returns (e.g., drops) to zero at a constant rate of decrease (e.g., linearly) for time interval T1F. Therefore, driver circuits are typically used to inject the desired current into the memory storage element starting from a reference current generated by a current-controlled digital-to-analog converter.

[0008] Current-controlled digital-to-analog converters based on the “W-2W” architecture are commonly used in such applications because they occupy a small silicon area. The paper “W-2W Current Steering DAC for Programming Phase Change Memory” by Gupta, Shantanu Sen et al., 2009 IEEE Microelectronics and Electronic Devices Workshop (2009): 1-4, is an example of this traditional approach.

[0009] However, due to its topology, the W-2W IDAC circuit may suffer from systematic errors in some transistors that affect the architecture, and therefore may not be able to produce an output current pulse with the correct shape expected during the SET pulse (i.e., linear reduction).

[0010] Therefore, there is a need in the art for an improved W-2W current-controlled digital-to-analog converter capable of generating output current pulses with desired shape and linearity. Summary of the Invention

[0011] In one or more embodiments, the circuit includes a diode-connected MOS transistor having a drain terminal connected to an input node and a source terminal connected to a reference voltage node. The diode-connected MOS transistor is configured to transfer a reference current from the input node to the reference voltage node. A plurality of ordered mirror MOS transistors have corresponding gate terminals connected to the gate terminals of the diode-connected MOS transistor and corresponding drain terminals alternately coupled to a first current node or a second current node according to a plurality of corresponding ordered control signals. A first mirror MOS transistor of the plurality of ordered mirror MOS transistors has a source terminal directly connected to the reference voltage node. A plurality of current-controlled MOS transistors have corresponding gate terminals connected to the gate terminals of the diode-connected MOS transistor, and each current-controlled MOS transistor is arranged between the source terminals of two consecutive mirror MOS transistors of the plurality of mirror MOS transistors. Both the diode-connected MOS transistor and the mirror MOS transistors have the same channel size, and the current-controlled MOS transistors all have the same channel size. The channel of the current-controlled MOS transistor has the same length and twice the width of the channel of the diode-connected MOS transistor. Mirror MOS transistors whose source terminals are not directly connected to the reference voltage node have corresponding body terminals configured to receive one or more compensation signals.

[0012] Therefore, one or more embodiments can help compensate for the body effect of mirrored MOS transistors in a W-2W current-controlled digital-to-analog converter.

[0013] In one or more embodiments, one or more compensation signals are linearly dependent on temperature.

[0014] In one or more embodiments, the circuit includes a compensation circuit configured to generate the one or more compensation signals. The compensation circuit includes a current generator device proportional to absolute temperature configured to generate a compensation voltage signal; a voltage divider circuit; and a buffer stage configured to provide the compensation voltage signal to the voltage divider circuit. One or more compensation signals are generated at one or more intermediate nodes of the voltage divider circuit.

[0015] In one or more embodiments, a current generator device proportional to absolute temperature includes a first p-channel MOS transistor and a first n-channel MOS transistor arranged in series between a power supply voltage node and a reference voltage node; and a second p-channel MOS transistor and a second n-channel MOS transistor arranged in series between the power supply voltage node and the reference voltage node. The first n-channel MOS transistor has a source terminal coupled to the reference voltage node, a drain terminal coupled to the drain terminal of the first p-channel MOS transistor, and a gate terminal configured to receive a bandgap reference voltage. The first p-channel MOS transistor has a source terminal coupled to the power supply voltage node and a gate terminal coupled to its drain terminal. The second p-channel MOS transistor has a source terminal coupled to the power supply voltage node, a drain terminal coupled to the drain terminal of the second n-channel MOS transistor, and a gate terminal coupled to the gate terminal of the first p-channel transistor. The second n-channel MOS transistor has a source terminal coupled to the reference voltage node and a gate terminal coupled to its drain terminal. A compensation voltage signal is generated at the gate terminal of the second n-channel MOS transistor.

[0016] In one or more embodiments, the buffer stage includes an amplifier circuit having an output terminal coupled to a voltage divider circuit, a non-inverting input terminal configured to receive a compensation voltage signal, and an inverting input terminal coupled to its output terminal.

[0017] In one or more embodiments, a mirrored MOS transistor whose source terminal is not directly connected to a reference voltage node may include (e.g., a tri-well n-channel MOS transistor).

[0018] In one or more embodiments, the source terminal of the last mirror MOS transistor in a plurality of ordered mirror MOS transistors is directly connected to the penultimate mirror MOS transistor in the plurality of ordered mirror MOS transistors.

[0019] In one or more embodiments, the last mirror MOS transistor and the penultimate mirror MOS transistor have corresponding body terminals configured to receive the same compensation signal.

[0020] In one or more embodiments, the drain terminal of the last mirror MOS transistor in a plurality of ordered mirror MOS transistors and the drain terminal of the penultimate mirror MOS transistor in a plurality of ordered mirror MOS transistors are stably coupled to a second current node.

[0021] In one or more embodiments, the drain terminals of a plurality of ordered mirrored MOS transistors are alternately coupled to a first current node or a second current node via respective switches that can be activated according to a corresponding ordered control signal.

[0022] In one or more embodiments, the diode-connected MOS transistor, the plurality of mirrored MOS transistors, and the plurality of current-controlled MOS transistors include, for example, an n-channel transistor.

[0023] In one or more embodiments, the circuit includes a first output diode-connected MOS transistor and a second output diode-connected MOS transistor. The first output diode-connected MOS transistor has a drain terminal connected to a first current node and a source terminal connected to a power supply voltage node. The second output transistor has a drain terminal connected to a second current node and a source terminal connected to a power supply voltage node. Attached Figure Description

[0024] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, wherein:

[0025] Figure 1 This is an exemplary waveform diagram showing the expected behavior of the programming current of the phase-change memory cell during the SET pulse;

[0026] Figure 2 This is a circuit diagram example of a current-controlled digital-to-analog converter (IDAC) based on a W-2W current mirror architecture;

[0027] Figure 3 It is by Figure 2 A waveform example illustrating the possible behavior of the programming current in the phase-change memory cell during the SET pulse generated by the DAC circuit;

[0028] Figure 4 This is a circuit diagram example of a current-controlled digital-to-analog converter (IDAC) based on a W-2W current mirror architecture according to one or more embodiments of this specification;

[0029] Figure 5 This is a circuit diagram example of a compensation circuit for a current-controlled digital-to-analog converter (IDAC) according to one or more embodiments of this specification; and

[0030] Figure 6 It is by Figure 5 The temperature-dependent voltage-temperature plot of one or more compensation signals generated by the compensation circuit. Detailed Implementation

[0031] In the following description, one or more specific details are shown to provide a thorough understanding of examples of embodiments described herein. Embodiments may be obtained without one or more specific details, or using other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been shown or described in detail so as not to obscure certain aspects of the embodiments.

[0032] The references to "embodiment" or "an embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to an embodiment is included in at least one implementation. Therefore, phrases such as "in one embodiment" or "in one implementation" that may appear in one or more points of this specification do not necessarily refer to the same implementation. Furthermore, in one or more embodiments, particular configurations, structures, or features may be combined in any suitable manner.

[0033] The headings / references used herein are provided for convenience only and are not intended to limit the scope or range of protection of the embodiments.

[0034] In the accompanying drawings, similar parts or elements are indicated by similar reference / figure reference numerals unless the context otherwise indicates, and for the sake of brevity, the corresponding descriptions will not be repeated.

[0035] Some embodiments of the present invention relate to an improved current-controlled digital-to-analog converter based on a W-2W architecture. For example, such a current-controlled digital-to-analog converter can be applied to memory devices such as phase-change memory (PCM) devices and / or general-purpose microcontrollers (GP-MCUs).

[0036] Through the detailed description of the exemplary embodiments, one can first refer to Figure 2 , Figure 2 This is a circuit diagram example of a 7-bit current-controlled digital-to-analog converter (IDAC)20 based on the known W-2W current mirror architecture, such as that cited in the previously cited literature by Gupta et al.

[0037] A W-2W current mirror can be used to implement a binary weighted current-controlled DAC, for example, as a write driver circuit for programming phase-change memory. It relies on the understanding that if two metal-oxide-semiconductor field-effect transistors (MOSFETs) with the same width-to-length ratio (W / L) are connected in parallel, they behave as equivalent transistors with a size of 2W / L, while if connected in series, they behave as equivalent transistors with a size of W / 2L.

[0038] The W-2W IDAC circuit 20 includes a diode-connected main transistor N (e.g., an N-channel MOS transistor) configured to receive current I. REF The transistor has a drain terminal at / 2 and a source terminal coupled to the reference voltage node GND (or local ground). Transistor N is configured to carry a current I. REF / 2, Current I REFIt may be equal to 64μA. The W-2W IDAC circuit 20 includes a set of slave transistors T0, T1, M0, ..., M6 (e.g., n-channel MOS transistors), each having a corresponding gate terminal connected to the gate terminal of the master transistor N, such that the gate voltage in the master transistor N is supplied to the gate terminal of each of the slave transistors T0, T1, M0, ..., M6. The master transistor N and the slave transistors T0, T1, M0, ..., M6 all have the same channel dimensions (e.g., the same width-to-length ratio W / L, possibly having the same width W and the same length L). The source terminal of the first slave transistor M6 is directly connected to the reference voltage node GND, such that transistor M6 carries the current I carried by the master transistor N. REF / 2 The same current I6 (I6=I REF / 2). The source terminal of the second slave transistor M5 is connected to the source terminal of the first slave transistor M6 via the first current-controlled transistor Q6 (e.g., to the reference voltage node GND). The source terminal of the third slave transistor M4 is connected to the source terminal of the second slave transistor M5 via the second current-controlled transistor Q5, and so on until the penultimate (e.g., the eighth) slave transistor T1, which is connected to the penultimate (e.g., the seventh) slave transistor M0 via the last (e.g., the seventh) current-controlled transistor Q0. All current-controlled transistors Q6 through Q0 have the same channel size, having twice the width of transistors N, M6, ..., M0, T1, T0 (e.g., the current-controlled transistors may have the same width-to-length ratio of 2*W / L, possibly with the same width of 2*W and the same length of L). The gate terminals of all current-controlled transistors Q6 through Q0 are connected to the gate terminal of the master transistor N to receive the same gate voltage. The source terminal of the last (e.g., the ninth) slave transistor T0 can be directly connected to the source of the penultimate slave transistor T1.

[0039] exist Figure 2 In the arrangement shown, the current flowing through each of transistors M5, ..., M0, T1, T0 is arranged to pass through transistor Q6. Transistor Q6 seeks the current I provided by transistors M5 and Q5. REF / 2. Transistors M5 and Q5 have the same gate voltage, so the current is evenly distributed between the two paths in which these transistors reside. Therefore, transistor M5 carries a current I5 = I REF / 4. Similarly, transistor M4 carries a current I4 = I REF / 8, Transistor M3 carries a current I3 = I REF / 16, Transistor M2 carries current I2=I REF / 32, Transistor M1 carries current I1=I REF / 64, Transistor M0 carries current I0 = I REF / 128, and transistors T1 and T0 each carry a current I. T =I REF / 256.

[0040] like Figure 2 As shown, the first seven drain terminals of the current mirror from transistors (M6 to M0) can be selectively coupled to either the first node 22 or the second node 24 via corresponding switches (e.g., MOS transistors). For example, the drain terminal of transistor MX (where X ranges from 0 to 6) can be coupled via a corresponding control signal C. X The corresponding activated switch (e.g., the switch responds to the corresponding control signal C) X (Assertion and conduction) selectively couple to node 22, and can be controlled by the corresponding control signal C. X The complement activated other corresponding switch is selectively coupled to node 24 (e.g., another switch responds to the corresponding control signal C). X The assertion is canceled, i.e., in response to the two's complement control signal. (Assert and guide).

[0041] like Figure 2 As shown, the drain terminals of transistors T0 and T1 can be coupled to the power supply voltage V through corresponding normally open switches (e.g., MOS n-channel transistors, whose gate terminals are coupled to the power supply voltage V). CC The transistors T0 and T1 are always coupled to node 24. Alternatively, normally off switches (e.g., MOS n-channel transistors with their gate terminals coupled to the reference voltage node GND) can be placed between the drain terminals of transistors T0 and T1 and node 22 to improve circuit matching.

[0042] Control signals C0, ..., C6 represent the digital input signals of the W-2W IDAC circuit (e.g., each control signal provides one bit of the 7-bit digital signal C, where C0 is the least significant bit (LSB) and C6 is the most significant bit (MSB)). The analog output signal (e.g., output current) of the W-2W IDAC circuit is provided by a single-ended current flowing through node 22. For example, the output current can be output from the IDAC circuit 20 via a PMOS current mirror coupled to node 22, such as the current coupled to node 22 and the supply voltage V. CC The p-channel MOS transistor 26 is shown with a diode connection between it and the diode. The current path through node 24 (and through coupling between node 24 and the supply voltage V) is shown. CCThe p-channel MOS transistor 28, connected by a diode between the transistors, provides a DC current path for transistors M5 through M0, and ensures that the current flowing through the IDAC structure is constant, independent of the values ​​of the input digital signals C0, ..., C6. This also ensures that the drain terminals of transistors M5 through M0 are correctly polarized when the input digital signals are switched to change the IDAC current value, thereby improving the accuracy and settling time of the IDAC output current.

[0043] The settings of transistors T0 and T1 essentially create an offset in the output current signal, which can advantageously avoid operating with zero output current when the input digital signal C (i.e., the set of control signals C0, ..., C6) is equal to zero.

[0044] In an exemplary 7-bit W-2W IDAC circuit based on the architecture considered herein, the current I 0010000 (That is, the output current corresponding to the digital input signal C = 0010000) is expected to be equal to I. REF / 8, therefore expected to be higher than I 0001111 =I REF / 16+I REF / 32+I REF / 64+I REF / 128 First-year factor I REF / 128 times. This situation occurs if the source voltages of all transistors M6, ..., M0, T1, T0 are the same, resulting in the same body-source voltages for all transistors. However, due to the presence of transistors Q6, ..., Q0 and the current flowing within them, the source voltage V of transistors M6, ..., M0, T1, T0 varies. S They may not be the same. Specifically, V S T0 = ​​V S T1>V S M0>V S M1>V S M2>V S M3>V S M4>V S M5>V S Therefore, compared to the body-source voltages of transistors M6 and N, the magnitude of the current flowing through transistors M5, ..., M0, T1, T0 may be affected by the body effect. Specifically, the threshold voltages of transistors M5, ..., M0, T1, T0 can be altered by the body effect, thereby changing the corresponding drain-source currents.

[0045] For example, Figure 3 It is by Figure 2 The programming current I of the phase-change memory cell during the SET pulse generated by the W-2W IDAC circuit shown is... CELLA waveform diagram showing the possible behaviors (e.g., shape) during the current drop period (time period t). 1F Due to the operation of the W-2WIDAC circuit described above, undesirable step transitions may occur (e.g., when transitioning from C=0010000 to C=0001111). This may affect the programming current I. CELL The shape of the object affects the temperature gradient applied to the memory storage element.

[0046] Therefore, in such Figure 4 In one or more embodiments shown, the body (or body) terminals of transistors M5, ..., M0, T1, T0 can be supplied with their respective compensation signals V5, ..., V0, V... 00 Control, and corresponding compensation signals, help mitigate (e.g., compensate) body effects. Transistors T1 and T0 can receive the same compensation signal V at their body terminals. 00 Because their source terminals are directly coupled to each other and receive the same voltage (i.e., they can be affected by the body effect to the same extent).

[0047] In one or more embodiments, the compensation signals V5, ..., V0, V 00 They can be different from each other. In some embodiments, transistors M5, ..., M0, T1, T0 can be divided into subsets, and each subset can receive the same compensation signal. In some embodiments, the same compensation signal can be provided to all transistors M5, ..., M0, T1, T0.

[0048] In one or more embodiments, the slave transistors M5, ..., M0, T1, T0 can therefore be designed to provide accessible and selectively controllable body terminals. For example, in one or more embodiments, the slave transistors M5, ..., M0, T1, T0 may include or be composed of triple-well NMOS transistors. In a triple-well NMOS transistor, the P-well of the transistor is embedded in a deep N-well to form an isolation body from the P-substrate. This isolates the body from the substrate and allows the transistor body and the deep N-well to be biased separately.

[0049] In one or more embodiments, the magnitude of the bulk effect acting on the slave transistors M5, ..., M0, T1, T0 can depend on temperature. In particular, at high temperatures (e.g., 140°C), the bulk effect can be almost entirely compensated for by the temperature itself, thus the output current generated by the W-2W IDAC circuit 20 has the desired shape. At low temperatures (e.g., -40°C), the bulk effect may not be compensated, and the output current may not have the desired shape, such as... Figure 3 As shown, when from I 0010000 Switch to I 0001111 At this time, a step or inflection point will be generated in the output current. Therefore, in one or more embodiments, the compensation signals V5, ..., V0, V00 The magnitude of the compensation may depend on the temperature in order to provide strong compensation at low temperatures and mild compensation at high temperatures (e.g., reducing to zero compensation).

[0050] Figure 5 This is a circuit diagram example of a possible implementation of the compensation circuit 50, which is configured as follows: Figure 4 The W-2W IDAC circuit 20 shown generates one or more compensation signals V5, ..., V0, V 00 The compensation signal depends on the temperature.

[0051] The compensation circuit 50 may include a current generator device that is inversely proportional to absolute temperature (IPTAT), configured to generate a voltage signal NBIAS that decreases (e.g., linearly) with respect to temperature. Figure 6 As shown in the voltage-temperature diagram, the compensation circuit 50 may include a circuit arranged in series with an n-channel MOS transistor 504 at the supply voltage V. CC A p-channel MOS transistor 502 is connected between the power supply voltage node 506 and the reference voltage node GND. Transistor 504 may have a source terminal coupled to the reference voltage node GND, a drain terminal coupled to the drain terminal of transistor 502, and a gate terminal configured to receive the bandgap reference voltage VBG.

[0052] Transistor 502 may have a source terminal coupled to power supply voltage node 506, a drain terminal coupled to the drain terminal of transistor 504, and a gate terminal coupled to its drain terminal (i.e., it may be in a diode-connected configuration). Compensation circuit 50 may also include a p-channel MOS transistor 508 arranged in series with n-channel MOS transistor 510 between power supply voltage node 506 and reference voltage node GND. Transistor 508 may have a source terminal coupled to power supply voltage node 506, a drain terminal coupled to the drain terminal of transistor 510, and a gate terminal coupled to the gate terminal of transistor 502 (e.g., in a current mirror configuration of transistor 502). Transistor 510 may have a source terminal coupled to reference voltage node GND, a drain terminal coupled to the drain terminal of transistor 508, and a gate terminal coupled to the drain terminal (i.e., it may be in a diode-connected configuration). Therefore, a current mirror configuration may be generated at the gate terminal of transistor 510. Figure 6 The signal NBIAS shown is temperature-dependent (e.g., linear).

[0053] The compensation circuit 50 may further include a voltage buffer circuit 512 having a non-inverting input configured to receive the signal NBIAS (e.g., coupled to the gate terminal of transistor 510) and an inverting input coupled to the output node 514 of the voltage buffer 512. The buffer 512 may include or be composed of an operational amplifier. A voltage divider circuit 516 (e.g., a resistive voltage divider or resistive ladder) may be coupled between the output node 514 of the voltage buffer 512 and the reference voltage node GND. Therefore, the voltage buffer 512 decouples the gate and drain terminals of transistor 510 (NBIAS node) from the voltage divider circuit 516 and provides current to the voltage divider circuit 516.

[0054] Therefore, one or more compensation signals V5, ..., V0, V 00 This can be provided at one or more intermediate nodes of the resistor divider circuit 516 to supply power to the body terminals of transistors M5, ..., M0, T1, T0 in the W-2W IDAC circuit 20, such as... Figure 4 As shown. Specifically, the voltage V used to bias the body of transistors T1 and T0. 00 The voltage V0 can be higher than the body voltage V0 used to bias transistor M0, the voltage V0 can be higher than the body voltage V1 used to bias transistor M1, the voltage V1 can be higher than the body voltage used to bias transistor M2, and so on until the body voltage V5 used to bias transistor M5 is the lowest voltage.

[0055] It should be understood that Figure 5 The compensation circuit 50 shown is only used to generate compensation signals V5, ..., V0, V 00 This is one example of many possible circuits. In alternative embodiments, other IPTAT current and voltage generators known in the art can be used to generate IPTAT voltages or currents and provide corresponding scaled outputs.

[0056] Therefore, in Figure 5 In the compensation circuit 50 shown, the IPTAT generator can be used to generate a... Figure 6 The temperature-dependent curve for the signal NBIAS is shown. At low temperatures (e.g., -40°C), the IPTAT current flowing through transistors 502 and 504 is higher than at high temperatures (e.g., 140°C). Therefore, the voltage signal NBIAS is higher at -40°C and lower at 140°C (e.g., the signal NBIAS may decrease linearly with temperature). The slope of the signal NBIAS (i.e., its temperature dependence coefficient) can be changed by altering the channel dimensions (width W and length L) of transistor 510. The signal NBIAS is replicated at the output node 514 of voltage buffer circuit 512, which supplies power to voltage divider 516 to generate the desired compensation signals V5, ..., V0, V... 00For example, when the same compensation signal is provided to all transistors M5, ..., M0, T1, T0, it can be generated at the midpoint between resistors R1 and R2 in the voltage divider circuit 516.

[0057] In one or more embodiments, one or more temperature-dependent compensation signals V5, ..., V0, V1, T0 are applied to the body (or body terminal) of transistors M5, ..., M0, T1, T0. 00 This can help compensate for the bulk effects of these transistors, thereby allowing the generation of current pulses with the (linear) behavior desired for programming the memory cells of the phase-change memory, while utilizing the silicon low region of the W-2WIDAC circuit architecture.

[0058] Without prejudice to the fundamental principles and without departing from the scope of protection, the details and embodiments may vary significantly from what has been described by way of example only.

[0059] The scope of protection is determined by the appended claims.

Claims

1. A digital-to-analog converter circuit, comprising: A diode-connected MOS transistor having a drain terminal connected to an input node and a source terminal connected to a reference voltage node, the diode-connected transistor being configured to transfer a reference current from the input node to the reference voltage node; A plurality of ordered mirror MOS transistors have corresponding gate terminals connected to the gate terminals of the diode-connected MOS transistors, and corresponding drain terminals that can be alternately coupled to a first current node or a second current node according to a plurality of corresponding ordered control signals, wherein the first mirror MOS transistor of the plurality of ordered mirror MOS transistors has a source terminal directly connected to the reference voltage node; as well as A plurality of current-controlled MOS transistors have corresponding gate terminals connected to the gate terminals of the diode-connected MOS transistors, wherein each current-controlled MOS transistor is arranged between the source terminals of two consecutive mirrored MOS transistors in the plurality of ordered mirrored MOS transistors, wherein The diode-connected MOS transistor and the plurality of ordered mirrored MOS transistors all have the same channel size. All of the multiple current-controlled MOS transistors have the same channel size. The channels of the plurality of current-controlled MOS transistors have the same length and twice the width as the channels of the MOS transistors connected to the diode, and The plurality of ordered mirrored MOS transistors having source terminals not directly connected to the reference voltage node have corresponding body terminals configured to receive one or more compensation signals having corresponding values ​​that decrease with increasing temperature.

2. The digital-to-analog converter circuit according to claim 1, wherein the one or more compensation signals are linearly dependent on temperature.

3. The digital-to-analog converter circuit of claim 1, further comprising a compensation circuit configured to generate the one or more compensation signals, the compensation circuit comprising: A current generator device that is inversely proportional to absolute temperature is configured to generate a compensation voltage signal that decreases linearly as the temperature increases. Voltage divider circuit; as well as A buffer stage is configured to provide the compensation voltage signal to the voltage divider circuit. The one or more compensation signals are generated at one or more intermediate nodes of the voltage divider circuit.

4. The digital-to-analog converter circuit according to claim 3, wherein the current generator device inversely proportional to absolute temperature comprises: The first p-channel MOS transistor and the first n-channel MOS transistor are connected in series between the power supply voltage node and the reference voltage node; as well as A second p-channel MOS transistor and a second n-channel MOS transistor are connected in series between the power supply voltage node and the reference voltage node, wherein The first n-channel MOS transistor has a source terminal coupled to the reference voltage node, a drain terminal coupled to the drain terminal of the first p-channel MOS transistor, and a gate terminal configured to receive a bandgap reference voltage. The first p-channel MOS transistor has a source terminal coupled to the power supply voltage node and a gate terminal coupled to its drain terminal. The second p-channel MOS transistor has a source terminal coupled to the power supply voltage node, a drain terminal coupled to the drain terminal of the second n-channel MOS transistor, and a gate terminal coupled to the gate terminal of the first p-channel MOS transistor. The second n-channel MOS transistor has a source terminal coupled to the reference voltage node and a gate terminal coupled to its drain terminal, and The compensation voltage signal is generated at the gate terminal of the second n-channel MOS transistor.

5. The digital-to-analog converter circuit of claim 3, wherein the buffer stage includes an amplifier circuit having an output terminal coupled to the voltage divider circuit, a non-inverting input terminal configured to receive the compensation voltage signal, and an inverting input terminal coupled to its output terminal.

6. The digital-to-analog converter circuit of claim 1, wherein the mirrored MOS transistors among the plurality of ordered mirrored MOS transistors having source terminals not directly connected to the reference voltage node comprise tri-well n-channel MOS transistors.

7. The digital-to-analog converter circuit according to claim 1, wherein the source terminal of the last mirror MOS transistor in the plurality of ordered mirror MOS transistors is directly connected to the source terminal of the penultimate mirror MOS transistor in the plurality of ordered mirror MOS transistors.

8. The digital-to-analog converter circuit of claim 7, wherein the last mirror MOS transistor and the penultimate mirror MOS transistor have corresponding body terminals configured to receive the same compensation signal.

9. The digital-to-analog converter circuit according to claim 1, wherein the drain terminal of the last mirror MOS transistor in the plurality of ordered mirror MOS transistors and the drain terminal of the penultimate mirror MOS transistor in the plurality of ordered mirror MOS transistors are stably coupled to the second current node.

10. The digital-to-analog converter circuit of claim 1, wherein the drain terminals of the plurality of ordered mirrored MOS transistors can be alternately coupled to the first current node or the second current node via corresponding switches that can be activated according to corresponding ordered control signals.

11. The digital-to-analog converter circuit of claim 1, wherein the diode-connected MOS transistor, the plurality of ordered mirror MOS transistors, and the plurality of current-controlled MOS transistors comprise n-channel transistors.

12. The digital-to-analog converter circuit of claim 1 further includes a first output diode-connected MOS transistor having a drain terminal connected to the first current node and a source terminal connected to the power supply voltage node, and a second output diode-connected MOS transistor having a drain terminal connected to the second current node and a source terminal connected to the power supply voltage node.

13. A digital-to-analog converter (DAC), comprising: The W-2W current mirror includes a plurality of first MOS transistors having a first width and a plurality of second MOS transistors having a second width twice the first width, wherein the second MOS transistors in the plurality of second MOS transistors are coupled between the drains of adjacent first MOS transistors in the plurality of first MOS transistors; as well as A body bias generator having a plurality of output nodes coupled to corresponding body nodes of the plurality of first MOS transistors, wherein the plurality of output nodes are configured to provide a voltage inversely proportional to temperature.

14. The DAC of claim 13, further comprising an output coupling network coupled to the output nodes of the plurality of first MOS transistors, the output coupling network being configured to selectively couple the output nodes of the plurality of first MOS transistors to the output nodes of the DAC according to a digital DAC input word.

15. The DAC of claim 13, wherein, The body bias generator includes: A voltage generator is configured to provide a reference voltage inversely proportional to temperature; and A resistor ladder, coupled to the output of the voltage generator, the resistor ladder including multiple taps, wherein the output nodes of the multiple output nodes of the body bias generator are coupled to the corresponding taps of the multiple taps.

16. The DAC of claim 15, wherein, The voltage generator includes: The input MOS transistor has a gate coupled to a reference voltage generator; A diode-connected MOS transistor has the following characteristics: A current mirror having an input coupled to the output node of the input MOS transistor and an output node coupled to the gate and drain of a diode-connected MOS transistor; and A voltage buffer is coupled between the gate and drain of the diode-connected MOS transistor and the resistor ladder.

17. The DAC of claim 13, wherein the voltage level of the voltage provided by the body bias generator and the temperature coefficient of the voltage provided by the body bias generator are selected to increase the linear behavior of the W-2W current mirror.

18. A method of operating a current digital-to-analog converter (IDAC) including a W-2W current mirror, the W-2W current mirror including a plurality of first MOS transistors having a first width and a plurality of second MOS transistors having a second width twice the first width, wherein the second MOS transistors of the plurality of second MOS transistors are coupled between the drains of adjacent first MOS transistors of the plurality of first MOS transistors, the method comprising: The body nodes of the plurality of first MOS transistors are biased with a plurality of corresponding bias voltages that are inversely proportional to temperature.

19. The method of claim 18, further comprising: Receive DAC input word; as well as The output branch of the W-2W current mirror is selected according to the DAC input word.

20. The method of claim 18, wherein biasing the body node comprises: Generate a first bias voltage that is inversely proportional to temperature; as well as The first bias voltage is applied to the resistor ladder.

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