A low latency, survivor path length automatic adjustment Viterbi decoding circuit

Abstract

The application discloses a low-latency, survivor path length automatic adjustment Viterbi decoding circuit, and belongs to the field of digital communication, which comprises a decoding control circuit, an interpolation circuit, a branch metric calculation circuit, a sum comparison selection circuit and a survivor path backtracking circuit. The decoding control circuit generates decoding circuit control information according to configuration; the interpolation circuit performs interpolation operation on soft bit data with a code rate of 2 / 3 or 3 / 4, so that the soft bit data is restored into soft bit data with a code rate of 1 / 2; the branch metric calculation circuit calculates branch metric values corresponding to four different outputs of soft bit data under a current node; the sum comparison selection circuit performs path metric calculation, comparison and selection, selects a survivor path and stores node information into an SRAM; and the survivor path backtracking circuit backtracks the survivor path and decodes a code word. The application can reduce circuit area, cope with burst data through a low-latency pipeline decoding structure, improve decoding speed and efficiency, and well cope with decoding scenes with variable packet length through dynamic survivor path adjustment.

Description

Technical Field

[0001] This invention relates to the field of digital communication technology, and in particular to a Viterbi decoding circuit with low latency and automatic adjustment of survival path length. Background Technology

[0002] In digital communication, error-correcting codes (i.e., error control techniques) are an effective means to improve the reliability of signal transmission and play an increasingly important role. Error-correcting codes mainly include block codes and convolutional codes. Under the same code rate and encoder complexity, convolutional codes outperform block codes. Decoding methods for convolutional codes mainly include algebraic decoding and probabilistic decoding. Algebraic decoding is based on the algebraic structure of the code; while probabilistic decoding not only relies on the algebraic structure of the code but also utilizes the statistical characteristics of the channel, fully leveraging the characteristics of convolutional codes to achieve a very low decoding error probability. The design of convolutional code decoders begins with high-performance complex decoders. For the initial sequence decoding in probabilistic decoding, the decoding error probability can reach a very small level as the decoding constraint length increases. The Viterbi decoding algorithm is an optimal probabilistic decoding algorithm.

[0003] The Viterbi decoding algorithm, proposed by Viterbi in 1967, is a method for decoding convolutional codes. It is a maximum likelihood decoding algorithm based on a trellis graph of the code, meaning the decoder's output always produces the codeword with the maximum log-likelihood function. Omura proved that the Viterbi algorithm is equivalent to a dynamic programming solution to the shortest path problem through a weighted graph. When the constraints on the code are relatively small, the Viterbi algorithm is more efficient and faster than sequence decoding algorithms, and the decoder is also simpler. Therefore, since its inception, the algorithm has experienced extremely rapid development both theoretically and practically, and has been widely applied in various digital transmission systems, especially in satellite and mobile communications. Summary of the Invention

[0004] The purpose of this invention is to provide a Viterbi decoding circuit with low latency and automatic adjustment of the survival path length, so as to solve the problems of high latency, high buffering and fixed survival path in current Viterbi decoding circuits.

[0005] To address the aforementioned technical problems, this invention provides a low-latency Viterbi decoding circuit with automatic adjustment of the survival path length, comprising:

[0006] The decoding control circuit generates decoding circuit control information based on the configuration.

[0007] The interpolation circuit performs interpolation operations on soft bit data with a code rate of 2 / 3 and 3 / 4 to restore it to soft bit data with a code rate of 1 / 2.

[0008] The branch metric calculation circuit calculates the branch metric value corresponding to the soft bit data relative to the four different outputs at the current node;

[0009] The addition of a selection circuit performs path metric calculation, comparison, and selection, identifies surviving paths, and stores the node information of 64 paths into SRAM;

[0010] Survival path backtracking circuit, backtracks the survival path, and decodes the codeword.

[0011] In one embodiment, the decoding control circuit outputs the decoded packet length information based on the input encoded packet length information and encoding mode; dynamically adjusts the survival path length based on the encoding mode and the end signal of the encoded packet; and outputs the end signal of the decoded packet based on the end signal of the encoded packet and the working state of the decoding circuit.

[0012] In one implementation, the survival path length ranges from 8 to 48.

[0013] In one implementation, the interpolation circuit restores the interpolated single-channel soft-bit data into dual-channel data.

[0014] In one implementation, the branch metric calculation circuit calculates four possible branch metrics for the current node, where hard bit "0" is quantized into soft bit "5'b 01111", hard bit "1" is quantized into soft bit "5'b11111", and its complement is "5'b 10001".

[0015] In one embodiment, the add-compare-select circuit includes an add function, a compare function, and a select function; wherein,

[0016] The addition function is as follows: select the corresponding branch metric based on the current state of the node and the inputs 0 and 1, and add the selected branch metric value to the path metric value of the previous state as one of the path metric values ​​of the current state.

[0017] The comparison function is as follows: the current state generates two path metric values ​​based on the input, compares the two path metric values, selects the smaller path metric value as the unique metric value of the current state, and stores the current comparison result as the node information of the path in SRAM;

[0018] The selection function is as follows: compare the path metric values ​​of the 64 states under the current node, select the minimum metric value, and record the state with the minimum metric value as the Best State.

[0019] In one implementation, the surviving path backtracking circuit selects the Best State of the final node as the starting point for backtracking, reads the path node information in SRAM for backtracking, decodes 1 bit of codeword for each node, and packages and sends out the decoded codeword in single-byte format after the backtracking is completed.

[0020] The Viterbi decoding circuit with low latency and automatic adjustment of survival path length provided by this invention has the following beneficial effects:

[0021] (1) Low latency, pipelined decoding circuit structure and short survival path length greatly reduce the delay of the decoder circuit, better cope with data bursts, and effectively improve decoding speed and efficiency.

[0022] (2) Low resource consumption. The real-time characteristics of the decoding circuit pipeline mean that the soft bit data to be decoded does not require additional buffering. The shorter survival path length also means that less buffering is consumed by the path node information, which can greatly reduce resource consumption and reduce circuit area.

[0023] (3) The survival path length can be dynamically adjusted between 8 and 48, which can better solve the problems caused by different amounts of data being translated under different encoding forms and the inconsistent size of the data block at the end of the packet due to changes in packet length. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the overall architecture of a Viterbi decoding circuit with low latency and automatic adjustment of survival path length provided by the present invention;

[0025] Figure 2 This is a schematic diagram of the convolutional code encoding circuit;

[0026] Figure 3 This is a timing diagram of the entire Viterbi decoding circuit's data path;

[0027] Figure 4 This is a diagram illustrating the data structure of the data packet and the interpolation methods at different bitrates;

[0028] Figure 5 This is the state transition diagram corresponding to the convolutional encoder;

[0029] Figure 6 This is a schematic diagram of the node selection process. Detailed Implementation

[0030] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a low-latency, automatically adjustable Viterbi decoding circuit based on the present invention. The advantages and features of the invention will become clearer from the following description. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0031] This invention proposes a low-latency Viterbi decoding circuit with automatic adjustment of the survival path length, the overall architecture of which is as follows: Figure 1 As shown, it includes a decoding control circuit (CTRL), an interpolation circuit (INST), a branch metric calculation circuit (BM), an additive comparison circuit (ACS), and a survivor path backtracking circuit (TRB). The decoding control circuit outputs the decoded packet length information (DEC_LEN) based on the input encoded packet length information (ENC_LEN) and encoding mode (ENC_MODE). It dynamically adjusts the survival path length based on ENC_MODE and the end signal of the encoded packet (ENC_END), with the survival path length ranging from 8 to 48. It also outputs the end signal of the decoded packet based on the end signal of the encoded packet and the working state of the decoding circuit. The interpolation circuit performs interpolation operations on soft bit data with code rates of 2 / 3 and 3 / 4, restoring it to soft bit data with a code rate of 1 / 2, and then restores the interpolated single-channel soft bit data to dual-channel data. The branch metric calculation circuit calculates the Euclidean distance of the soft bit data (DAT_A, DAT_B) at the current node relative to four different outputs. In the four possible branch metrics of the current node, hard bit "0" is quantized into soft bit "5'b 01111", and hard bit "1" is quantized into soft bit "5'b 11111", with its complement "5'b". 10001”; The addition, comparison and selection circuit completes the calculation, comparison and selection of path metrics, selects the surviving path and stores the node information of 64 paths into SRAM; The surviving path backtracking circuit backtracks the surviving path and decodes the codeword.

[0032] like Figure 2 This is a convolutional code encoding circuit with 1-bit input, 2-bit output, and a constraint length of 7. The 2-bit output of the encoder is quantized into two 5-bit soft bits. The highest bit of the soft bit is the sign bit. The output "0" is quantized as "5'b01111", and the output "1" is quantized as "5'b11111", whose complement is "5'b10001".

[0033] like Figure 3This is a timing diagram of the entire Viterbi decoding circuit data path (1 / 2 code rate). A burst data block contains 64 5-bit soft bits of data. Through a pipelined structure of interpolation circuits, branch path calculation circuits, and adder-compare-selector circuits, the selection of the surviving path is completed with very low latency, and the node information of the 64 paths is recorded. Due to the characteristics of the Viterbi decoding algorithm, backtracking can only proceed after the selection of the surviving path and the recording of the node information of the 64 paths are completed. Therefore, a surviving path backtracking circuit cannot be added to the pipelined structure; however, shorter surviving paths can still significantly reduce decoding latency.

[0034] Figure 4 This diagram illustrates the data structure of the data packet and the interpolation methods at different bit rates. A0-A5 and B0-B5 represent the two soft bits quantized from the encoder output. Data at 3 / 4 and 2 / 3 bit rates requires interpolation by an interpolation circuit to restore it to 1 / 2 bit rate data. "5'b00000" is inserted at the corresponding positions. The interpolation method is as follows: Figure 4 As shown in (a) and (b). Figure 4 In the middle (d), the data structure of a single data packet is shown. The data packet size is 1-1024 soft bits, which is divided into several burst data blocks. Each data block is 64 soft bits in size, and the data block size at the end of the packet is 1-64 soft bits in size.

[0035] The branch metric calculation circuit calculates the branch metric value of the node. Specifically, the soft bit data DAT_A and DAT_B of the current node have four different branch metric values ​​when the node's state and input are unknown: BM_00, BM_01, BM_10, and BM_11. BM_00 represents the Euclidean distance of data B_A relative to "0_0", BM_01 represents the Euclidean distance of data B_A relative to "0_1", BM_10 represents the Euclidean distance of data B_A relative to "1_0", and BM_11 represents the Euclidean distance of data B_A relative to "1_1". Taking BM_11 as an example, the value of BM_11 is equal to the distance of B relative to "1" plus the distance of A relative to "1". The distance data of A / B relative to "0 / 1" are shown in Table 1.

[0036]

[0037] Table 1 shows the distance data of A / B relative to "0 / 1".

[0038] The decoding control circuit primarily handles the automatic adjustment of the survival path length. At different code rates, the amount of data recovered after interpolation from a 64-soft-bit data block varies, reflecting the different survival path lengths. Specifically, at a 1 / 2 code rate, the recovered data size is still 64 soft bits, yielding a 32-bit codeword; at a 3 / 4 code rate, the recovered data size is 96 soft bits, yielding a 48-bit codeword; and at a 2 / 3 code rate, the recovered data size is 80 soft bits (with 4 uninterpolated soft bits remaining), yielding a 40-bit codeword. The number of bits in the decoded codeword determines the survival path length. At a 1 / 2 bit rate, the survival path length is 32; at a 3 / 4 bit rate, the survival path length is 48; at a 2 / 3 bit rate, there are two different survival path lengths of 40 and 48. This is because after decoding a burst data block, there is still residual data. After decoding a 40-bit codeword from a burst data block, there will be 4 remaining uninterpolated soft bits. Two data blocks will be superimposed with the remaining 8 soft bits, which will be superimposed onto a third data block. The third data block will then have 72 soft bits. After interpolation recovery, a 48-bit codeword can be decoded, meaning the survival path length is 48. When the size of the data block at the end of the packet is less than 64, the survival path length is determined by the pulse of the ENC_EOF signal, and the survival path length is 1-48. The same processing method applies to all three bit rates.

[0039] The addition, comparison, and selection circuit completes the accumulation and comparison of path metrics, selects the surviving path based on the path metric value, and stores the node information of 64 paths into SRAM. Figure 5 This is the state transition diagram for the convolutional encoder. The next state and output are determined based on the input "0 / 1" and the current state. In the state transition diagram, the two states of the current node can only transition to the states not enclosed in parentheses in the next node. For example, node "S1(S..." 33 ")", states S1 and S 33 At the next node, the state can transition to either S2 or S3, but not to S... 34 and S 35State. Specifically, "addition" mainly involves selecting the corresponding branch metric based on the current node's state and the input (0 and 1), and accumulating the selected branch metric value to the path metric value of the previous state, as one of the path metric values ​​of the current state; "comparison" mainly involves comparing the two path metric values ​​generated by the current state based on the input, selecting the smaller path metric value as the unique metric value of the current state, and storing the current comparison result as the node information of the path in SRAM; "selection" mainly involves comparing the path metric values ​​of the 64 states under the current node, selecting the minimum metric value, and recording the state (BestState) containing the minimum metric value.

[0040] like Figure 6 The diagram illustrates the comparison node, taking a surviving path length of 48 as an example. Due to the coding characteristics of convolutional codes, after the comparison is completed (node ​​48), the branch metric will continue to input several zero values ​​into the comparison circuit, restoring the decoder state. SRAM stores the node information from node 7 to node 54. Regarding the Best State, two points need clarification: First, the path metric values ​​for all 64 states at node 1 are zero, and BEST STATE(BS_START) is 63 (the 64th state); second, BEST STATE(BS_END) at node 54 is also 63 after state restoration.

[0041] The survival path backtracking circuit completes the backtracking of the survival path, selects the Best State of the final node as the starting point of the backtracking, reads the path node information in SRAM for backtracking, backtracks from node 54 to node 7, decodes 1 bit of codeword for each node, and packages and sends out the decoded codeword in single-byte manner after the backtracking is completed.

[0042] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A Viterbi decoding circuit with low latency and automatic adjustment of survival path length, characterized in that, include: The decoding control circuit generates decoding circuit control information based on the configuration. The interpolation circuit performs interpolation operations on soft bit data with a code rate of 2 / 3 and 3 / 4 to restore it to soft bit data with a code rate of 1 / 2. The branch metric calculation circuit calculates the branch metric values ​​corresponding to the soft bit data relative to four different outputs at the current node. The soft bit data DAT_A and DAT_B at the current node have four different branch metric values ​​without knowing the node's state or input: BM_00, BM_01, BM_10, and BM_11. BM_00 represents the Euclidean distance of data B_A relative to "0_0", BM_01 represents the Euclidean distance of data B_A relative to "0_1", BM_10 represents the Euclidean distance of data B_A relative to "1_0", and BM_11 represents the Euclidean distance of data B_A relative to "1_1". The addition of a selection circuit performs path metric calculation, comparison, and selection, identifies surviving paths, and stores the node information of 64 paths into SRAM; The survival path backtracking circuit backtracks the survival path and decodes the codewords; among which... The decoding control circuit outputs the decoded packet length information based on the input encoded packet length information and encoding mode; dynamically adjusts the survival path length based on the encoding mode and the end signal of the encoded packet; and outputs the end signal of the decoded packet based on the end signal of the encoded packet and the working state of the decoding circuit. The decoding control circuit dynamically adjusts the survival path length as follows: At different code rates, the amount of data recovered after interpolation from a 64-soft-bit data block varies, reflecting the different survival path lengths. At a 1 / 2 code rate, the recovered data size is still 64 soft bits, resulting in a 32-bit codeword. At a 3 / 4 code rate, the recovered data size is 96 soft bits, resulting in a 48-bit codeword. At a 2 / 3 code rate, the recovered data size is 80 soft bits, with 4 uninterpolated soft bits remaining, resulting in a 40-bit codeword. The number of bits in the decoded codeword determines the survival path length. At a 1 / 2 code rate, the survival path length is 32; at a 3 / 4 code rate, it is 48; at a 2 / 3 code rate, there will be two different survival path lengths of 40 and 48, because there is still residual data after decoding a burst data block. A burst data block, after decoding 40... After the bit codeword is processed, the remaining 4 uninterpolated soft bits are used to add the remaining 8 soft bits to the two data blocks. These 8 soft bits are then added to the third data block, which will have 72 soft bits. After interpolation recovery, a 48-bit codeword is decoded, and the survival path length is 48. When the size of the data block at the end of the packet is less than 64, the survival path length is determined by the pulse of the ENC_EOF signal, and the survival path length is 1-48. The same processing method is used for all three code rates.

2. The low-latency, automatically adjustable Viterbi decoding circuit with surviving path length as described in claim 1, characterized in that, The length of the surviving path ranges from 8 to 48.

3. The low-latency, automatically adjustable Viterbi decoding circuit with surviving path length as described in claim 1, characterized in that, The interpolation circuit restores the interpolated single-channel soft-bit data into dual-channel data.

4. The low-latency, automatically adjustable Viterbi decoding circuit with surviving path length as described in claim 1, characterized in that, The branch metric calculation circuit calculates four possible branch metrics for the current node, where the hard bit "0" is quantized into the soft bit "5'b 01111", the hard bit "1" is quantized into the soft bit "5'b 11111", and its complement is "5'b 10001".

5. The low-latency, automatically adjustable Viterbi decoding circuit with surviving path length as described in claim 1, characterized in that, The adder-comparator-selector circuit includes an adder function, a comparer function, and a selector function; wherein... The addition function is as follows: select the corresponding branch metric based on the current state of the node and the inputs 0 and 1, and add the selected branch metric value to the path metric value of the previous state as one of the path metric values ​​of the current state. The comparison function is as follows: the current state generates two path metric values ​​based on the input, compares the two path metric values, selects the smaller path metric value as the unique metric value of the current state, and stores the current comparison result as the node information of the path in SRAM; The selection function is as follows: compare the path metric values ​​of the 64 states under the current node, select the minimum metric value, and record the state with the minimum metric value as the Best State.

6. The low-latency, automatically adjustable Viterbi decoding circuit with surviving path length as described in claim 1, characterized in that, The surviving path backtracking circuit selects the best state of the final node as the starting point for backtracking, reads the path node information in SRAM for backtracking, decodes 1 bit of codeword for each node, and packages and sends out the decoded codeword in single-byte format after backtracking is completed.

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