Signal timing synchronization method and synchronization apparatus

Abstract

The application discloses a signal timing synchronization method and a synchronization device, which are used for signal transmission between a source terminal and a terminal, and comprise the following steps: configuring a decoder to decode a source terminal signal, and decoding a source timing signal from the source terminal signal; configuring an FPGA chip to process the source timing signal, to perform gray scale stretching on an image signal, to count a generated odd-even field signal, to obtain a restored timing signal, and to output the restored timing signal; configuring an encoder to encode the restored timing signal, so that the restored timing signal is synchronized with the source terminal signal, and finally outputting; and providing a timing synchronization device based on the method, which can restore and synchronize the timing of a PAL video signal transmitted by a source terminal device and a terminal device, solves the problem of inconsistent timing of video signal transmission, and significantly improves the recognition of a video signal of the source terminal device by the terminal device.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology for special equipment, and more specifically, to a signal timing synchronization method and synchronization device for adjusting the timing of source and terminal signals in special equipment. Background Technology

[0002] Aviation equipment falls under the category of special equipment. The digital transformation of aviation equipment technology has consistently required modifications to both hardware and software across various aircraft models. For example, in a modification project for an airborne display and control system, the following difficulties arose:

[0003] 1) Directly modify the hardware of the display and control equipment, such as replacing the display device and the corresponding sensors. However, the compatibility of the improved equipment with other existing equipment in the whole machine also needs to be verified by a lot of experimental testing. Therefore, this method is difficult to modify and has a high cost.

[0004] 2) Retaining the existing display and control system presents new challenges. Taking the cockpit scenario as an example, a display and control system is commonly used to monitor the movement within the cabin and / or cargo hold. This system includes multiple source devices at various monitoring locations and terminal devices within the cockpit. PAL video signals are transmitted between these sources, and the terminal devices integrate the images captured by the multiple source devices. With older models, the image quality captured by the source and terminal devices is far from meeting current monitoring requirements. As mentioned earlier, directly replacing the equipment is costly and difficult. Since the terminal devices and source devices are related, the timing of the multiple source devices displayed on the terminal devices must be consistent; that is, the signals received by the terminal devices must be completely synchronized with the source devices to be recognized. For any device capable of generating PAL video, the PAL timing is generated by its own clock or timer. Due to the error of the clock or timer, there will always be a certain difference in the specific timing of the PAL video signals acquired and transmitted by multiple source devices. In fact, the problem that can be improved from a software perspective is that, with the improvement of other devices in the system, although the video signals generated by each device meet the transmission standard, there will be differences in timing.

[0005] Therefore, existing technologies should be improved to solve the signal synchronization problem faced in the transformation of display and control systems in this field. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a signal timing synchronization method and device that enables the synchronization of video signal timing between source devices and terminal devices.

[0007] To address the above technical problems, the first aspect of the present invention employs a signal timing synchronization method for transmitting signals between a source and a terminal. The timing synchronization method includes the following steps: configuring a decoder to decode the source signal and decode a source timing signal from the source signal; configuring an FPGA chip to process the source timing signal, counting the generated odd and even field signals to obtain a restored timing signal and outputting it; configuring an encoder to encode the restored timing signal so that the restored timing signal is synchronized with the source signal, and finally outputting it.

[0008] As a preferred embodiment of this scheme, the step of decoding the source timing signal from the source signal specifically involves the decoder decoding the source signal to obtain the source parallel video signal, as well as the source timing signal including the clock signal, the first field synchronization signal, the first line synchronization signal, and the first odd field signal.

[0009] As a further preferred embodiment of this solution, before the step of the FPGA chip processing the source timing signal, the solution further includes: a step of converting the source parallel video signal and the source timing signal from interlaced to progressive to obtain a first image signal; and a step of performing grayscale stretching on the first image signal to obtain a second image signal.

[0010] As a further preferred embodiment of this scheme, the step of performing grayscale stretching on the first image signal to obtain the second image signal specifically includes: obtaining the grayscale histogram of each frame of the source parallel video signal, and obtaining the cumulative sum of the grayscale histogram; determining the maximum grayscale stretching coefficient and the minimum grayscale stretching coefficient based on the cumulative sum of the grayscale histogram; and mapping the maximum grayscale stretching coefficient and the minimum grayscale stretching coefficient onto a preset grayscale to obtain the second image signal.

[0011] As a preferred embodiment of this scheme, the step of counting the generated odd and even field signals specifically includes: acquiring the first field synchronization signal, the first line synchronization signal, and the first odd and even field signal, and discarding error information; starting from the rising or falling edge of the first odd and even field signal, performing kvcnt counting, and when the key value encoding count is less than a preset value, counting the image point khcnt until the range of pixel point khcnt is taken to obtain the second line synchronization signal; and taking the range of object point khcnt and kvcnt to obtain the second field synchronization signal, the second odd and even field signal, and the odd and even field flip flag signal, which constitute the restored timing signal; after performing line-by-line to interlaced processing on the restored timing signal and the second image signal, encoding is performed to generate the output signal.

[0012] Another aspect of the present invention is based on the aforementioned signal timing synchronization method, providing a signal timing synchronization device that connects a source device and a terminal device. The timing synchronization device includes: a decoder that decodes a source signal sent by the source device; a processor that processes the signal decoded by the decoder to obtain a restored timing signal and output it; and an encoder that encodes the restored timing signal to generate an output signal.

[0013] As another preferred embodiment of this solution, the FPGA chip includes: an interlaced-to-progressive conversion module, which performs interlaced-to-progressive conversion on the source signal; a grayscale stretching module, which acquires the grayscale histogram of each frame of the source parallel video signal, acquires the cumulative sum of the grayscale histogram, determines the maximum and minimum grayscale stretching coefficients based on the cumulative sum, and maps the stretching coefficients onto a preset grayscale to obtain the image signal; a source timing production module, which acquires the signal decoded by the decoder, performs technical processing starting from the rising or falling edge of the odd / even field signal, and obtains the restored timing signal through range value extraction; and a progressive-to-interlaced conversion module, which performs progressive-to-interlaced processing on the restored timing signal and the image signal, and encodes and generates an output signal.

[0014] As another preferred embodiment of this solution, it further includes a first storage unit and a second storage unit. The first storage unit caches the data of the interlaced-to-progressive conversion module, and the second storage unit includes two storage modules that alternately call and store the data of the interlaced-to-progressive conversion module.

[0015] As a further preferred embodiment of this solution, the processor is an FPGA chip, the decoder is an AD decoder, and the encoder is a DA encoder.

[0016] Due to the adoption of the above technical solutions, the present invention has the following beneficial technical effects compared with the prior art:

[0017] 1. Although the decoder generates corresponding field synchronization and line synchronization signals during the decoding process, these signals, after being adjusted by the decoder itself, cannot achieve synchronization with the timing of the source signal. For special equipment display and control systems, video signal transmission requires conversion from analog to digital signals, and then from digital signals to analog signals after encoding. The key to solving the timing problem during decoding and encoding is restoring the timing of the source video signal. This solution separates the image signal from the timing signal during decoding, and then restores the timing of the source video signal by taking the range of values ​​obtained after counting the odd and even field signals. Finally, during the progressive to interlaced conversion process, the restored timing signal and the processed image signal are subjected to a ping-pong operation, and the image signal and timing signal are output together to the encoder to generate the terminal video signal. Thus, when this method is applied to the transmission of PAL video signals between the source and terminal devices in the display and control system, no hardware replacement is required. The display and control system is transformed from the software level, ensuring the coherence between the source and terminal devices, solving the problem of inconsistent timing of video signal transmission, and significantly improving the recognition of the source device's video signal by the terminal device.

[0018] 2. Based on the above method, in the process of image signal processing, the gray-level histogram and gray-level cumulative sum are obtained frame by frame. The maximum gray-level stretching coefficient and the minimum gray-level stretching coefficient are mapped to the preset gray-level range to realize the gray-level stretching of the source image signal, improve the color contrast of the video signal, and thus enhance the image quality of the source video image in the process of restoring the timing. Attached Figure Description

[0019] Figure 1 This is a framework diagram illustrating the framework structure of the signal timing synchronization device according to a preferred embodiment of the present invention;

[0020] Figure 2 The schematic diagram illustrates the logical framework structure of signal processing in this preferred embodiment;

[0021] Figure 3 The flowchart illustrates the process of the signal timing identification method according to a preferred embodiment of the present invention. Detailed Implementation

[0022] To achieve iterative innovation in aviation display and control equipment, especially addressing the challenges encountered in upgrading equipment in older aircraft models:

[0023] 1) The image quality of older equipment urgently needs to be improved, but the cost of directly replacing the equipment is high, and many matching and compatibility issues need to be resolved;

[0024] 2) From a software perspective, improvements need to address the issue of timing synchronization difficulties between source and terminal devices. The root cause is that the timing of video signals transmitted by source devices is generated by the device's own clock or timer. Due to errors in the device's clock or timer, timing errors are always likely to exist between the video signals of multiple source devices.

[0025] The improvement of this invention is to avoid the timing asynchrony caused by clocks or timers in the signal timing part. It separates the image signals and timing signals involved in the display and control system, synchronizes the timing signals and then merges them with the processed image signals, thereby solving the timing asynchrony problem in the video signal transmission process.

[0026] Embodiments of a signal timing synchronization method and synchronization device according to the present invention will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that various modifications can be made to the described embodiments without departing from the spirit and scope of the invention. Therefore, the drawings and description are illustrative in nature and not intended to limit the scope of the claims. Furthermore, in this specification, the drawings are not drawn to scale, and the same reference numerals denote the same parts.

[0027] It should be noted that the terms "first" and "second" used in the embodiments of the present invention are used to distinguish between two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the invention. Subsequent embodiments will not explain this in detail.

[0028] Figure 1 This is a schematic diagram illustrating the framework structure of the signal timing synchronization device according to a preferred embodiment of the present invention. See also... Figure 1 Based on the aforementioned improvement approach, in this preferred embodiment, a decoder, a processor, and two memories (memory 1 and memory 2) are configured between the source device and the terminal device. The PAL video signal output by the source device is decoded by the decoder to output an RGB image signal and timing signals including field synchronization (vsy) and line synchronization (hsy). The processor processes the signals decoded by the decoder and finally merges the synchronized timing signals and image signals, outputting them to the encoder for encoding to obtain the final PAL video signal.

[0029] First, let's discuss the decoder. In this preferred embodiment, the decoder uses the GM7403 from Chengdu Zhenxin Technology Co., Ltd. as an AD decoder. The GM7403 decoder is configured via the processor through the I2C bus, decoding the source signal sent by the source device from an analog signal to a digital signal, thus realizing the decoding of the PAL source signal. The decoded source signal includes a 24-bit source parallel video signal (RGB1) and timing signals such as clock clk, field synchronization signal vsy, line synchronization signal hsy, and odd / even field signals oe.

[0030] The processor uses an EP3C120F780C device and is configured with an FPGA chip. The source signal decoded by the AD decoder is an interlaced signal; therefore, the FPGA chip is configured to convert the interlaced signal to a progressive signal for further processing, and then convert the progressive signal back to an interlaced signal recognizable by the encoder. Based on the improved approach of this invention, the FPGA chip needs to process the source parallel video signal (RGB1) and timing signal obtained from the decoder separately, see [link to relevant documentation]. Figure 2 , Figure 2 The schematic diagram illustrates the logical framework structure of the signal processing in this preferred embodiment. The logic within the FPGA chip includes an interlaced-to-progressive conversion section, a grayscale stretching section, a source timing generation section, and a progressive-to-interlaced conversion section.

[0031] In this preferred embodiment, the environment configured within the FPGA chip is Quartus. The SOPC core within Quartus is used to perform the interlaced to progressive conversion, that is, to convert the source parallel video signal and the timing signal to obtain the first image signal (RGB2). See also... Figure 1 During the interlaced-to-progressive conversion process, a storage unit for data caching is configured for the processor. In this preferred embodiment, memory 1 is an MT48LC8M32B2 memory from Micron Technology, which is adapted to the interlaced-to-progressive conversion part of the FPGA chip in the Quartus environment to cache the data during the conversion process.

[0032] After decoding, the decoder outputs two parts: a source parallel video signal (RGB1) and a timing signal. The FPGA chip needs to process these two signals separately. Let's first discuss the source parallel video signal. The PAL signal from the source device, especially in older models, has low image clarity and insufficient contrast. In this preferred embodiment, the grayscale stretching part in the FPGA chip enhances image clarity by performing graded stretching of grayscale values. The grayscale stretching module uses a linear stretching method. First, it collects and statistically analyzes the grayscale histogram of each frame of the first image signal, and calculates the cumulative sum of the histograms. Then, based on the cumulative sum, it calculates the maximum stretching coefficient A and the minimum stretching coefficient B of the current source video signal. These maximum and minimum stretching coefficients A and B form an interval, which is mapped to a preset grayscale interval to obtain the stretched RGB signal. Corresponding to the aforementioned first image signal (RGB2), the stretched RGB signal is defined as the second image signal (RGB3). The stretched image has more obvious color contrast, thus enhancing image clarity.

[0033] Next, let's discuss the signal timing section. The AD decoder also generates clock signals, synchronization signals, and horizontal synchronization signals when decoding the source signals. However, the vertical and horizontal synchronization signals in this part are difficult to synchronize with the timing of the source signals after being adjusted by the decoder itself. Therefore, the source timing generation section of the FPGA chip processes the signals obtained from the AD decoder and restores the signal timing. Specifically, the source timing generation section acquires the timing signals (first odd / even field signal oe, first field synchronization signal vsy, and first horizontal synchronization signal hsy) generated by the GM 7403, and then discards some signals containing error information. Starting from the rising edge of the first odd / even field signal oe, the line kvcnt is counted, and if kvcnt is less than 624, the pixel khcnt is counted. The new line synchronization signal is obtained by taking the value of the pixel khcnt range, and the new field synchronization signal and the odd / even field flip flag signal (the second line synchronization signal hsy_2, the second field synchronization signal vsy2, the second odd / even field signal oe_2, and the odd / even field flip flag signal set_2) are obtained by taking the value of the pixel khcnt and kvcnt range.

[0034] The processed second image signal (RGB3) and timing signals (second line synchronization signal hsy_2, second field synchronization signal vsy2, second odd / even field signal oe_2, and odd / even field inversion flag signal set_2) are sent together to the progressive-to-interlaced section of the FPGA chip. The progressive-to-interlaced operation is performed using a ping-pong operation. (See previous text) Figure 1The memory 2 in the FPGA chip is adapted to the line-to-interlaced conversion section. In this embodiment, memory 2 uses two sets of ISSI IS61WV102416BLL memory cells, each corresponding to one path of the ping-pong operation. The ping-pong operation can be viewed as follows: input data is written to both memory cells sequentially, and when one data cell is full, it is transferred to the other memory cell, and the currently full memory cell is output. This process is repeated. In the line-to-interlaced ping-pong operation of this embodiment, the FPGA chip controls the sequential writing of line-by-line data into the two memory cells of memory 2, and alternates between calling and storing as described above, outputting the line-by-line data interlaced. See [link / reference] Figure 2 After merging, the second image signal (RGB3) and timing signals (second line synchronization signal hsy_2, second field synchronization signal vsy2, second odd field signal oe_2 and odd field flip flag signal set_2) are merged to form the output signal (RGB4).

[0035] The encoder encodes the output signal (RGB4) to ultimately restore the signal timing and generate a PAL video signal that can be recognized and displayed by the terminal device. The encoder uses the GM7341 from Chengdu Zhenxin Technology Co., Ltd. as a DA decoder to convert the digital signal output from the FPGA chip into an analog signal. It then uses the RGB parallel signals and timing signals output from the FPGA to generate the final PAL video signal. This PAL video signal is synchronized with the source signal and can be recognized by the terminal device in the airborne system.

[0036] Accordingly, another aspect of the present invention is to provide a signal timing identification method based on the aforementioned signal timing identification device. See also... Figure 3 , Figure 3 The flowchart illustrates the process of a signal timing identification method according to a preferred embodiment of the present invention. The signal timing identification method includes the following steps: configuring a decoder to decode the source signal and decode a source timing signal from the source signal; configuring an FPGA chip to process the source timing signal, counting the generated odd and even field signals to obtain a restored timing signal and outputting it; configuring an encoder to encode the restored timing signal so that the restored timing signal is synchronized with the source signal, and finally outputting it.

[0037] The timing discrepancies in existing devices are due to errors caused by clock or timer timing. In the method described in this invention, corresponding to the device, the odd / even field signals are counted using a counter. The source timing generation section acquires the timing signals (first odd / even field signal oe, first field synchronization signal vsy, and first line synchronization signal hsy) generated by the GM 7403, and then discards signals containing error information. Starting from the rising edge of the first odd / even field signal oe, the line kvcnt is counted. If kvcnt is less than 624, the pixel khcnt is counted. A new line synchronization signal is obtained by taking values ​​within the range of pixel khcnt. A new field synchronization signal and an odd / even field reversal flag signal (second line synchronization signal hsy_2, second field synchronization signal vsy2, second odd / even field signal oe_2, and odd / even field reversal flag signal set_2) are obtained by taking values ​​within the range of pixel khcnt.

[0038] Due to the adoption of the above technical solutions, the present invention has the following beneficial technical effects compared with the prior art:

[0039] 1. Although the decoder generates corresponding field synchronization and line synchronization signals during the decoding process, these signals, after being adjusted by the decoder itself, cannot achieve synchronization with the timing of the source signal. For special equipment display and control systems, video signal transmission requires conversion from analog to digital signals, and then from digital signals to analog signals after encoding. The key to solving the timing problem during decoding and encoding is restoring the timing of the source video signal. This solution separates the image signal from the timing signal during decoding, and then restores the timing of the source video signal by taking the range of values ​​obtained after counting the odd and even field signals. Finally, during the progressive to interlaced conversion process, the restored timing signal and the processed image signal are subjected to a ping-pong operation, and the image signal and timing signal are output together to the encoder to generate the terminal video signal. Thus, when this method is applied to the transmission of PAL video signals between the source and terminal devices in the display and control system, no hardware replacement is required. The display and control system is transformed from the software level, ensuring the coherence between the source and terminal devices, solving the problem of inconsistent timing of video signal transmission, and significantly improving the recognition of the source device's video signal by the terminal device.

[0040] 2. Based on the above method, in the process of image signal processing, the gray-level histogram and gray-level cumulative sum are obtained frame by frame. The maximum gray-level stretching coefficient and the minimum gray-level stretching coefficient are mapped to the preset gray-level range to realize the gray-level stretching of the source image signal, improve the color contrast of the video signal, and thus enhance the image quality of the source video image in the process of restoring the timing.

[0041] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A signal timing synchronization method for transmitting signals between a source and a terminal, wherein, The timing synchronization method includes the following steps: The step of configuring a decoder to decode the source signal and decoding the source timing signal from the source signal is as follows: the decoder decodes the source signal to obtain the source parallel video signal and the source timing signal including the clock signal, the first field synchronization signal, the first line synchronization signal, and the first odd field signal. The process includes configuring an FPGA chip to process the source timing signal, counting the generated odd and even field signals to obtain and output the restored timing signal. It also includes converting the source parallel video signal and the source timing signal from interlaced to progressive to obtain a first image signal; and performing grayscale stretching on the first image signal to obtain a second image signal. The steps include configuring an encoder to encode the restored timing signal so that the restored timing signal is synchronized with the source signal and finally outputting it. The specific steps for counting the generated odd and even field signals are as follows: The first field synchronization signal, the first line synchronization signal, and the first odd / even field signal are acquired, and error information is discarded. Starting from the rising or falling edge of the first odd field signal, kvcnt is counted, and when the key value encoding count is less than a preset value, the image point khcnt is counted until the range of pixel point khcnt is taken to obtain the second row synchronization signal. Also, the range of object point khcnt and kvcnt is taken to obtain the second field synchronization signal, the second odd field signal and the odd field flip flag signal, which constitute the restoration timing signal. After the restored timing signal and the second image signal are processed by progressive-to-interlacing conversion, they are encoded to generate the output signal.

2. The signal timing synchronization method according to claim 1, wherein, The specific steps for performing grayscale stretching on the first image signal to obtain the second image signal are as follows: Obtain the grayscale histogram of each frame of the source parallel video signal, and obtain the cumulative sum of the grayscale histogram; The maximum and minimum gray-level stretching coefficients are determined based on the cumulative sum of the gray-level histograms. The maximum and minimum grayscale stretching coefficients are mapped to a preset grayscale range to obtain the second image signal.

3. A signal timing synchronization device, which connects a source device and a terminal device, wherein, The timing synchronization device includes: A decoder that decodes the source signals sent by the source device; The processor processes the signal decoded by the decoder to obtain the restored timing signal and outputs it. An encoder that encodes the restored timing signal to generate an output signal; The FPGA chip includes: Interlaced to progressive conversion module, which performs interlaced to progressive conversion on the source signal; The grayscale stretching module acquires the grayscale histogram of each frame of the source parallel video signal, and acquires the cumulative sum of the grayscale histogram. Then, it determines the maximum and minimum grayscale stretching coefficients based on the cumulative sums, and maps the stretching coefficients onto a preset grayscale to obtain the image signal. The source timing production module acquires the signal decoded by the decoder, uses the rising or falling edge of the odd / even field signal as a starting point for processing, and obtains the reconstructed timing signal by taking values ​​within a range. The progressive-to-interlaced module performs progressive-to-interlaced processing on the restored timing signal and the image signal, and encodes them to generate an output signal.

4. The signal timing synchronization device according to claim 3, wherein, It also includes a first storage unit and a second storage unit. The first storage unit caches the data of the interlaced to progressive conversion module, and the second storage unit contains two storage modules that alternately call and store the data of the interlaced to progressive conversion module.

5. The signal timing synchronization device according to claim 4, wherein, The processor is an FPGA chip, the decoder is an AD decoder, and the encoder is a DA encoder.

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