Semiconductor device structure and self-aligned multiple exposure method without sidewall
By employing a sidewall-free self-aligned multiple exposure method, staggered arrangement, and sidewall-free patterning process, the limitations of one-dimensional patterns in existing technologies are solved, the definition of complex two-dimensional patterns is realized, the capacitance per unit area and capacitor performance of semiconductor devices are improved, and the process flow is simplified.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2021-11-26
- Publication Date
- 2026-06-19
AI Technical Summary
In existing patterning processes with feature sizes below 38nm, the self-aligned multiple exposure scheme based on sidewalls limits the patterns to one-dimensional straight lines, sacrificing the flexibility of layout design, increasing design difficulty and manufacturing costs, and making it difficult to achieve multiple decomposition processes for complex patterns.
The sidewall-free self-aligned multiple exposure method connects semiconductor devices through staggered wave curves or zigzag-shaped bit lines. Combined with sidewall-free patterning and reduction processing, it replaces the sidewall deposition process, realizes the definition of complex two-dimensional patterns, and simplifies the process flow.
It expands the feasibility of layout design, increases the number of semiconductor devices per unit area, improves the performance of capacitors in 4F2 1T1C DRAM, simplifies the process flow, and improves yield.
Smart Images
Figure CN116193848B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor devices and their manufacturing technology, and in particular to a semiconductor device structure and a sidewall-free self-aligned multiple exposure method. Background Technology
[0002] Currently, in the field of advanced semiconductor manufacturing, the patterning process for feature sizes below 38nm generally adopts the self-aligned multiple exposure (SADP) solution based on sidewalls (spacers), see appendix. Figure 10 and attached Figure 11 While this approach expands the resolution of patterns compared to ArF lithography, it also limits the patterns to one-dimensional linear designs, sacrificing flexibility in layout design. For complex patterns, multiple decomposition processes are required, and additional structural / connection layers may even be needed to complete the device structure, significantly increasing design complexity and manufacturing costs. Summary of the Invention
[0003] To address the aforementioned technical problems, the present invention provides a semiconductor device structure, including a substrate;
[0004] Bit lines are disposed on the substrate;
[0005] And multiple memory cell groups, including: multiple transistor and / or capacitor cells disposed on a substrate, the transistor and / or capacitor cells being arranged row by row in a first direction parallel to the substrate; wherein,
[0006] The memory cell group is hexagonal, consisting of at least six transistors and / or capacitors located at six vertices; the bit lines extend in a second direction perpendicular to the first direction, and the transistors and / or capacitors with the same bit order along the second direction are connected by any of the bit lines; among the transistors and / or capacitors located at the six vertices of the memory cell group, at least two adjacent transistors and / or capacitors are connected by the same bit line in the second direction.
[0007] Optionally, transistors and / or capacitor cells with the same bit sequence in different rows are arranged in a staggered manner, and the bit lines are curved or polygonal lines.
[0008] Optionally, the bit lines are formed using a sidewall-less patterning process.
[0009] Optionally, the hexagon is a regular hexagon.
[0010] Optionally, the semiconductor device structure may further include multiple structural layers, with the transistors and / or capacitors in each structural layer arranged in the same way and connected to the bit lines.
[0011] Optionally, the structural layer includes a metal mask layer and a substrate, wherein the metal mask layer covers and adheres to the surface of the substrate.
[0012] This invention provides a sidewall-free self-aligned multiple exposure method for fabricating semiconductor device structures, comprising the following steps:
[0013] S10 sets photoresist or mask layers in groups of two bit lines according to the preset transistor and / or capacitor units and bit line pattern design.
[0014] S20 performs the first hard mask layer etching, and synchronously transfers the pattern to the metal mask layer and the dielectric mask layer;
[0015] S30 shrinks the dielectric mask layer so that the remaining dielectric mask layer is only retained in the space between the two bit lines in each group.
[0016] S40 performs spin coating of the organic film layer, and then etchs back to expose the dielectric mask layer on the surface of the organic film layer;
[0017] S50 performs a second hard mask layer etching to remove the dielectric mask layer and metal mask layer of the two bit line spacing in each group.
[0018] Optionally, the following steps may also be included:
[0019] S60 undergoes ashing treatment to remove the organic film layer;
[0020] S70 uses a metal mask layer as a patterning barrier layer to perform anisotropic etching on the substrate, forming a predetermined pattern on the substrate.
[0021] Optionally, in step S10, a metal mask layer and a dielectric mask layer are deposited on the surface of the substrate material to be etched before setting the photoresist or mask layer.
[0022] Optionally, in step S30, the shrinking method is to perform isotropic etching on the dielectric mask layer to cause pattern shrinkage of the dielectric mask layer, with the shrinkage size equal to the bit line width.
[0023] Optionally, in step S40, the organic film layer is formed using a carbon material to create a carbon mask layer.
[0024] Optionally, in step S10, the width of the photoresist or mask layer is equal to the sum of the width of the bit line spacing portion of the pattern design and twice the bit line width.
[0025] Optionally, the bit line forming the preset shape is a curve or a polygonal line.
[0026] Optionally, the predetermined pattern is a hexagonal pattern of storage cells, and the transistor or capacitor cells are located at the six vertices of the hexagonal pattern.
[0027] The semiconductor device structure and sidewall-less self-aligned multiple exposure method of the present invention employ a staggered arrangement of semiconductor devices, connecting each row of semiconductor devices with bit lines in the shape of wavy curves or broken lines. For the same semiconductor device spacing, the number of semiconductor devices per unit area can be increased. To realize the manufacturing of this semiconductor device structure, a novel spacer-less self-aligned multiple exposure (SADP) patterning process is also proposed. In the key pattern multiplication process step, a reduction processing (miniaturization) method is used to replace the sidewall deposition process. This eliminates the adverse effects of uneven thickness at sidewall corners, reduces the likelihood of lateral stress, and results in a more stable structure during processing, preventing pattern tilting. This avoids the linewidth unevenness and pattern collapse problems caused by the inherent characteristics of the sidewall deposition process in the prior art. Using the spacer-less self-aligned multiple exposure (SADP) patterning process proposed in this invention, the definition of complex two-dimensional patterns such as broken lines and curves, which are impossible with traditional SADP processes, can be achieved. This expands the feasibility of layout design, improves the performance of capacitors in 4F21T1C DRAM, and simplifies the existing process flow. This invention is an improvement on patterning processes. It mainly adopts a sidewall-free deposition process solution in the self-aligned multiple exposure process, which expands the patterning capabilities of self-aligned multiple exposure, while also expanding the feasibility of layout design and improving the product yield.
[0028] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.
[0029] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0030] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:
[0031] Figure 1 This is a schematic diagram of a semiconductor device structure according to an embodiment of the present invention;
[0032] Figure 2 This is a flowchart of a sidewall-free self-aligned multiple exposure method according to an embodiment of the present invention;
[0033] Figure 3 This is a flowchart of a second embodiment of the sidewall-free self-aligned multiple exposure method of the present invention;
[0034] Figure 4 A schematic diagram of a cross-section of a photoresist or mask layer in an embodiment of the sidewall-free self-aligned multiple exposure method of the present invention;
[0035] Figure 5 This is a schematic cross-sectional view of the first hard mask layer after etching in an embodiment of the sidewall-free self-aligned multiple exposure method of the present invention.
[0036] Figure 6 This is a scaled-down cross-sectional schematic diagram of the dielectric mask layer in an embodiment of the sidewall-free self-aligned multiple exposure method of the present invention;
[0037] Figure 7 This is a schematic cross-sectional view of the organic film layer after spin coating and etch-back in an embodiment of the sidewall-free self-aligned multiple exposure method of the present invention;
[0038] Figure 8 This is a schematic cross-sectional view of the second hard mask layer after etching in an embodiment of the sidewall-free self-aligned multiple exposure method of the present invention.
[0039] Figure 9 This is a schematic cross-sectional view of the substrate after anisotropic etching in an embodiment of the sidewall-free self-aligned multiple exposure method of the present invention.
[0040] Figure 10 This is a schematic diagram of the process of the self-aligned multiple exposure method based on sidewalls used in the prior art;
[0041] Figure 11 A schematic diagram illustrating the lateral stress that causes the pattern to tilt when using the existing sidewall-based self-aligned multiple exposure method to create curved patterns.
[0042] Figure 12 This is a comparison diagram of the effects of the sidewall-free self-aligned multiple exposure method of the present invention and the prior art.
[0043] In the figure: 1-transistor and / or capacitor, 2-structural layer, 3-bit line, 4-photoresist or mask layer, 5-dielectric mask layer, 6-metal mask layer, 7-substrate, 8-organic film layer, 9-sidewall. Detailed Implementation
[0044] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.
[0045] like Figure 1-2 As shown in Figures 4-8, embodiments of the present invention provide a semiconductor device structure, including a substrate;
[0046] Bit line 3 is disposed on the substrate;
[0047] And multiple memory cell groups, including: multiple transistor and / or capacitor cells 1 disposed on a substrate, the transistor and / or capacitor cells 1 being arranged row by row in a first direction parallel to the substrate; wherein,
[0048] The memory cell group is hexagonal, consisting of at least six transistor and / or capacitor cells 1 located at six vertices; the bit line extends in a second direction perpendicular to the first direction, and the transistor and / or capacitor cells 1 with the same bit sequence along the second direction are connected by any of the bit lines; among the transistor and / or capacitor cells 1 located at the six vertices of the memory cell group, at least two adjacent transistor and / or capacitor cells 1 are connected by the same bit line in the second direction.
[0049] The working principle and beneficial effects of the above technical solution are as follows: This solution adopts a staggered arrangement of semiconductor devices (transistors and / or capacitor cells), connecting each row of semiconductor devices with wavy or polygonal bit lines. For the same semiconductor device spacing, the capacity per unit area can be increased. By arranging transistors and capacitors in a honeycomb distribution, the densest stacking is achieved, increasing the transistor and capacitor capacity by approximately 21% compared to existing linear orthogonal designs. This structure can also be used in 6F2 1T1C DRAM structure design, utilizing wavy or polygonal bit lines to improve the graphic layout design, allowing storage node contacts to naturally form a honeycomb distribution, thereby saving on landing pads. The pad (pad) process improves resistance. Taking the wavy curve bit line as an example, the same bit sequence means that transistors and / or capacitors of the same order in each row are connected by the same wavy curve bit line. For example, the first-order transistor and / or capacitor in the first row, the first-order transistor and / or capacitor in the second row, the first-order transistor and / or capacitor in the third row, and so on, until the first-order transistor and / or capacitor in the last row are connected by the same wavy curve bit line. The second-order transistor and / or capacitor in the first row, the second-order transistor and / or capacitor in the second row, the second-order transistor and / or capacitor in the third row, and so on, until the second-order transistor and / or capacitor in the last row are connected by another wavy curve bit line, and so on. The peak and valley points of the wavy curve bit line correspond to the positions of the same-order transistors and / or capacitors in each row. The manufacturing method used in this structure has no sidewalls, so there is no adverse effect of uneven thickness at the corners of the sidewalls. It is not easy to generate lateral stress, the structure is more stable during processing, and it will not cause the pattern to tilt, thus improving the yield.
[0050] In one embodiment, transistors and / or capacitor cells with the same bit sequence in different rows are staggered, and the bit lines are curved or polygonal lines; the curved or polygonal bit lines are formed by a sidewall-less patterning process; the semiconductor device structure also includes multiple structural layers, and the transistors and / or capacitors in each structural layer are connected to the bit lines in the same arrangement; the structural layer includes a metal mask layer 6 and a substrate 7, and the metal mask layer covers and adheres to the surface of the substrate.
[0051] The working principle and beneficial effects of the above technical solution are as follows: In this solution, transistors and / or capacitors with the same bit sequence in different rows are arranged in a staggered manner, and the bit lines can be curved or broken lines; the curved or broken bit lines are formed by a sidewall-free patterning process; the semiconductor device structure has multiple structural layers, and the transistors and / or capacitors in each structural layer are arranged in the same way and connected to the bit lines to increase the number of semiconductor device capacities per unit area; the structural layer includes a metal mask layer and a substrate, and the metal mask layer covers and adheres to the surface of the substrate, both of which are used to form the semiconductor device structure thereon.
[0052] like Figure 2 As shown, this embodiment of the invention also provides a sidewall-free self-aligned multiple exposure method for manufacturing the above-mentioned semiconductor device structure, comprising the following steps:
[0053] S10 Figure 4 As shown, according to the preset transistor and / or capacitor cell bit line pattern design, photoresist or mask layer 4 is set in groups of two bit lines.
[0054] S20 Figure 5 As shown, the first hard mask layer etching is performed, and the pattern is synchronously transferred to the metal mask layer 6 and the dielectric mask layer 5.
[0055] S30 Figure 6 As shown, the dielectric mask layer 5 is miniaturized so that the remaining dielectric mask layer 5 is only retained in the space between the two bit lines in each group; wherein, Figure 6 The middle arrow indicates the direction of miniaturization;
[0056] S40 Figure 7 As shown, the organic film layer 8 is spin-coated, and then etched back to expose the dielectric mask layer 5 on the surface of the organic film layer 8.
[0057] S50 Figure 8 As shown, a second hard mask layer etching is performed to remove the dielectric mask layer and metal mask layer of the two bit line spacing in each group.
[0058] The working principle and beneficial effects of the above technical solution are as follows: In order to realize the manufacturing of the above semiconductor device structure, this solution proposes a novel spacer-less self-aligned multiple exposure (SADP) patterning process. In the key pattern multiplication process step, a reduction processing (miniaturization) method is used to replace the sidewall deposition process. There is no adverse effect of uneven thickness at the sidewall corners, and it is not easy to generate lateral stress. The structure is more stable during the processing and will not cause the pattern to tilt. Thus, it avoids the problems of uneven linewidth and pattern collapse caused by the inherent characteristics of the sidewall deposition process in the prior art, and can improve the yield. Using the spacer-less self-aligned multiple exposure (SADP) patterning process proposed in this invention, it is possible to define complex two-dimensional patterns such as broken lines and curves that cannot be achieved by the traditional SADP process, expand the feasibility of layout design, improve the performance of capacitors in 4F2 1T1C DRAM, and simplify the existing process flow. This invention is an improvement to the patterning process. It mainly adopts a sidewall-free deposition process solution in the self-aligned multiple exposure process, which expands the pattern processing capabilities of self-aligned multiple exposure and the feasibility of layout design. The process of this invention does not use sidewalls, but uses the trim process to define the miniature pattern, which does not produce a high aspect ratio structure and avoids the pattern defects that may occur in line / curve patterns. This expands the application range of SADP process from one-dimensional patterns to two-dimensional patterns.
[0059] In one embodiment, such as Figure 3 and 9 As shown, the method further includes the following steps:
[0060] S60 is subjected to ashing treatment to remove the organic film layer 8;
[0061] S70 uses a metal mask layer 6 as a pattern blocking layer to perform anisotropic etching on the substrate 7 to form a predetermined pattern on the substrate 7; preferably, the bit line forming the predetermined shape is a curve or a broken line; the predetermined pattern is a hexagonal memory cell group, and the transistor or capacitor cell is located at the six vertices of the hexagonal pattern.
[0062] The working principle and beneficial effects of the above technical solution are as follows: After forming the wavy curve-shaped bit lines, the organic film layer is removed by ashing treatment. Then, a metal mask layer is used as a pattern blocking layer to perform anisotropic etching on the substrate to form the required design pattern (predetermined pattern) on the substrate. This results in a staggered semiconductor device structure with wavy curve-shaped bit lines connected, which increases the number of semiconductor devices per unit area for the same semiconductor device spacing.
[0063] In one embodiment, in step S10, before setting the photoresist or mask layer 4, a metal mask layer 6 and a dielectric mask layer 5 are deposited on the surface of the substrate material to be etched.
[0064] The working principle and beneficial effects of the above technical solution are as follows: Before setting the photoresist or mask layer, this solution deposits a metal mask layer and a dielectric mask layer on the surface of the substrate material to be etched, providing a basic processing object for subsequent processes. The main function of the dielectric mask layer is to transfer the processing pattern during processing. In addition to transferring the processing pattern during processing, the metal mask layer retains a portion after processing that becomes part of the structure, i.e., the dot line. This solution stipulates that the dielectric mask layer and the metal mask layer need to provide a sufficient etching selectivity ratio to meet the process window requirements, so as to provide processing conditions for subsequent processes, effectively protect the product prototype during processing, and avoid damage to the product due to insufficient material, which would result in product defects.
[0065] In one embodiment, in step S30, the method of miniaturization is to perform isotropic etching on the dielectric mask layer 5 to cause pattern miniaturization of the dielectric mask layer, and the miniaturization size is equal to the bit line width.
[0066] The working principle and beneficial effects of the above technical solution are as follows: the metal mask layer pattern does not change during the miniaturization process; miniaturization is an isotropic etching of the dielectric mask layer. Except for the lower end face that is in close contact with the metal mask layer, the upper end face and two side faces of the dielectric mask layer are miniaturized simultaneously. The miniaturization size is equal to the bit line width, so as to provide a basis for subsequent processes to form bit lines with the required design width.
[0067] In one embodiment, in step S40, the organic film layer 8 is formed using a carbon material to create a carbon mask layer.
[0068] The working principle and beneficial effects of the above technical solution are as follows: The mechanical film layer in this solution is formed by carbon material to form a carbon mask layer. Of course, it can also be replaced with other organic materials with filling and anti-etching capabilities. As long as it is an organic material that can fill and resist etching, it can achieve the purpose. Organic materials are used so that they can be removed by subsequent ashing treatment, so that they will not leave residues on the product.
[0069] In one embodiment, in step S10, the width of the photoresist or mask layer 4 is equal to the sum of the width of the bit line spacing portion of the pattern design and twice the bit line width.
[0070] The working principle and beneficial effects of the above technical solution are as follows: This solution limits the width of the photoresist or mask layer to the sum of the width of the bit line spacing portion of the graphic design and twice the bit line width. By limiting this, the processing accuracy can be strictly controlled. The bit line spacing portion width and bit line width are selected and determined according to the needs during the design.
[0071] To address the following problems existing in current process technologies: Figure 10 and 11 As shown, ALD technology can only be applied to straight-line patterns. Complex patterns require decomposition. The characteristics of thin-film deposition result in uneven sidewall film thickness at the corners of zigzag lines. The sidewalls need to maintain a certain aspect ratio to define the pattern. Curved patterns are more prone to lateral stress, leading to pattern tilting. Currently, SADP mass production processes based on sidewall spacers are still limited to one-dimensional patterns, restricting device layout design. This invention adopts a spacer-less self-aligned multiple exposure (SADP) patterning process, which can realize the definition of complex two-dimensional patterns such as zigzag lines and curves that traditional SADP processes cannot achieve. This expands the feasibility of layout design, improves the performance of capacitors in 4F2 1T1CDRAM, and simplifies the existing process flow; for example... Figure 12 As shown, the VGAA DRAM structure utilizes a novel Spacer-less SADP patterning scheme to form curved bit lines, arranging transistors and capacitors in a honeycomb pattern to achieve the densest stacking. Compared to a linear orthogonal design, the capacitor capacity is increased by approximately 21%.
[0072] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A semiconductor device structure, characterized by, include, substrate; Bit lines are disposed on the substrate; And multiple memory cell groups, including: multiple transistor and / or capacitor cells disposed on a substrate, the transistor and / or capacitor cells being arranged row by row in a first direction parallel to the substrate; wherein, The memory cell group is hexagonal, consisting of at least six transistors and / or capacitors located at six vertices; the bit line extends in a second direction perpendicular to the first direction, and transistors and / or capacitors of the same bit order along the second direction are connected by any of the bit lines; among the transistors and / or capacitors located at the six vertices of the memory cell group, at least two adjacent transistors and / or capacitors are connected by the same bit line in the second direction.
2. The semiconductor device structure of claim 1, wherein, The transistors and / or capacitor cells with the same bit sequence in different rows are arranged in a staggered manner, and the bit lines are curved or broken lines.
3. The semiconductor device structure of claim 2, wherein, The bit lines are formed using a sidewall-less patterning process.
4. The semiconductor device structure of claim 1, wherein, The hexagon is a regular hexagon.
5. The semiconductor device structure according to claim 1, characterized in that, The semiconductor device structure also includes multiple structural layers, and the transistors and / or capacitors of each structural layer are connected to the bit lines in the same arrangement.
6. The semiconductor device structure of claim 5, wherein, The structural layer includes a metal mask layer and a substrate, with the metal mask layer covering and bonded to the surface of the substrate.
7. A self-aligned multiple exposure method without spacers, characterized in that, The method for manufacturing semiconductor device structures includes the following steps: S10 designs a preset memory cell group based on transistor and / or capacitor cells and bit line patterns, setting photoresist or mask layers in groups of two bit lines; the transistor and / or capacitor cells are arranged row by row in the first direction; the memory cell group is hexagonal, consisting of at least six transistor and / or capacitor cells located at six vertices; the bit lines extend in a second direction perpendicular to the first direction, and transistor and / or capacitor cells with the same bit sequence along the second direction are connected through any of the bit lines; among the transistor and / or capacitor cells located at the six vertices of the memory cell group, at least two adjacent transistor and / or capacitor cells are connected through the same bit line in the second direction; S20 performs the first hard mask layer etching, and synchronously transfers the pattern to the metal mask layer and the dielectric mask layer; S30 shrinks the dielectric mask layer so that the remaining dielectric mask layer is only retained in the space between the two bit lines in each group. S40 performs spin coating of the organic film layer, and then etchs back to expose the dielectric mask layer on the surface of the organic film layer; S50 performs a second hard mask layer etching to remove the dielectric mask layer and metal mask layer of the two bit line spacing in each group.
8. The method of claim 7, wherein the photoresist is a negative photoresist. It also includes the following steps: S60 undergoes ashing treatment to remove the organic film layer; S70 uses a metal mask layer as a patterning barrier layer to perform anisotropic etching on the substrate, forming a predetermined pattern on the substrate.
9. The method of claim 7, wherein the photoresist is a negative photoresist. In step S10, before setting the photoresist or mask layer, a metal mask layer and a dielectric mask layer are deposited on the surface of the substrate material to be etched.
10. The sidewall-free self-aligned multiple exposure method according to claim 7, characterized in that, In step S30, the shrinking method is as follows: isotropic etching is performed on the dielectric mask layer to cause the dielectric mask layer to be patterned and shrunk, and the shrinkage size is equal to the bit line width.
11. The method of claim 7, wherein, In step S40, the organic film layer is formed using carbon materials to create a carbon mask layer.
12. The method of claim 7, wherein, In step S10, the width of the photoresist or mask layer is equal to the sum of the width of the bit line spacing portion of the pattern design and twice the bit line width.
13. The sidewall-free self-aligned multiple exposure method according to claim 7, characterized in that, The bit lines that form the preset shape are either curves or polygonal lines.