Method of manufacturing a semiconductor memory device

Abstract

The present application relates to a method of manufacturing a semiconductor memory device. A method of manufacturing a semiconductor memory device, the method comprising: forming a stacked structure including alternately stacked interlayer insulating layers and sacrificial layers; forming an upper insulating layer covering the stacked structure; forming a preliminary isolation structure in the upper insulating layer; forming a slit through the upper insulating layer and the stacked structure; replacing the sacrificial layers with a conductive pattern through the slit; and opening a preliminary trench structure defined in the upper insulating layer by removing the preliminary isolation structure.

Description

Technical Field

[0001] This disclosure generally relates to methods for manufacturing semiconductor memory devices, and more specifically, to methods for manufacturing three-dimensional semiconductor memory devices. Background Technology

[0002] Semiconductor memory devices may include memory cell arrays comprising multiple memory cells. The memory cell arrays may include memory cells arranged in various structural configurations. To improve the integration density of semiconductor memory devices, memory cells may be arranged three-dimensionally above a substrate. When fabricating three-dimensional semiconductor memory devices, a stacked structure in which multiple material layers are stacked can be used. Summary of the Invention

[0003] According to embodiments of the present disclosure, a method for manufacturing a semiconductor memory device is provided, the method comprising: forming a stacked structure including alternating layers of interlayer insulating layers and sacrificial layers; forming an upper insulating layer covering the stacked structure; forming a preliminary isolation structure in the upper insulating layer; forming a slit penetrating the upper insulating layer and the stacked structure; replacing the sacrificial layer with a conductive pattern through the slit; and opening a preliminary trench structure defined in the upper insulating layer by removing the preliminary isolation structure. Attached Figure Description

[0004] Various examples of implementation methods will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as being limited to the implementation methods set forth herein.

[0005] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as "between" two elements, it can be the only element between those two elements, or there may be one or more intermediate elements. It will be understood that when an element, structure, pattern, or layer is referred to as "on," "connected to," or "attached to" another element, structure, pattern, or layer, it can be directly "on," connected to, or attached to the other element, structure, pattern, or layer, or there may be intermediate elements, patterns, or layers. Conversely, when an element, structure, pattern, or layer is referred to as "directly on," "directly connected to," or "directly attached to" another element, structure, pattern, or layer, there are no intermediate elements or layers. Similar reference numerals always refer to similar elements.

[0006] Figure 1A and Figure 1B This is a block diagram schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0007] Figure 2 This is a schematic circuit diagram of a semiconductor memory device according to an embodiment of the present disclosure.

[0008] Figure 3A and Figure 3B This is a plan view illustrating the layout of a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 4 This is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H and Figure 5I This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 6 This is a block diagram of the configuration of a memory system according to an embodiment of the present disclosure.

[0012] Figure 7 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0013] The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0014] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the “first” element discussed below may also be referred to as the “second” element.

[0015] Various implementations provide methods for manufacturing semiconductor memory devices that can improve electrical characteristics.

[0016] Figure 1A and Figure 1B This is a block diagram schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Reference Figure 1A and Figure 1BEach semiconductor memory device according to embodiments of the present disclosure may include a peripheral circuit structure PC and a cell array CAR disposed on a substrate SUB.

[0018] The substrate SUB can be a single-crystal semiconductor layer. For example, the substrate SUB can be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed by a selective epitaxial growth process.

[0019] A cell array (CAR) can include multiple memory blocks. Each memory block can include multiple cell strings. Each cell string is electrically connected to bit lines, source lines, word lines, and select lines. Each cell string can include memory cells and select transistors connected in series. Each select line serves as the gate electrode of its corresponding select transistor, and each word line serves as the gate electrode of its corresponding memory cell.

[0020] The peripheral circuit structure PC may include NMOS and PMOS transistors, resistors, and capacitors electrically connected to the cell array CAR. The NMOS and PMOS transistors, resistors, and capacitors can be used as components to form row decoders, column decoders, page buffers, and control circuits.

[0021] like Figure 1A As shown, the peripheral circuit structure PC can be set on a portion of the substrate SUB that does not overlap with the cell array CAR.

[0022] Alternative locations, such as Figure 1B As shown, the peripheral circuit structure PC can be disposed between the cell array CAR and the substrate SUB. The peripheral circuit structure PC overlaps with the cell array CAR, thus reducing the area of ​​the substrate SUB occupied by the cell array CAR and the peripheral circuit structure PC.

[0023] Figure 2 This is a schematic circuit diagram of a semiconductor memory device according to an embodiment of the present disclosure.

[0024] Reference Figure 2 A semiconductor memory device may include multiple cell strings CS1 and CS2 connected to a common source line SL. Cell strings CS1 and CS2 may be arranged in multiple rows and columns. Each row of cell strings CS1 and CS2 may be connected to multiple bit lines BL.

[0025] Each of the cell strings CS1 and CS2 may include multiple memory cells MC connected in series, a source-select transistor SST, and drain-select transistors DST1 and DST2. The source-select transistor SST controls the electrical connection between its corresponding cell string CS1 or CS2 and the common source line SL. The drain-select transistors DST1 and DST2 control the electrical connection between their corresponding cell string CS1 or CS2 and their corresponding bit line BL. Each of the cell strings CS1 and CS2 may include one drain-select transistor or two or more drain-select transistors connected in series. For example, Figure 2 An example is given of each of the cell strings CS1 and CS2, including a first drain selection transistor DST1 and a second drain selection transistor DST2 connected in series between the bit line BL and the plurality of memory cells MC.

[0026] Unit strings CS1 and CS2 may include multiple first unit strings CS1 and multiple second unit strings CS2. Each bit line BL may be connected to a corresponding pair of first unit strings CS1 and second unit strings CS2 among the multiple first unit strings CS1 and multiple second unit strings CS2, so as to jointly control the pair of first unit strings CS1 and second unit strings CS2.

[0027] Multiple first unit strings CS1 and multiple second unit strings CS2 can be connected to conductive patterns DSL11, DSL12, DSL21, DSL22, WL, and SSL. Conductive patterns DSL11, DSL12, DSL21, DSL22, WL, and SSL may include first drain select lines DSL11 and DSL12, second drain select lines DSL21 and DSL22, word line WL, and source select line SSL.

[0028] The first drain select lines DSL11 and DSL12 can be individually connected to the gate electrodes of the first drain select transistor DST1 and the second drain select transistor DST2 that constitute the first unit string CS1. The second drain select lines DSL21 and DSL22 can be individually connected to the gate electrodes of the first drain select transistor DST1 and the second drain select transistor DST2 that constitute the second unit string CS2.

[0029] The source select line SSL can be connected to the gate electrode of the source select transistor SST, and the word line WL can be connected to the gate electrode of the memory cell MC. Each of the source select line SSL and the word line WL can be connected together to multiple first cell strings CS1 and multiple second cell strings CS2 to control the multiple first cell strings CS1 and multiple second cell strings CS2.

[0030] According to the above structure, the first drain selection lines DSL11 and DSL12 can be selected to perform selective operation only on the first unit string CS1, and the second drain selection lines DSL21 and DSL22 can be selected to perform selective operation only on the second unit string CS2.

[0031] As described above, two or more cell strings can be connected to a bit line BL and a word line WL, and the drain select line can be individually connected to two or more cell strings to control them individually. For example, as Figure 2 As shown, the first unit string CS1 and the second unit string CS2 can be connected to a bit line BL and a word line WL. The first drain selection lines DSL11 and DSL12 connected to the first unit string CS1 can be separated from each other to control the first unit string CS1 and the second unit string CS2 independently.

[0032] Figure 3A and Figure 3B This is a plan view illustrating the layout of a semiconductor memory device according to an embodiment of the present disclosure. Figure 3A and Figure 3B Each of the structures shown can be included Figure 1A or Figure 1B The cell array CAR shown.

[0033] Reference Figure 3A and Figure 3B The semiconductor memory device according to embodiments of the present disclosure may include a select stack structure SET and a cell stack structure CET. Figure 3A This example demonstrates the layout for selecting a SET stacked structure, and Figure 3B The layout of a cell stacked structure (CET) is illustrated. In the following text, the first horizontal direction X, the second horizontal direction Y, and the vertical direction Z can be defined as directions facing axes that intersect each other. In an embodiment, the first horizontal direction X, the second horizontal direction Y, and the vertical direction Z can be defined as the X-axis direction, Y-axis direction, and Z-axis direction of the XYX coordinate system.

[0034] Selecting a stacked structure SET allows it to overlap with a unit stacked structure CET.

[0035] The selected stacked structure SET can be isolated from each other by slits S and selection line isolation structures SLS. One or more selection line isolation structures SLS can be arranged between slits S adjacent to each other along the first horizontal direction X. For example, one selection line isolation structure SLS can be arranged between slits S adjacent to each other along the first horizontal direction X. In another example, two or more selection line isolation structures SLS can be arranged between slits S adjacent to each other along the first horizontal direction X.

[0036] Slits S may extend between unit stack structures CET. Each unit stack structure CET may extend along a first horizontal direction X between adjacent slits S. Each unit stack structure CET may overlap with two or more selected stack structures SET and selected line isolation structures SLS that isolate the selected stack structures SET from each other.

[0037] Each of the selected stack-up structure SET and the unit stack-up structure CET can extend in a first horizontal direction X and a second horizontal direction Y. Each of the selected stack-up structure SET and the unit stack-up structure CET can include interlayer insulating layers and conductive patterns stacked in the vertical direction Z. (See below for further details.) Figure 4 Describes the stack-up structure of interlayer insulating layers and conductive patterns. The conductive pattern of the selected stack-up structure SET can form a reference. Figure 2 The first drain selection lines DSL11 and DSL12 and the second drain selection lines DSL21 and DSL22 are described. The conductive pattern of the unit stack structure CET can form a reference. Figure 2 The word line described is WL.

[0038] Each of the slits S and the selection line isolation structures SLS can extend in the second horizontal direction Y. Channel structures CH can be disposed on both sides of each selection line isolation structure SLS. Each channel structure CH can extend in the vertical direction Z and penetrate the selection stack structure SET and the unit stack structure CET. The channel structures CH disposed between adjacent slits S can be divided into multiple channel groups (e.g., GR1 to GR4) by the selection line isolation structures SLS. Channel groups GR1 to GR4 shared by a unit stack structure CET can be individually controlled by selection stack structures SET isolated from each other by at least one selection line isolation structure SLS. Each channel group GR1, GR2, GR3, or GR4 can include one or more columns of channel structures CH.

[0039] The adjacent channels with slits S inserted therebetween can be divided into a first channel structure CH1 and a second channel structure CH2. The adjacent channels with selected line isolation structures SLS inserted therebetween can be divided into a third channel structure CH3 and a fourth channel structure CH4. The distance between the first channel structure CH1 and the second channel structure CH2 can be defined as a first distance W1, and the distance between the third channel structure CH3 and the fourth channel structure CH4 can be defined as a second distance W2. In an embodiment, the distance between the first channel structure CH1 and the second channel structure CH2 can be formed to be a first distance W1 that is wider than the second distance W2.

[0040] According to the above structure, the number of channel structures CH shared by each selected stack structure SET is less than the number of channel structures CH shared by each unit stack structure CET.

[0041] The width of each selection line isolation structure SLS can be formed to be different from the width of each slit S. More specifically, each selection line isolation structure SLS can be formed to be narrower than each slit S in the first horizontal direction X.

[0042] The channel structure CH can be configured in a Z-shape. However, this disclosure is not limited thereto. In an embodiment, the channel structure CH can be arranged parallel to each other in the first horizontal direction X and the second horizontal direction Y.

[0043] The channel structure CH can be connected to the bit line BL. The bit line BL can be positioned spaced apart from the selected stack structure SET in the vertical direction Z, and can be positioned on the selected stack structure SET. The bit line BL can extend in a first horizontal direction X. The bit lines BL can be arranged to be spaced apart from each other in a second horizontal direction Y. Each bit line BL can be electrically connected to the channel structure CH via a bit line contact (not shown). The bit line BL can include a conductive material. In the example, the bit line BL can include tungsten, aluminum, or copper.

[0044] Figure 4 This is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0045] Figure 4 Examples Figure 3A The selected stacked structure SET and Figure 3B The stacked structure of the unit layer CET is shown. Figure 4 Examples are shown along Figure 3A and Figure 3B The cross-section of the semiconductor memory device is shown by line I-I'.

[0046] Reference Figure 4 A semiconductor memory device according to embodiments of the present disclosure may include a gate stack structure GST. The gate stack structure GST may include interlayer insulating layers (ILDs) and conductive patterns (CPs) alternately stacked in the vertical direction Z. Each of the interlayer insulating layers (ILDs) and conductive patterns (CPs) may be configured to... Figure 3A and Figure 3B It extends along the second horizontal direction Y as shown.

[0047] The gate stack structure (GST) can be divided into a cell stack structure (CET) and a select stack structure (SET). In other words, the interlayer insulating layer (ILD) and the conductive pattern (CP) can be divided into patterns constituting the cell stack structure (CET) and patterns constituting the select stack structure (SET). The select stack structure (SET) can be stacked on top of the cell stack structure (CET) and can be... Figure 3A They are spaced apart from each other in the first horizontal direction X.

[0048] The select line isolation structure SLS can be disposed within the gate stack structure GST. The select line isolation structure SLS isolates the select stack structures SET from each other. The boundary of the gate stack structure GST can be defined by a slit S. The slit S can extend in the vertical direction Z to define the sidewalls of the cell stack structure CET. The slit S can extend up to the height where the select stack structure SET is disposed. Therefore, the slit S can define the sidewalls of the side stack structures adjacent to the slit S in the select stack structure SET.

[0049] The slit S can be filled with a vertical structure VS. The vertical structure VS can consist only of insulating material or include both insulating material and conductive material penetrating the insulating material. The optional line isolation structure SLS can be configured with insulating material.

[0050] The selective line isolation structure (SLS) can be a pattern disposed in at least the uppermost layer of the conductive pattern (CP) of the gate stack structure (GST). However, this disclosure is not limited thereto.

[0051] For example, the select line isolation structure (SLS) can penetrate the topmost pattern and one or more patterns continuously disposed below it in the conductive pattern CP of the gate stack structure (GST). Multiple layers of patterns in the conductive pattern CP are not penetrated by the select line isolation structure (SLS), but can extend to overlap with it. The conductive pattern CP of the cell stack structure (CET) not penetrated by the select line isolation structure (SLS) can be used as the source select line and word line (WL). The conductive pattern CP of the select stack structure (SET) isolated by the select line isolation structure (SLS) can be used as the drain select line (DSL).

[0052] Each of the conductive pattern CP and the interlayer insulating layer ILD may surround the channel structure CH. Each channel structure CH may include a semiconductor material such as silicon. The channel structure CH may include a core insulating layer CO, a channel layer CL, and a memory layer ML. The channel structure CH may include a liner pattern surrounding the sidewalls of the core insulating layer CO and a cover pattern disposed on the core insulating layer CO. The cover pattern of the channel structure CH may include conductivity-type impurities. In an embodiment, the conductivity-type impurities may include n-type impurities.

[0053] The memory layer ML surrounding the channel layer may include a tunneling insulating layer, a data storage layer, and a barrier insulating layer sequentially stacked on the surface of the channel layer. The data storage layer may include a material layer capable of storing data altered using Fowler-Nordheim tunneling. For this purpose, the data storage layer can be formed of various materials. For example, the data storage layer may be formed of a nitride layer in which charge can be trapped. However, this disclosure is not limited to this, and the data storage layer may include silicon, phase change materials, nanodots, etc. The barrier insulating layer may include an oxide layer capable of blocking the movement of charge. The tunneling insulating layer may include a silicon oxide layer through which charge can tunnel.

[0054] A memory layer ML can be disposed between each channel structure CH and the gate stack structure GST. The memory layer ML can extend along the sidewall of its corresponding channel structure CH. However, this disclosure is not limited thereto.

[0055] Although not shown in the figures, in an embodiment, the memory layer ML may be disposed on the sidewall of each conductive pattern CP facing the channel structure CH, and extend along the interface between each conductive pattern CP and the adjacent interlayer insulating layer ILD. The memory layer ML may have a C-shaped cross-sectional structure opening toward the select line isolation structure SLS or the slit S.

[0056] Each conductive pattern CP may include at least one of a silicon layer, a metal silicide layer, a metal layer, and a metal nitride layer. Each conductive pattern CP may include a metal such as tungsten (W) to achieve low-resistance wiring. A barrier layer (not shown) may be further formed to prevent direct contact between each conductive pattern CP and its adjacent interlayer insulating layer ILD, and between each conductive pattern CP and the memory layer ML. The barrier layer may be formed of a metal oxide layer. For example, the barrier layer may include a titanium nitride layer, a tungsten nitride layer, or a tantalum nitride layer.

[0057] Each interlayer insulating layer (ILD) can be formed from various insulating materials. For example, each ILD may include a silicon oxide layer.

[0058] The channel structure CH can protrude further in the vertical direction Z than the gate stack structure GST. Both the channel structure CH and the gate stack structure GST can be covered by the upper insulating layer UI. The slit S and its vertical structure VS can extend in the vertical direction Z to penetrate the upper insulating layer UI. The selected line isolation structure SLS can extend in the vertical direction Z to penetrate the upper insulating layer UI.

[0059] The contact plug CT can individually contact the channel structure CH, while penetrating the upper insulating layer UI overlapping the channel structure CH. The contact plug CT can be formed of various conductive materials. In an embodiment, each contact plug CT may include titanium nitride (TiN) and tungsten (W).

[0060] Bit line BL electrically connects the contact plug CT to the channel structure CH. Bit line BL may include a conductive material. In the example, bit line BL may include tungsten, aluminum, or copper.

[0061] Figures 5A to 5I This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. Figures 5A to 5I It is along Figure 3A and Figure 3B Each of the lines shown in the diagram is a process cross-section diagram taken from line I-I'.

[0062] Reference Figure 5A A stacked structure ST is formed through which the channel structure CH is penetrated. The stacked structure ST can be formed on a doped semiconductor layer (not shown). The manufacturing method may include a process of forming the stacked structure ST by alternately stacking an interlayer insulating layer 101 and a sacrificial layer 103, a process of forming a mask layer 111 on the interlayer insulating layer 101' present in the uppermost layer of the stacked structure ST, and a process of forming a channel structure CH through the stacked structure ST and the mask layer 111.

[0063] The stacked structure ST may include an interlayer insulating layer 101 and a sacrificial layer 103 alternately stacked in the vertical direction Z. The interlayer insulating layer 101 may be formed of a different material than the sacrificial layer 103, and the interlayer insulating layer 101 and the sacrificial layer 103 may have different etch rates. In an embodiment, the interlayer insulating layer 101 may be formed as a silicon oxide layer, and the sacrificial layer 103 may be formed as a silicon nitride layer.

[0064] The process of forming the channel structure CH may include forming vias H that penetrate the mask layer 111 and the stacked structure ST, and filling the vias H with the channel structure CH. The manufacturing method may also include forming a memory layer ML on the surface of each via H prior to forming the channel structure CH. The channel structure CH may be formed on the memory layer ML.

[0065] Reference Figure 5A and Figure 5B The mask layer 111 can be removed, exposing the interlayer insulating layer 101' in the uppermost layer. In this process, the memory layer ML of the channel structure CH can be partially removed. However, this disclosure is not limited thereto.

[0066] Reference Figure 5CAn upper insulating layer 121 is formed on the interlayer insulating layer 101'. Subsequently, a preliminary trench structure 150 is formed by etching the upper insulating layer 121. Each preliminary trench structure 150 may have elements therein. Figure 3A The selected line isolation structure SLS is located in the region at the top. And along... Figure 3A The second horizontal direction Y is shown. The preliminary trench structure 150 can be set between the trench structures CH.

[0067] In the implementation, the channel structure CH may include, as referenced Figure 3A The first trench structure CH1 and the second trench structure CH2 are spaced apart from each other by a first distance W1, and the third trench structure CH3 and the fourth trench structure CH4 are spaced apart from each other by a second distance W2. The preliminary trench structure 150 extends from the top surface of the upper insulating layer 121 toward the laminated structure ST, and can be formed to a depth to which the preliminary trench structure 150 does not penetrate the interface between the upper insulating layer 121 and the laminated structure ST.

[0068] Reference Figure 5C and Figure 5D The initial trench structure 150 may be filled with an initial isolation structure 152. The initial isolation structure 152 may include a material that has a higher etch selectivity than the upper insulating layer 121 during a subsequent etching process. In an embodiment, the upper insulating layer 121 may be configured with an oxide, and the initial isolation structure 152 may include at least one of a nitride and a metal.

[0069] The preliminary isolation structure 152 may extend from the top surface of the upper insulating layer 121 toward the laminated structure ST, and has a depth in which the preliminary isolation structure 152 does not penetrate the laminated structure ST. The preliminary isolation structure 152 may have a bottom surface between the sacrificial layer 103', which is the adjacent sacrificial layer 103 of the upper insulating layer 121, and the upper insulating layer 121. The preliminary isolation structure 152 may be configured to be spaced apart from the sacrificial layer 103', which is the adjacent sacrificial layer 103 of the upper insulating layer 121.

[0070] Reference Figure 5E After the initial isolation structure 152 is formed, a slit 160 can be formed. The slit 160 is formed to a depth penetrating the upper insulating layer 121 and the stacked structure ST. That is, the slit 160 can be formed deeper than the initial isolation structure 152. Although not shown in the figure, a mask layer serving as an etching barrier can be provided on the upper insulating layer 121 and the initial isolation structure 152 during the etching process used to form the slit 160.

[0071] like Figure 3AAs shown, slit 160 penetrates the stacked structure ST between the first channel structure CH1 and the second channel structure CH2. Figure 3A As shown, the initial isolation structure 152 overlaps with the third channel structure CH3 and the fourth channel structure CH4.

[0072] Reference Figure 5F The sacrificial layer 103 is removed through slit 160. The interlayer space where the sacrificial layer 103 has been removed can be filled with a conductive pattern CP. The conductive pattern CP may include at least one of a metal, a metal silicide, a metal nitride, and a doped silicon layer. Each conductive pattern CP may include a low-resistance metal such as tungsten to achieve low-resistance wiring. After the conductive pattern CP, the mask layer provided for forming the slit 160 is removed, thereby exposing the upper insulating layer 121 and the initial isolation structure 152.

[0073] The conductive pattern CP can apply stress to the gate stack structure GST. According to an embodiment of this disclosure, a preliminary isolation structure 152 is formed before the conductive pattern CP. Therefore, alignment defects in the preliminary isolation structure 152 caused by the stress applied by the conductive pattern CP can be reduced. For example, unlike an embodiment of this disclosure, the preliminary isolation structure 152 can be formed after the conductive pattern CP is formed. The gate stack structure GST may bend due to the stress applied to it by the conductive pattern CP.

[0074] When the initial isolation structure 152 is formed after bending the gate stack structure GST, alignment defects in the initial isolation structure 152 may occur, and the process for position correction of the initial isolation structure 152 may be increased. According to an embodiment of the present disclosure, the conductive pattern CP is formed after the initial isolation structure 152 is pre-aligned with the position between the channel structures CH, thereby reducing alignment defects in the initial isolation structure 152 caused by the stress applied by the conductive pattern CP.

[0075] Reference Figure 5G This forms a vertical structure 162 that fills the slit 160. The vertical structure 162 may consist only of insulating material or may consist of insulating material and conductive material penetrating the insulating material. Subsequently, only the initial isolation structure 152 may be removed, thereby opening the initial trench structure 150 defined in the upper insulating layer 121.

[0076] Reference Figure 5G and Figure 5HA trench 154 penetrating at least one layer of the conductive pattern CP can be formed through an open preliminary trench structure 150. At least one conductive pattern in the conductive pattern CP adjacent to the upper insulating layer 121 can be isolated as a drain select line DSL around the third channel structure CH3 and a drain select line DSL around the fourth channel structure CH4. Although no separate masking process is performed to isolate the drain select line DSL, the trench 154 can be self-aligned between the third channel structure CH3 and the fourth channel structure CH4.

[0077] Reference Figure 5H and Figure 5I The trench 154 can be filled with the selective line isolation structure 156. The selective line isolation structure 156 may include insulating material.

[0078] Figure 6 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0079] Reference Figure 6 The memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0080] Memory device 1120 may be a multi-chip package configured with multiple flash memory chips. Memory device 1120 may include word lines configured to jointly control a first cell string and a second cell string. The word lines may surround the channel structure of the first cell string and the channel structure of the second cell string. Memory device 1120 may include a first drain select line and a second drain select line overlapping the aforementioned word lines and configured to independently control the first cell string and the second cell string. The first drain select line may surround the channel structure of the first cell string, and the second drain select line may surround the channel structure of the second cell string. The first drain select line and the second drain select line may be isolated from each other. (The above is incomplete and requires further context.) Figures 5A to 5I The process described herein can be used to isolate the first drain select line and the second drain select line from each other.

[0081] Memory controller 1110 controls memory device 1120 and may include static random access memory (SRAM) 1111, central processing unit (CPU) 1112, host interface 1113, error correction block 1114, and memory interface 1115. SRAM 1111 serves as operating memory for CPU 1112, which performs overall control operations for data exchange with memory controller 1110. Host interface 1113 includes a data exchange protocol for a host connected to memory system 1100. Error correction block 1114 detects errors in data read from memory device 1120 and corrects the detected errors. Memory interface 1115 interfaces with memory device 1120. Memory controller 1110 may also include read-only memory (ROM) for storing code data, etc., for connection to the host interface.

[0082] The memory system 1100 configured as described above can be a memory card or solid-state drive (SSD) in which the memory device 1120 is combined with the memory controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1110 can communicate with an external (e.g., a host) via one of a variety of interface protocols such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, Fast PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA) protocol, Parallel ATA (PATA) protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Integrated Drive Electronic Devices (IDE) protocol.

[0083] Figure 7 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure.

[0084] Reference Figure 7 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. When the computing system 1200 is a mobile device, it may also include a battery for providing operating voltage to the computing system 1200, and may also include an application chipset, a graphics processor, mobile DRAM, etc.

[0085] The memory system 1210 may be configured with a memory device 1212 and a memory controller 1211.

[0086] Memory device 1212 can be referenced above Figure 6 The memory device 1120 described is configured similarly.

[0087] The memory controller 1211 can be referenced above. Figure 6 The memory controller 1110 described is configured equally.

[0088] According to embodiments of this disclosure, the selective wire isolation process can be performed by dividing it into a first process before replacing the sacrificial layer of the stacked structure with a conductive pattern and a second process after replacing the sacrificial layer with the conductive pattern. Therefore, in this embodiment, structural degradation of the semiconductor memory device is reduced, thereby improving the electrical characteristics of the semiconductor memory device.

[0089] While this disclosure has been shown and described with reference to certain examples of its embodiments, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above-described examples of embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0090] In the above embodiments, all steps may be selectively performed or some steps may be omitted. In each embodiment, these steps are not necessarily performed in the order described and may be rearranged. The embodiments disclosed in this specification and drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, those skilled in the art should understand that various modifications can be made based on the technical scope of this disclosure.

[0091] Furthermore, examples of embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, it is for the purpose of explaining embodiments of this disclosure only. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. Those skilled in the art will understand that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein.

[0092] Cross-references to related applications

[0093] This application claims priority to Korean Patent Application No. 10-2021-0165572, filed on November 26, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A method for manufacturing a semiconductor memory device, the method comprising the following steps: This forms a laminated structure consisting of alternating layers of interlayer insulation and sacrificial layers; Form an upper insulating layer covering the laminated structure; A preliminary isolation structure is formed in the upper insulating layer; A slit is formed that penetrates the upper insulating layer and the laminated structure; The sacrificial layer is replaced with a conductive pattern through the slit; as well as The initial trench structure defined in the upper insulating layer is opened by removing the initial isolation structure. The step of forming the slit is performed after the step of forming the preliminary isolation structure.

2. The method according to claim 1, wherein, The interlayer insulating layer and the sacrificial layer are separated into multiple stacked structures by the slit, and The plurality of stacked structures are disposed below the initial isolation structure.

3. The method according to claim 1, wherein, The initial isolation structure is formed from the top surface of the upper insulating layer to a depth that does not penetrate the stacked structure.

4. The method according to claim 1, wherein, The initial isolation structure has a bottom surface between the sacrificial layer and the upper insulating layer, which is the sacrificial layer most adjacent to the upper insulating layer.

5. The method according to claim 1, wherein, The initial isolation structure is spaced apart from the sacrificial layer that is most adjacent to the upper insulating layer.

6. The method according to claim 1, further comprising the following steps: The initial trench structure forms a trench that penetrates at least one layer of the conductive pattern; as well as An insulating material is formed in the initial trench structure and the trench.

7. The method according to claim 6, further comprising the following step: A selection line isolation structure is formed inside the trench.

8. The method according to claim 1, further comprising the following step: A channel structure is formed that runs through the stacked structure.

9. The method according to claim 8, wherein, The channel structure includes: A first channel structure and a second channel structure, the first channel structure and the second channel structure being spaced apart from each other by a first distance; and A third channel structure and a fourth channel structure are spaced apart from each other by a second distance.

10. The method according to claim 9, wherein, The slit penetrates the stacked structure between the first channel structure and the second channel structure, and The preliminary isolation structure is disposed between the third channel structure and the fourth channel structure.

11. The method according to claim 9, wherein, The second distance is narrower than the first distance.

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