Method for improving etch residue in peripheral circuit region after word line poly layer grind

Abstract

The application provides a method for improving etching residue in a peripheral circuit region after polishing a word line polysilicon layer, comprising the following steps: S1, providing a substrate, the substrate is divided into a core region and a peripheral region, a plurality of flash memory gate structures are formed on the substrate, and a plurality of word line polysilicon layers are formed on the core region; S2, forming a sacrifice layer on the substrate; S3, forming a photoresist layer on the substrate, and exposing the peripheral region; S4, performing wet etching until a control gate in the flash memory gate structure in the peripheral region is exposed; S5, removing the photoresist layer; and S6, performing dry etching until a gate oxide layer in the flash memory gate structure in the peripheral region is exposed. The hard mask layer with uneven surface flatness in the flash memory gate structure is removed through wet etching, and then the control gate, the inter-electrode dielectric layer and the floating gate are removed through dry etching, so that etching residue is not formed, and the reliability of the device formed in the peripheral region is ensured.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for improving etching residue in the peripheral circuit area after polishing the polysilicon layer of word lines. Background Technology

[0002] Currently, flash memory has become the mainstream non-volatile memory. Based on its structure, flash memory can be divided into NOR flash memory and NAND flash memory. The main characteristics of flash memory are its ability to retain stored information for a long time without power; it also has advantages such as high integration density, fast access speed, and ease of erasing and rewriting, thus finding wide application in microcomputers, automation control, and many other fields.

[0003] Existing flash memory consists of a core memory circuit (Cell Circuit) on the substrate and peripheral circuitry surrounding the core memory circuit. The core memory circuit includes transistors with relatively small feature sizes, while the peripheral circuitry mainly consists of conventional MOS transistors with larger feature sizes, including high-voltage and medium-to-low-voltage circuits. In embedded systems, there may also be corresponding low-voltage logic circuitry. Notably, the distance between the gates of adjacent transistors in the core memory circuit is very small, while the distance between the gates of transistors in the peripheral circuitry is relatively large.

[0004] In existing technology, the devices in the flash memory cell array region, including multiple spaced flash gate structures, are fabricated first. Then, the word lines of the flash memory cell array region and the devices in the peripheral circuit region, such as logic devices in the logic area, are fabricated separately. When fabricating the word lines of the flash memory cell array region, a hard mask layer is first formed on the substrate to cover the flash memory cell array region and the peripheral circuit region. Then, multiple strip trenches are formed in the hard mask layer on the flash memory cell array region by etching. Next, a polysilicon layer is deposited on the substrate to fill the trenches. Then, the polysilicon layer of the peripheral circuit region is removed by grinding, and the exposed part of the hard mask layer is removed to make its thickness meet the requirements of subsequent etching.

[0005] Because the spacing between the multiple spaced flash gate structures in the flash memory cell array region is small and there is a height difference between this region and the peripheral circuit region, the different grinding rates in different regions result in poor uniformity of the hard mask layer thickness after grinding the word line polysilicon layer. When the subsequent etching of the hard mask layer in the peripheral circuit region and the flash gate structure below it is terminated, floating gate residue is easily formed in the gate oxide layer, which in turn affects the reliability of devices in the peripheral circuit region, such as logic devices in the logic region. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method to improve the etching residue in the peripheral circuit area after polishing the polysilicon layer of word lines, so as to solve the problem of floating gate residue when the etching of the hard mask layer and the flash memory gate structure below it in the peripheral circuit area is terminated after polishing the polysilicon layer of word lines.

[0007] To achieve the above and other related objectives, this application provides a method for improving etching residue in the peripheral circuit area after polishing the polysilicon layer of word lines, comprising:

[0008] Step S1: Provide a substrate, which is divided into a core region and a peripheral region. Multiple flash memory gate structures are formed on the substrate, and multiple word line polysilicon structures are formed on the core region.

[0009] Step S2: A sacrificial layer is formed on the substrate;

[0010] Step S3: A photoresist layer is formed on the substrate to expose the peripheral area;

[0011] Step S4: Perform wet etching until the control gate in the flash memory gate structure located in the peripheral region is exposed;

[0012] Step S5: Remove the photoresist layer;

[0013] Step S6: Perform dry etching until the gate oxide layer in the flash memory gate structure located in the peripheral region is exposed.

[0014] Preferably, the flash memory gate structure includes, from bottom to top, a gate oxide layer, a floating gate, an inter-electrode dielectric layer, a control gate, and a hard mask layer.

[0015] Preferably, the inter-electrode dielectric layer is composed of a silicon oxide-silicon nitride-silicon oxide layer.

[0016] Preferably, the material of the hard mask layer is an oxide.

[0017] Preferably, the material of the sacrificial layer is an oxide.

[0018] Preferably, the oxide is tetraethyl orthosilicate.

[0019] Preferably, the sacrificial layer is formed using plasma-enhanced chemical vapor deposition.

[0020] Preferably, the thickness of the sacrificial layer is 550 angstroms to 650 angstroms.

[0021] Preferably, the photoresist layer is removed using an ashing process.

[0022] Preferably, in step S6, the sacrificial layer of the core region is removed by dry etching.

[0023] As described above, the method for improving the etching residue in the peripheral circuit area after polishing the polysilicon layer of word lines provided in this application has the following beneficial effects: firstly, the hard mask layer with uneven surface flatness in the flash memory gate structure is removed by wet etching, and then the control gate, inter-electrode dielectric layer and floating gate are removed by dry etching, which will not form etching residue and ensure the reliability of the device formed in the peripheral area. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the cross-sectional structure of a device formed after each step of grinding the polysilicon layer of the Chinese character line and etching the peripheral circuit area in the prior art.

[0026] Figure 2 The flowchart shown is a method for improving etching residue in the peripheral circuit area after polishing the polysilicon layer of word lines according to an embodiment of this application;

[0027] Figures 3-8 The diagram shown is a schematic cross-sectional view of the device formed after each step in the method for improving the etching residue in the peripheral circuit area after polishing the polysilicon layer of word lines provided in the embodiments of this application. Detailed Implementation

[0028] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0029] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0031] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0032] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0033] like Figure 1 As shown in (a), the substrate 100 is divided into a core memory circuit region (left side of the figure) and a peripheral circuit region (right side of the figure). Multiple isolation components are formed in both the core memory circuit region and the peripheral circuit region to achieve isolation between multiple flash memory gate structures in the core memory circuit region and isolation between multiple devices in the peripheral circuit region, respectively. An isolation component is also formed between the core memory circuit region and the peripheral circuit region, but it is not shown in the figure for simplicity.

[0034] A flash memory gate structure is formed on the substrate 100. The flash memory gate structure includes: a floating gate 103 located on the gate oxide layer 102; an inter-electrode dielectric layer 105 located on the floating gate 103, wherein, for example, the inter-electrode dielectric layer 105 is composed of a silicon oxide-silicon nitride-silicon oxide layer; a control gate 106 located on the inter-electrode dielectric layer 105; and a hard mask layer 107 located on the control gate.

[0035] In the core memory circuit region, the flash memory gate structure is etched until the gate oxide layer 102 is exposed, word line polysilicon 108 is grown in the formed trench, and the polysilicon on the hard mask layer 107 is removed by chemical mechanical polishing.

[0036] like Figure 1As shown in (b), a photoresist layer 109 covering only the core memory circuit area is formed on the hard mask layer 107. Using the photoresist layer 109 as a mask, the flash memory gate structure located in the peripheral circuit area is sequentially etched by a dry etching process until the gate oxide layer 102 is exposed.

[0037] like Figure 1 As shown in (c), the photoresist layer 109 is removed by an ashing process.

[0038] Because the spacing between the multiple spaced flash gate structures in the core memory circuit region is small and there is a height difference between this region and the peripheral circuit region, the different grinding rates in different regions result in poor uniformity of the thickness of the hard mask layer 107 after grinding the word line polysilicon 108. When the etching of the flash gate structure in the peripheral circuit region is terminated, a floating gate 103 residue is formed on the gate oxide layer 102, which in turn affects the reliability of devices in the peripheral circuit region, such as logic devices in the logic region.

[0039] To address this issue, this application provides a method for improving etching residue in the peripheral circuit area after polishing the polysilicon layer of word lines.

[0040] Please see Figure 2 The document illustrates a flowchart of a method for improving etching residue in the peripheral circuit area after polishing the polysilicon layer of word lines, as provided in an embodiment of this application.

[0041] like Figure 2 As shown, the method for improving etching residue in the peripheral circuit area after polishing the polysilicon layer of word lines includes the following steps:

[0042] Step S1: Provide a substrate, which is divided into a core region and a peripheral region. Multiple flash memory gate structures are formed on the substrate, and multiple word line polysilicon structures are formed on the core region.

[0043] Step S2: A sacrificial layer is formed on the substrate;

[0044] Step S3: A photoresist layer is formed on the substrate to expose the peripheral area;

[0045] Step S4: Perform wet etching until the control gate in the flash memory gate structure located in the peripheral region is exposed;

[0046] Step S5: Remove the photoresist layer;

[0047] Step S6: Perform dry etching until the gate oxide layer in the flash memory gate structure located in the peripheral region is exposed.

[0048] In step S1, as Figure 3As shown, optionally, the substrate 300 is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the material of the substrate 300 may also include other materials, such as gallium arsenide or other III-V compounds. Those skilled in the art can select the constituent material of the substrate 300 according to the type of transistor formed on the substrate 300, therefore the type of substrate 300 should not limit the scope of protection of this invention.

[0049] The substrate 300 is divided into a core region and a peripheral region. The core region is used to form the stacked gate transistors of the core memory circuit, i.e., the flash memory gate structure; the peripheral region is used to form the MOS transistors of the peripheral circuit. For embedded flash memory, this includes the logic region used to form logic devices.

[0050] Multiple isolation components are formed in the substrate 300. For simplicity, they are not shown in the figure. The linewidth of the isolation components located in the core region is smaller than that of the isolation components located in the peripheral region. Typically, the top of the isolation components is higher than the surface of the substrate 300.

[0051] In this embodiment, the present application forms the isolation component using a shallow trench isolation process (STI), which includes, but is not limited to, shallow trench etching, oxide filling, and oxide planarization.

[0052] Shallow trench etching includes, but is not limited to, isolating oxide layers, nitride deposition, shallow trench isolation using masks, and STI shallow trench etching. STI oxide filling includes, but is not limited to, trench liner silicon oxide, trench CVD (chemical vapor deposition) oxide filling, or PVD (physical vapor deposition) oxide filling. Silicon wafer surface planarization can be achieved through various methods. Planarization can be achieved by using SOG (spin-on-glass) to fill the gaps. SOG can be composed of 80% solvent and 20% silicon dioxide. After deposition, the SOG is baked to evaporate the solvent, leaving the silicon dioxide in the gaps. Alternatively, the entire surface can be reverse-etched to reduce the overall wafer thickness. Planarization can also be effectively achieved through CMP (chemical mechanical polishing) processes, including but not limited to polishing the trench oxides (using chemical mechanical polishing) and nitride removal.

[0053] The insulating component can be composed of any insulating material such as silicon dioxide (SiO2) or a "high-k" dielectric with a high dielectric constant, for example, greater than 3.9. In some cases, the insulating component can be composed of oxide materials. Suitable materials for composing the insulating component include, for example, silicon dioxide (SiO2), hafnium oxide (HfO2), bauxite (Al2O3), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), titanium dioxide (TiO2), praseodymium oxide (Pr2O3), zirconium oxide (ZrO2), erbium oxide (ErOx), and other materials with similar properties, whether currently known or developed later.

[0054] The flash memory gate structure formed on the substrate 300 includes: a gate oxide layer 302; a floating gate 303 located on the gate oxide layer 302; an inter-electrode dielectric layer 305 located on the floating gate 303, wherein, for example, the inter-electrode dielectric layer 305 is composed of a silicon oxide-silicon nitride-silicon oxide layer; a control gate 306 located on the inter-electrode dielectric layer 305; and a hard mask layer 307 located on the control gate 306, wherein, for example, the material of the hard mask layer 307 is an oxide.

[0055] Multiple word line polysilicon 308s are formed in the core region. Exemplarily, the steps of forming the word line polysilicon 308 include: etching the flash memory gate structure of the core region until the gate oxide layer 302 is exposed; growing a polysilicon layer in the formed trench by a deposition process; and removing the polysilicon layer located outside the trench by a chemical mechanical polishing process.

[0056] In step S2, as Figure 4 As shown, a sacrificial layer 309 is formed on the substrate 300.

[0057] For example, a plasma-enhanced chemical vapor deposition process is used to form the sacrificial layer 309. The thickness of the sacrificial layer 309 can be 550 angstroms to 650 angstroms, preferably 600 angstroms.

[0058] The formation of the sacrificial layer 309 can prevent subsequent etching from damaging the word line polysilicon 308, and can also avoid the risk of dopant precipitation caused by rapid thermal annealing after doping of the word line polysilicon 308.

[0059] The preferred material for the sacrificial layer 309 is tetraethyl orthosilicate (TEOS), which has good thickness stability and uniformity, and can improve the surface morphology of the hard mask layer 307 after grinding.

[0060] To improve the subsequent etching rate, it is preferable that the material of the hard mask layer 307 is the same as that of the sacrificial layer 309.

[0061] In step S3, as Figure 5As shown, a photoresist layer 310 is formed on the substrate 300 through processes such as coating, exposure, and development, exposing the peripheral area.

[0062] In step S4, as Figure 6 As shown, wet etching is performed until the control gate 306 in the flash memory gate structure located in the peripheral region is exposed.

[0063] Since the materials of the sacrificial layer 309 and the hard mask layer 307 are usually oxides, the etchant used for wet etching can be diluted hydrofluoric acid (DHF).

[0064] The core region has a photoresist layer 310 as a mask. The feature size of the isolation component between the core region and the peripheral region is relatively large. Therefore, there is a sufficient process window to ensure that the sacrificial layer 309 and the hard mask layer 307 of the peripheral region can be completely removed by wet etching. Since the control gate 306, the inter-electrode dielectric layer 305 and the floating gate 303 are all grown in furnace tubes, the thickness uniformity is good. Therefore, the surface flatness of the control gate 306 is uniform in different areas of the peripheral region.

[0065] In step S5, as Figure 7 As shown, the photoresist layer 310 is removed.

[0066] For example, an ashing process is used to remove the photoresist layer 310. At the same time, a conventional cleaning process is used to remove residual polymer and impurities.

[0067] In step S6, as Figure 8 As shown, dry etching is performed until the gate oxide layer 302 in the flash memory gate structure located in the peripheral region is exposed.

[0068] During the etching process, the sacrificial layer 309 in the core area was also removed.

[0069] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0070] In summary, the method provided in this application for improving the etching residue in the peripheral circuit area after polishing the polysilicon layer of the word line first removes the uneven surface of the hard mask layer 307 by wet etching, and then removes the control gate 306, the inter-electrode dielectric layer 305, and the floating gate 303 by dry etching. This method avoids etching residue formation and ensures the reliability of the device formed in the peripheral area. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0071] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A method for improving etching residue in the peripheral circuit area after polishing the polysilicon layer of word lines, characterized in that, The method includes: Step S1: Provide a substrate, the substrate being divided into a core region and a peripheral region, and a plurality of flash memory gate structures are formed on the substrate. The flash memory gate structure includes a gate oxide layer, a floating gate, an inter-electrode dielectric layer, a control gate, and a hard mask layer stacked from bottom to top. A plurality of word line polysilicon is formed on the core region. Step S2: A sacrificial layer is formed on the substrate; Step S3: A photoresist layer is formed on the substrate to expose the peripheral area; Step S4: Perform wet etching until the control gate in the flash memory gate structure located in the peripheral region is exposed, and remove the sacrificial layer and hard mask layer located in the peripheral region through the wet etching. Step S5: Remove the photoresist layer; Step S6: Perform dry etching until the gate oxide layer in the flash memory gate structure located in the peripheral region is exposed. Remove the sacrificial layer located in the core region and the control gate, inter-electrode dielectric layer and floating gate located in the peripheral region by the dry etching.

2. The method according to claim 1, characterized in that, The inter-electrode dielectric layer is composed of silicon oxide-silicon nitride-silicon oxide layers.

3. The method according to claim 1, characterized in that, The material of the hard mask layer is an oxide.

4. The method according to claim 1, characterized in that, The material of the sacrificial layer is an oxide.

5. The method according to claim 4, characterized in that, The oxide is tetraethyl orthosilicate.

6. The method according to claim 1, characterized in that, The sacrificial layer is formed using a plasma-enhanced chemical vapor deposition process.

7. The method according to claim 1, characterized in that, The thickness of the sacrificial layer is 550 angstroms to 650 angstroms.

8. The method according to claim 1, characterized in that, The photoresist layer is removed using an ashing process.

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