Display device

Abstract

Disclosed is a display device, data lines are disposed on or above a substrate along a first direction, first scan lines extend through first sub-pixels along a second direction, first auxiliary patterns are disposed in the first sub-pixels along the second direction and are electrically connected to the first scan lines through one or more first contact holes in an interlayer insulating film, the first scan lines include first line portions and wider first contact portions, the first auxiliary patterns include first line pattern portions and wider first placement pattern portions, the first contact portions are connected to the first placement pattern portions through the one or more first contact holes, the first contact portions are symmetrical about a central axis of the first line portions, and the first placement pattern portions are symmetrical about a central axis of the first line pattern portions.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0166849, filed on November 29, 2021, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to a display device. Background Technology

[0004] In the manufacturing of display panels, process deviations may occur due to various reasons. As a result, signal lines, patterns, electrodes, etc., may be patterned in positions deviating from the expected locations. Because the patterned positions are offset due to process deviations, the cover layers between metals that need to contact each other may be misaligned, which can adversely affect the electrical connection between the metals.

[0005] Furthermore, during the manufacturing of display panels, defects such as bright spots or dark spots may occur in sub-pixels due to various reasons, such as the presence of impurities at various locations within the sub-pixels. For example, during the formation of the driving transistor in each sub-pixel, tiny process-induced substances may form within the driving transistor. When the driving transistor contains impurities in this way, short circuits between nodes may be caused by the impurities, and abnormal currents with very large amplitudes may flow through the driving transistor. Due to this phenomenon, abnormally bright spots may form in the sub-pixel, resulting in a sub-pixel defect. Summary of the Invention

[0006] In the field of display technology, when signal lines, patterns, electrodes, etc., are patterned at positions deviating from the expected locations due to process deviations in panel manufacturing, the cover layers between metals that are to contact each other may be misaligned, leading to problems with the electrical connection between the metals. In this regard, the inventors of this application have invented a display device that can provide a reliable contact structure even when process deviations occur in panel manufacturing.

[0007] In particular, the inventors of this application discovered through various experiments and analyses that when the overlays between metals (e.g., scan lines or auxiliary patterns) that are to come into contact with each other are misaligned, the parasitic capacitance of two adjacent sub-pixels with a flip structure (i.e., a symmetrical structure) may change, resulting in a brightness deviation between the two sub-pixels with a flip structure (i.e., a symmetrical structure).

[0008] Therefore, the inventors of this application have invented a display device that can provide a reliable electrical connection between metals and prevent brightness deviation between two sub-pixels with a flip structure (i.e., a symmetrical structure) even when the overlays between metals (e.g., scan lines or auxiliary patterns) that are to come into contact with each other are misaligned.

[0009] Embodiments of this disclosure may provide a display device having a scan line structure suitable for cases where subpixels have a flip structure, and a scan line structure that does not cause brightness deviation even in the event of process deviations.

[0010] Embodiments of this disclosure may provide a display device having a storage capacitor structure suitable for cases where subpixels have a flip structure, and a scan line structure that does not cause storage capacitor deviation even in the event of process deviation.

[0011] According to an embodiment, a display device is provided, comprising: a substrate; a data line disposed on or above the substrate along a first direction; a first scan line extending through a first sub-pixel among a plurality of sub-pixels and disposed along a second direction intersecting the first direction; a first auxiliary pattern disposed in a region of the first sub-pixel along the second direction and electrically connected to the first scan line through one or more first contact holes; and an interlayer insulating film located between the first scan line and the first auxiliary pattern and having one or more first contact holes.

[0012] The first scan line may include a first line portion having a first width in a first direction and a first contact portion having a second width in the first direction, the second width being wider than the first width. The first auxiliary pattern may include a first line pattern portion having a third width in a first direction and a first placement pattern portion having a fourth width in the first direction, the fourth width being wider than the third width. The first contact portion of the first scan line may be connected to the first placement pattern portion of the first auxiliary pattern through one or more first contact holes.

[0013] The first contact portion of the first scan line may be symmetrical about the central axis of the first line portion of the first scan line in a second direction. The first placement pattern portion of the first auxiliary pattern may be symmetrical about the central axis of the first line pattern portion in a second direction.

[0014] The display device may further include: a second scan line disposed along a second direction and adjacent to a first scan line in a first direction; and a second auxiliary pattern disposed along the second direction in a region of a second sub-pixel adjacent to the first sub-pixel along the first direction, and electrically connected to the second scan line through one or more second contact holes. An interlayer insulating film may be located between the second scan line and the second auxiliary pattern.

[0015] The second scan line may include a second line portion having a first width in the first direction and a second contact portion having a second width in the first direction. The second auxiliary pattern may include a second line pattern portion having a third width in the first direction and a second placement pattern portion having a fourth width in the first direction. The second contact portion of the second scan line may be connected to the second placement pattern portion of the first auxiliary pattern through one or more second contact holes.

[0016] The second contact portion of the second scan line may be symmetrical about the center line of the second line portion of the second scan line in the second direction. The second placement pattern portion of the second auxiliary pattern may be symmetrical about the center line of the second line pattern portion of the second auxiliary pattern in the second direction.

[0017] According to an embodiment, a display device is provided, comprising: a substrate; a first scan line disposed on or above the substrate and extending through a first sub-pixel among a plurality of sub-pixels; a first auxiliary pattern disposed in a region of the first sub-pixel and electrically connected to the first scan line through one or more first contact holes; and an interlayer insulating film located between the first scan line and the first auxiliary pattern and having one or more first contact holes.

[0018] The first scan line may be highlighted in the vertical direction to be symmetrical about the longitudinal axis. The first auxiliary pattern may be highlighted in the vertical direction to be symmetrical about the longitudinal axis.

[0019] According to an embodiment, the display device may have a scan line structure suitable for cases where sub-pixels have a flip structure, and a scan line structure that does not cause brightness deviation even in the event of process deviation.

[0020] According to an embodiment, the display device may have a storage capacitor structure suitable for cases where sub-pixels have a flip structure, and a scan line structure that will not cause storage capacitor deviation even if process deviations occur.

[0021] According to an embodiment, the display device may have a repair structure that does not cause a reduction in aperture ratio and does not occupy a large space, as well as a sub-pixel flipping structure for the repair structure. Attached Figure Description

[0022] The above and other objects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 This is a diagram illustrating the system configuration of a display device according to an embodiment;

[0024] Figure 2 The equivalent circuit of a sub-pixel in a display device according to an embodiment is shown;

[0025] Figure 3 A subpixel flipping structure in a display device according to an embodiment is shown;

[0026] Figure 4 The layout of sub-pixels having a top-emitting structure in a display device according to an embodiment is shown;

[0027] Figure 5 The equivalent circuit of the first sub-pixel and the second sub-pixel in the display device according to an embodiment is shown when the first sub-pixel and the second sub-pixel have a flip structure relative to each other;

[0028] Figure 6 The planar structure of the first sub-pixel row and the second sub-pixel row in a display device according to an embodiment is shown;

[0029] Figure 7 , Figure 8A , Figure 8B , Figure 9 , Figure 10 , Figure 11A and Figure 11B The planar structure and cross-sectional (i.e., vertical) structure of the first scan line and the second scan line in the display device according to an embodiment for a flip structure between the first sub-pixel and the second sub-pixel are shown.

[0030] Figure 12 , Figure 13A and Figure 13B A first storage capacitor structure and a second storage capacitor structure are shown in a display device according to an embodiment, which are suitable for a flip structure between a first sub-pixel and a second sub-pixel.

[0031] Figure 14 and Figure 15 These are schematic diagrams and cross-sectional views illustrating the state of the repair structure prior to repair processing in a display device according to an embodiment, where both the first and second sub-pixels, which have flip structures relative to each other, are normal sub-pixels; and

[0032] Figure 16 and Figure 17This is a schematic diagram and cross-sectional view showing the change in the repair structure after repair processing when the first sub-pixel of the first and second sub-pixels, which have flipped structures relative to each other, is a defective sub-pixel. Detailed Implementation

[0033] In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and in which the same or similar reference numerals may be used to denote the same or similar parts, even if they are shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, a detailed description of well-known functions and parts included herein will be omitted where it is determined that such detailed description may obscure the subject matter of some embodiments of the invention. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed by” as used herein are generally intended to allow for the addition of additional parts, unless these terms are used in conjunction with the term “only.” As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0034] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of the invention. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0035] When described as "connected or combined," "in contact or overlapping," etc., between the first element and the second element, it should be understood that not only can the first element be "directly connected or combined" or "directly in contact or overlapping" with the second element, but a third element can also be "inserted" between the first element and the second element, or the first element and the second element can be "connected or combined," "in contact or overlapping," etc., with each other through a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or combined," "in contact or overlapping," etc., with each other.

[0036] Various embodiments will be described in detail below with reference to the accompanying drawings.

[0037] Figure 1 This is a diagram illustrating the system configuration of the display device 100 according to an embodiment. (Refer to...) Figure 1 The display driving system of the display device 100 according to the embodiment may include a display panel 110 and a display driving circuit for driving the display panel 110.

[0038] The display panel 110 may include a display area DA for displaying images and a non-display area NDA for not displaying images. The display panel 110 may include a plurality of subpixels SP disposed on a substrate SUB for displaying images. For example, the plurality of subpixels SP may be disposed in the display area DA. In some cases, at least one subpixel SP may be disposed in the non-display area NDA. At least one subpixel SP disposed in the non-display area NDA will also be referred to as a dummy subpixel.

[0039] The display panel 110 may include multiple signal lines disposed on or above the substrate SUB to drive multiple sub-pixels SP. For example, the multiple signal lines may include data lines DL, gate lines GL, drive voltage lines, etc.

[0040] Multiple data lines DL can intersect with multiple gate lines GL. Each data line in the multiple data lines DL can be arranged to extend along a first direction. Each gate line in the multiple gate lines GL can be arranged to extend in a direction intersecting the first direction. Here, the first direction can be a column direction, and the direction intersecting the first direction can be a row direction.

[0041] The display driving circuit may include a data driver circuit 120 and a gate driver circuit 130, and also includes a controller 140 for controlling the data driver circuit 120 and the gate driver circuit 130. The data driver circuit 120 can output a data signal (also called a data voltage) corresponding to the image signal to multiple data lines DL. The gate driver circuit 130 can generate a gate signal and output the gate signal to multiple gate lines GL. The controller 140 can convert image data input from an external host 150 into image data with a data signal format that can be read by the data driver circuit 120, and provide the image data to the data driver circuit 120.

[0042] The data driver circuit 120 may include one or more source driver integrated circuits (SDICs). For example, each SDIC may be connected to the display panel 110 via a tape-on-board (TAB) method, connected to bonding pads of the display panel 110 via a chip-on-glass (COG) method or a chip-on-panel (COP) method, or implemented as a chip-on-film (COF) structure connected to the display panel 110.

[0043] The gate driver circuit 130 can be connected to the display panel 110 via the TAB method, to the bonding pads of the display panel 110 via the COG or COP method, to the display panel 110 via the COF method, or formed in the non-display area NDA of the display panel 110 via the gate in panel (GIP) method.

[0044] The display device 100 according to an embodiment may be a self-emissive display device in which the display panel 110 emits its own light. For example, the display device 100 according to an embodiment may be an organic light-emitting display device, wherein the light-emitting device is implemented as an organic light-emitting diode (OLED). As another example, the display device 100 according to an embodiment may be an inorganic light-emitting display device, wherein the light-emitting device is implemented as a light-emitting diode based on inorganic materials. As another example, the display device 100 according to an embodiment may be a quantum dot display device, wherein the light-emitting device is implemented as a quantum dot as a self-emissive semiconductor crystal.

[0045] Figure 2 The equivalent circuit of a sub-pixel SP in a display device 100 according to an embodiment is shown. (Refer to...) Figure 2 In the display device 100 according to an embodiment, each sub-pixel SP may include a light-emitting device ED and a pixel driver circuit SPC that drives the light-emitting device ED. The pixel driver circuit SPC may include a driving transistor DRT, a scanning transistor SCT, and a storage capacitor Cst.

[0046] The driving transistor DRT drives the light-emitting device ED by controlling the current flowing through it. The scanning transistor SCT transmits the data voltage Vdata to the first node N1, which serves as the gate node of the driving transistor DRT. The storage capacitor Cst can be configured to maintain its voltage for a predetermined time.

[0047] A light-emitting device (ED) may include a pixel electrode (PE), a common electrode (CE), and an emitter layer (EL) located between the pixel electrode (PE) and the common electrode (CE). The pixel electrode (PE) may be an anode (or cathode) and may be electrically connected to a second node N2 of a driving transistor (DRT). The common electrode (CE) may be a cathode (or anode), and a base voltage (EVSS) may be applied to the common electrode (CE). The ED may be, for example, a light-emitting device such as an organic light-emitting diode (OLED), an inorganic material-based light-emitting diode (LED), or a quantum dot light-emitting device.

[0048] The driving transistor DRT can be a transistor used to drive a light-emitting device (ED), and may include a first node N1, a second node N2, a third node N3, etc. The first node N1 can be a gate node and can be electrically connected to the source or drain node of the scanning transistor SCT. The second node N2 can be a source or drain node and can be electrically connected to the pixel electrode PE of the ED. The third node N3 can be a drain or source node and can be electrically connected to the driving voltage line DVL (through which the driving voltage EVDD is supplied). In the following text, for simplicity, the second node N2 will be described as a source node, and the third node N3 will be described as a drain node.

[0049] The scan transistor SCT can switch the connection between the data line DL and the first node N1 of the drive transistor DRT. The scan transistor SCT can control the connection between the first node N1 of the drive transistor DRT and the corresponding data line DL among multiple data lines DL in response to the scan signal SCAN supplied through the scan line SCL (i.e., a gate line GL).

[0050] The drain or source node of the scan transistor SCT can be electrically connected to the corresponding data line DL. The source or drain node of the scan transistor SCT can be electrically connected to the first node N1 of the driving transistor DRT. The gate node of the scan transistor SCT can be electrically connected to the scan signal line SCL to receive the scan signal SCAN applied through it. The scan transistor SCT can be turned on by the scan signal SCAN with an on-state voltage to transfer the data voltage Vdata supplied from the corresponding data line DL to the first node N1 of the driving transistor DRT.

[0051] The storage capacitor Cst can be placed between the first node N1 and the second node N2 of the driving transistor DRT.

[0052] Reference Figure 2 In the display device 100 according to an embodiment, the pixel driver circuit SPC for each sub-pixel SP may further include a sensing transistor SENT. The sensing transistor SENT can switch the connection between the second node N2 of the driving transistor DRT and the reference voltage line RVL on which the reference voltage Vref is applied.

[0053] The sensing transistor SENT can control the connection between the second node N2 of the driving transistor DRT, which is electrically connected to the pixel electrode PE of the light-emitting device ED, and the corresponding reference voltage line RVL among multiple reference voltage lines, in response to the scan signal SCAN supplied through the scan line SCL. Figure 2 In this diagram, the gate node of the sensing transistor SENT and the gate node of the scanning transistor SCT are connected to the same scan line SCL. However, this is for illustrative purposes only, and the gate nodes of the sensing transistor SENT and the scanning transistor SCT can be connected to different scan lines SCL.

[0054] The drain or source node of the sensing transistor SENT can be electrically connected to the reference voltage line RVL. The source or drain node of the sensing transistor SENT can be electrically connected to the second node N2 of the driving transistor DRT, and can also be electrically connected to the pixel electrode PE of the light-emitting device ED. The gate node of the sensing transistor SENT can be electrically connected to the scan line SCL to receive the scan signal SCAN applied through it.

[0055] Each of the driving transistor DRT, scanning transistor SCT, and sensing transistor SENT can be an N-type transistor or a P-type transistor.

[0056] Figure 2 The 3T1C structure of the subpixel SP shown is merely an example for illustration. Conversely, the subpixel structure may consist of only two transistors and one capacitor, or further include one or more transistors, or even further include one or more capacitors. All of the multiple subpixels may have the same structure, or a subset of the multiple subpixels may have different structures.

[0057] Furthermore, the display device 100 according to the embodiment may have a top-emitting structure or a bottom-emitting structure. Hereinafter, as an example, the display device 100 will be described as having a top-emitting structure.

[0058] Figure 3 The flip structure of the sub-pixel SP in the display device 100 according to an embodiment is shown. Figure 4 The layout of a sub-pixel SP having a top-emitting structure is shown in a display device 100 according to an embodiment.

[0059] Reference Figure 3 In the sub-pixel SP flip structure in the display device 100 according to the embodiment, two sub-pixels SP that are adjacent to each other in the vertical direction can be configured to be inverted relative to each other.

[0060] Reference Figure 3 The structures of the first sub-pixel SP1 in the first sub-pixel row ROW#1 and the second sub-pixel SP2 in the second sub-pixel row ROW#2 can be inverted relative to each other (i.e., have a flipped shape). The structure of each first sub-pixel SP1 may, for example, include the position and / or shape of the devices (e.g., DRT, SCT, SENT, and Cst) in the pixel driver circuit SPC of each first sub-pixel SP1. The structure of each second sub-pixel SP2 may, for example, include the position and / or shape of the devices (e.g., DRT, SCT, SENT, and Cst) in the pixel driver circuit SPC of each second sub-pixel SP2.

[0061] Reference Figure 3 The structures of the third sub-pixel SP3 in the third sub-pixel row ROW#3 and the fourth sub-pixel SP4 in the fourth sub-pixel row ROW#4 can be inverted relative to each other (i.e., the shapes are flipped). See above, referring to... Figure 3 The structures of the first sub-pixel row ROW#1 and the second sub-pixel row ROW#2, as well as the structures of the third sub-pixel row ROW#3 and the fourth sub-pixel row ROW#4, can be inverted relative to each other (i.e., the shapes are flipped). Therefore, referring to... Figure 5The structure of the second sub-pixel SP2 in the second sub-pixel row ROW#2 and the structure of the third sub-pixel SP3 in the third sub-pixel row ROW#3 can be inverted relative to each other (i.e., have a flipped shape).

[0062] Figure 4 It shows Figure 3 The light-emitting regions EA1, EA2, EA3, and EA4 of the sub-pixels SP1, SP2, SP3, and SP4 are shown. The display device 100 according to the embodiment has a top-emitting structure. Since the repair structure, which will be described later, does not reduce the aperture ratio, the light-emitting regions EA1, EA2, EA3, and EA4 of the sub-pixels SP1, SP2, SP3, and SP4 can be maximized without reducing the area due to the repair structure.

[0063] Figure 5 The equivalent circuit of the first sub-pixel SP1 and the second sub-pixel SP2 in the display device 100 according to the embodiment is shown when the first sub-pixel SP1 and the second sub-pixel SP2 have a flip structure relative to each other.

[0064] Reference Figure 5 The first sub-pixel SP1 may include a first light-emitting device ED1, a first driving transistor DRT1, a first scanning transistor SCT1, a first sensing transistor SENT1, and a first storage capacitor Cst1. The gate nodes of the first scanning transistor SCT1 and the first sensing transistor SENT1 can be connected to a single first scan line SCL1 to simultaneously receive the first scan signal SCAN1 applied through it. The first scan line SCL1 is a gate line GL.

[0065] Reference Figure 5 The second sub-pixel SP2 may include a second light-emitting device ED2, a second driving transistor DRT2, a second scanning transistor SCT2, a second sensing transistor SENT2, and a second storage capacitor Cst2. The gate node of the second scanning transistor SCT2 and the gate node of the second sensing transistor SENT2 may be connected to a single second scan line SCL2 to simultaneously receive the second scan signal SCAN2 applied through it. The second scan line SCL2 is a gate line GL.

[0066] Reference Figure 5 The first sub-pixel SP1 is included in the first sub-pixel row ROW#1, and the second sub-pixel SP2 is included in the second sub-pixel row ROW#2. Therefore, the first sub-pixel SP1 and the second sub-pixel SP2 can be connected together to a single data line DL and can be connected together to a single reference voltage line RLV.

[0067] Furthermore, since the first sub-pixel SP1 is included in the first sub-pixel row ROW#1 and the second sub-pixel SP2 is included in the second sub-pixel row ROW#2, the first sub-pixel SP1 and the second sub-pixel SP2 can be connected together to a single drive voltage line DVL.

[0068] The first sub-pixel SP1 and the second sub-pixel SP2 can be inverted relative to each other with respect to the boundary line BL between them (i.e., they have a flipped structure). In other words, the structure of the second sub-pixel SP2 and the structure of the first sub-pixel SP1 can be inverted relative to each other (i.e., they are symmetrical). In other words, the first sub-pixel SP1 and the second sub-pixel SP2 can be symmetrical about the boundary line BL.

[0069] Reference Figure 5 The structures (e.g., positions and / or shapes) of devices DRT1, SCT1, SENT1, and Cst1 in the first sub-pixel SP1 and the structures (e.g., positions and / or shapes) of devices DRT2, SCT2, SENT2, and Cst2 in the second sub-pixel SP2 can be inverted relative to each other about the boundary line BL. For example, the structures (e.g., positions and / or shapes) of devices DRT1, SCT1, SENT1, and Cst1 in the first sub-pixel SP1 and the structures (e.g., positions and / or shapes) of devices DRT2, SCT2, SENT2, and Cst2 in the second sub-pixel SP2 can be symmetrical about the boundary line BL.

[0070] Additionally, refer to Figure 5 When adjacent first sub-pixels SP1 and SP2 have a flipped structure (i.e., a symmetrical structure), if the overlays between the metals that are to contact each other (e.g., the overlay between the first scan line SCL1 and the first auxiliary pattern AUX1, and the overlay between the second scan line SCL2 and the second auxiliary pattern AUX2) are misaligned due to process variations, the first parasitic capacitance Cp1 in the first sub-pixel SP1 and the second parasitic capacitance Cp2 in the second sub-pixel SP2 may change respectively. For example, the first parasitic capacitance Cp1 may increase, while the second parasitic capacitance Cp2 may decrease. Conversely, the first parasitic capacitance Cp1 may decrease, while the second parasitic capacitance Cp2 may increase.

[0071] Therefore, the difference between the first parasitic capacitance Cp1 and the second parasitic capacitance Cp2 may increase significantly. This may affect the gate node of the first driving transistor DRT1 of the first sub-pixel SP1 and the gate node of the second driving transistor DRT2 of the second sub-pixel SP2, thereby changing the voltage state of each gate node. This change in the voltage state of each of the gate nodes of the first driving transistor DRT1 of the first sub-pixel SP1 and the second driving transistor DRT2 of the second sub-pixel SP2 may lead to a brightness deviation between the first sub-pixel SP1 and the second sub-pixel SP2, which have a flip structure (i.e., a symmetrical structure). In this regard, embodiments are proposed and will be referred to later. Figures 7 to 11B The described scan-symmetric structure.

[0072] Figure 6 The planar structure of the first sub-pixel row ROW#1 and the second sub-pixel row ROW#2 in the display device 100 according to an embodiment is shown. Figure 6 middle, Figure 5 The flip structure of the circuit shown is illustrated in the plan view of the panel.

[0073] exist Figure 6 The image shows eight sub-pixels arranged in two rows and two columns. (Reference) Figure 6 The four first sub-pixels SP1 in the first sub-pixel row ROW#1 include four first pixel driver circuits SPC1, and the four second sub-pixels SP2 in the second sub-pixel row ROW#2 adjacent to the first sub-pixel row ROW#1 include four second pixel driver circuits SPC2.

[0074] The first scan line SCL1 can be set in the first sub-pixel row ROW#1, and the second scan line SCL2 can be set in the second sub-pixel row ROW#2. The first scan line SCL1 can be connected to the gate node of the first scan transistor SCT1 and the first sensing transistor SENT1 in each of the four first sub-pixels SP1.

[0075] Two data lines DL can be set between the first sub-pixel column COL#1 and the second sub-pixel column COL#2. One of the two data lines DL can be connected to the drain node (or source node) of each of the scan transistors SCT1 and SCT2 of sub-pixels SP1 and SP2 in the first sub-pixel column COL#1, and the other data line DL can be connected to the drain node (or source node) of each of the scan transistors SCT1 and SCT2 of sub-pixels SP1 and SP2 in the second sub-pixel column COL#2.

[0076] Two data lines DL can be set between the third sub-pixel column COL#3 and the fourth sub-pixel column COL#4. One of the two data lines DL can be connected to the drain node (or source node) of each of the scan transistors SCT1 and SCT2 of sub-pixels SP1 and SP2 in the third sub-pixel column COL#3, and the other data line DL can be connected to the drain node (or source node) of each of the scan transistors SCT1 and SCT2 of sub-pixels SP1 and SP2 in the fourth sub-pixel column COL#4.

[0077] The first sub-pixel column COL#1 to the fourth sub-pixel column COL#4 can receive the reference voltage Vref through a single reference voltage line RVL. Figure 6 In the diagram, a single reference voltage line RVL can be set between the second sub-pixel column COL#2 and the third sub-pixel column COL#3.

[0078] The reference voltage line RVL can be connected to the drain node (or source node) of the first sensing transistor SENT1 in each of the four first sub-pixels SP1 via the first reference connection pattern RCP1 set in the first sub-pixel row ROW#. The reference voltage line RVL can be connected to the drain node (or source node) of the first sensing transistor SENT1 included in each of the four second sub-pixels SP2 via the second reference connection pattern RCP2 set in the second sub-pixel row ROW#2.

[0079] The first sub-pixel columns COL#1 to the fourth sub-pixel columns COL#4 can receive the driving voltage EVDD via a single driving voltage line DVL. In the illustration of Figure 8, the single driving voltage line DVL can be positioned on one side (left side) of the first sub-pixel column COL#1. The driving voltage line DVL can be connected to the third node N3 of the first driving transistor DRT3 in each of the four first sub-pixels SP1 via the first driving connection pattern DCP1 positioned in the first sub-pixel row ROW#1. The driving voltage line DVL can be connected to the third node N3 of the first driving transistor DRT3 in each of the four second sub-pixels SP2 via the second driving connection pattern DCP2 positioned in the second sub-pixel row ROW#2.

[0080] Reference Figure 6The four first pixel driver circuits SPC1 in the first sub-pixel row ROW#1 and the four second pixel driver circuits SPC2 in the second sub-pixel row ROW#2 can have a flipped structure. That is, the position and / or shape of the devices DRT2, Cst2, SCT2 and SENT2 included in the second pixel driver circuit SPC2 can be configured to be inverted about the boundary line BL relative to the position and / or shape of the devices DRT1, Cst1, SCT1 and SENT1 included in the first pixel driver circuit SPC1.

[0081] Referring to Figure 8, the signal lines SCL1, RCP1, and DCP1 arranged along the row direction in the first sub-pixel row ROW#1 and the signal lines SCL2, RCP2, and DCP2 arranged along the row direction in the second sub-pixel row ROW#2 can be configured to be inverted relative to each other. That is, the positions of the signal lines SCL1, RCP1, and DCP1 arranged along the row direction in the first sub-pixel row ROW#1 and the positions of the signal lines SCL2, RCP2, and DCP2 arranged along the row direction in the second sub-pixel row ROW#2 can be symmetrical about the boundary line BL.

[0082] The following will describe the planar structure and cross-sectional structure (i.e., vertical structure) of the first scan line SCL1 and the second scan line SCL2 suitable for the flip structure of the first sub-pixel SP1 and the second sub-pixel SP2.

[0083] Figure 7 This is a plan view showing the region through which the first scan line SCL1 extends in the first sub-pixel SP1 and the region through which the second scan line SCL2 extends in the second sub-pixel SP2 in a display device 100 according to an embodiment, where the first sub-pixel SP1 and the second sub-pixel SP2 have a flip structure relative to each other. Figure 8A The first scan line SCL1 and the first auxiliary pattern AUX1 are shown in the region of the first sub-pixel SP1 through which the first scan line SCL1 extends in the display device 100 according to an embodiment. Figure 8B The second sub-pixel SP2 and the second auxiliary pattern AUX2 are shown in the region through which the second sub-pixel SP2 extends in the display device 100 according to an embodiment. Figure 9 The diagram shows cross-sections of two overlapping portions A-A' and B-B' of the first scan line SCL1 and the first auxiliary pattern AUX1 in the region of the first sub-pixel SP1 through which the first scan line SCL1 extends, in the display device 100 according to an embodiment. Figure 10 A cross-section of the portion C-C' where the first scan line SCL1 and the first auxiliary pattern AUX1 overlap in the region of the first sub-pixel SP1 through which the first scan line SCL1 extends is shown in the display device 100 according to an embodiment.

[0084] Reference Figure 7 The display device 100 according to the embodiment may include: a substrate SUB; a first scan line SCL1 disposed on or above the substrate SUB and extending through a first sub-pixel SP1 among a plurality of sub-pixels SP; and a first auxiliary pattern AUX1 disposed in the region of the first sub-pixel SP1 and electrically connected to the first scan line SCL1 through one or more first contact holes CTH1.

[0085] For example, the first auxiliary pattern AUX1 may be located on or above the gate insulating film GI on or above the buffer layer BUF, and may include gate metal material. The first scan line SCL1 may be located on or above the interlayer insulating film ILD on or above the first auxiliary pattern AUX1, and may include source-drain metal material.

[0086] refer to Figure 7 , Figure 9 and Figure 10 According to an embodiment, the display device 100 may include an interlayer insulating film (ILD) located between a first scan line SCL1 and a first auxiliary pattern AUX1 and having one or more first contact holes CTH1.

[0087] Reference Figure 7 , Figure 8A and Figure 9 The first scan line SCL1 can protrude in the vertical direction to be symmetrical about the longitudinal axis (i.e., the axis in the second direction), and the first auxiliary pattern AUX1 can protrude in the vertical direction to be symmetrical about the longitudinal axis (i.e., the axis in the second direction).

[0088] Reference Figure 7 , Figure 8A and Figure 9 The line region SCL1_BS, which includes the portion of the first scan line SCL1 protruding in the vertical direction, and the line region AUX1_BS, which includes the portion of the first auxiliary pattern AUX1 protruding in the vertical direction, can be connected through one or more first contact holes CTH1.

[0089] Reference Figure 7 and Figure 8A In panel manufacturing, when there are no process deviations, a portion of the line region AUX1_BS, including the portion protruding from the first auxiliary pattern AUX1 in the vertical direction, can completely overlap with the line region SCL1_BS, including the portion protruding from the first scan line SCL1 in the vertical direction.

[0090] In panel manufacturing, when there is a process deviation, a portion of the line region AUX1_BS, including the portion protruding from the first auxiliary pattern AUX1 in the vertical direction, may not overlap with the line region SCL1_BS, including the portion protruding from the first scan line SCL1 in the vertical direction.

[0091] Reference Figure 7 The display device 100 according to the embodiment may further include: a substrate SUB; a second scan line SCL2 disposed on or above the substrate SUB and extending through a plurality of sub-pixels SP adjacent to a first sub-pixel SP1; and a second auxiliary pattern AUX2 disposed in the region of the second sub-pixel SP2 and electrically connected to the second scan line SCL2 through one or more second contact holes CTH2.

[0092] For example, the second auxiliary pattern AUX2 may be located on or above the gate insulating film GI on or above the buffer layer BUF, and includes gate metal material. The second scan line SCL2 may be located on or above the interlayer insulating film ILD on or above the first auxiliary pattern AUX1, and includes source-drain metal material.

[0093] Reference Figure 7 , Figure 9 and Figure 10 The interlayer insulating film (ILD) can be located between the second scan line SCL2 and the second auxiliary pattern AUX2, and has one or more second contact holes CTH2.

[0094] Reference Figure 7 and Figure 8B The second scan line SCL2 can protrude in the vertical direction to be symmetrical about the longitudinal axis (i.e., the axis in the second direction), and the second auxiliary pattern AUX2 can protrude in the vertical direction to be symmetrical about the longitudinal axis (i.e., the axis in the second direction).

[0095] Reference Figure 7 and Figure 8B The line region AUX2_BS, which includes the portion of the second auxiliary pattern AUX2 protruding in the vertical direction, and the line region SCL2_BS, which includes the portion of the second scan line SCL2 protruding in the vertical direction, can be connected through one or more contact holes CTH2.

[0096] Reference Figure 7 and Figure 8B In panel manufacturing, when there is no process deviation, a portion of the line region AUX2_BS, including the portion protruding from the second auxiliary pattern AUX2 in the vertical direction, can completely overlap with the line region SCL2_BS, including the portion protruding from the second scan line SCL2 in the vertical direction.

[0097] In panel manufacturing, when there is a process deviation, a portion of the line region AUX2_BS, including the portion protruding from the second auxiliary pattern AUX2 in the vertical direction, may not overlap with the line region SCL2_BS, including the portion protruding from the second scan line SCL2 in the vertical direction.

[0098] Reference Figure 7 and Figure 8A The display device 100 according to the embodiment may include: a substrate SUB; a data line DL disposed on or above the substrate SUB along a first direction; a first scan line SCL1 disposed in a second direction intersecting the first direction; and a first auxiliary pattern AUX1 disposed in the region of the first sub-pixel SP1 among a plurality of sub-pixels SP along the second direction and electrically connected to the first scan line SCL1 through one or more first contact holes CTH1.

[0099] Reference Figure 7 , Figure 8A and Figure 9 The first scan line SCL1 may include a first line portion SCL1_LP having a first width D1 in a first direction and a contact portion SCL1_BS having a second width D2 in the first direction, wherein the second width D2 is wider than the first width D1. The first auxiliary pattern AUX1 may include a first line pattern portion AUX1_LP having a third width D3 in a first direction and a first placement pattern portion AUX1_BS having a fourth width D4 in the first direction, wherein the fourth width D4 is wider than the third width D3.

[0100] Reference Figure 7 , Figure 8A and Figure 9 The first contact portion SCL1_BS of the first scan line SCL1 can be connected to the first placement pattern portion AUX1_BS of the first auxiliary pattern AUX1 through one or more first contact holes CTH1.

[0101] Reference Figure 7 , Figure 8A and Figure 9 The first contact portion SCL1_BS of the first scan line SCL1 can be symmetrical about the central axis AX1 of the first line portion SCL1_LP of the first scan line SCL1 in the second direction. The first placement pattern portion AUX1_BS of the first auxiliary pattern AUX1 can be symmetrical about the central axis AX1' of the first line pattern portion AUX1_LP of the first auxiliary pattern AUX1 in the second direction.

[0102] Reference Figure 7 , Figure 8A and Figure 9The first width D1 of the first line portion SCL1_LP in the first scan line SCL1 can correspond to the third width D3 of the first line pattern portion AUX1_LP in the first auxiliary pattern AUX1. The second width D2 of the first contact portion SCL1_BS in the first scan line SCL1 can correspond to the fourth width D4 of the first placement pattern portion AUX1_BS in the first auxiliary pattern AUX1.

[0103] Reference Figure 8A In the first scan line SCL1, the length L1 by which the first contact portion SCL1_BS protrudes from the first line portion SCL1_LP in a direction opposite to the first direction can be the same as the length L2 by which the first contact portion SCL1_BS protrudes from the first line portion SCL1_LP in the first direction. In the first auxiliary pattern AUX1, the length L3 by which the first placement pattern portion AUX1_BS protrudes from the first line pattern portion AUX1_LP in a direction opposite to the first direction can be the same as the length L4 by which the first placement pattern portion AUX1_BS protrudes from the first line pattern portion AUX1_LP in the first direction.

[0104] Reference Figure 6 and Figure 7 In addition to the first driving transistor DRT1, the first scanning transistor SCT1 and the first sensing transistor SENT1, the first sub-pixel SP1 may further include a first storage capacitor Cst1.

[0105] Reference Figure 7 The first scan line SCL1 and the first auxiliary pattern AUX1 may intersect with the first active layer ACT1 of the first scan transistor SCT1 in the first sub-pixel SP1. The first scan line SCL1 and the first auxiliary pattern AUX1 may intersect with the first active layer ACT1 of the first sensing transistor SENT1 in the first sub-pixel SP1.

[0106] The gate node of the first scan transistor SCT1 can receive the first scan signal from the first scan line SCL1. The gate node of the first sensing transistor SENT1 can receive the first scan signal from the first scan line SCL1.

[0107] Reference Figure 6 and Figure 7 In addition to the second driving transistor DRT2, the second scanning transistor SCT2, and the second sensing transistor SENT2, the second sub-pixel SP2 may further include a second storage capacitor Cst2.

[0108] Reference Figure 7The second scan line SCL2 and the second auxiliary pattern AUX2 may intersect with the second active layer ACT2 of the second scan transistor SCT2 in the second sub-pixel SP2. The second scan line SCL2 and the second auxiliary pattern AUX2 may intersect with the second active layer ACT2 of the second sensing transistor SENT2 in the second sub-pixel SP2.

[0109] The gate node of the second scan transistor SCT2 can receive the second scan signal from the second scan line SCL2. The gate node of the second sensing transistor SENT2 can receive the second scan signal from the second scan line SCL2.

[0110] Reference Figure 7 The first storage capacitor Cst1 of the first sub-pixel SP1 may include a first plate PLT1 and a second plate PLT2.

[0111] The first plate PLT1 may be a metal corresponding to the first node N1, which serves as the gate node of the first driving transistor DRT1. The first plate PLT1 may be the source electrode (or drain electrode) of the first scanning transistor SCT1, or a metal electrically connected to the source electrode (or drain electrode) of the first scanning transistor SCT1. The first plate PLT1 may be a conductive portion of the first active layer ACT1 electrically corresponding to the source node (or drain node) of the first scanning transistor SCT1.

[0112] The second plate PLT2 can be a metal corresponding to the second node N2, which is the source node (or drain node) of the first driving transistor DRT1. The second plate PLT2 can be the source node (or drain node) of the first sensing transistor SENT1, or a metal electrically connected to the source node (or drain node) of the first sensing transistor SENT1. The second plate PLT2 can be a conductive portion of the first active layer ACT1 electrically corresponding to the source node (or drain node) of the first sensing transistor SENT1.

[0113] Reference Figure 7 The second storage capacitor Cst2 of the second sub-pixel SP2 may include a third plate PLT3 and a fourth plate PLT4.

[0114] The third plate PLT3 can be a metal corresponding to the first node N1, which serves as the gate node of the second driving transistor DRT2. The third plate PLT3 can be the source node (or drain node) of the second scanning transistor SCT2, or a metal electrically connected to the source node (or drain node) of the second scanning transistor SCT2. The third plate PLT3 can be a conductive portion of the second active layer ACT2 electrically corresponding to the source node (or drain node) of the second scanning transistor SCT2.

[0115] The fourth plate PLT4 can be a metal corresponding to the second node N2, which is the source node (or drain node) of the second driving transistor DRT2. The fourth plate PLT4 can be the source node (or drain node) of the second sensing transistor SENT2, or a metal electrically connected to the source node (or drain node) of the second sensing transistor SENT2. The fourth plate PLT4 can be a conductive portion of the second active layer ACT2 electrically corresponding to the source node (or drain node) of the second sensing transistor SENT2.

[0116] Reference Figure 7 and Figure 8B The display device 100 according to an embodiment may further include a second scan line SCL2 and a second auxiliary pattern AUX2. The second scan line SCL2 is disposed in a second direction and adjacent to the first scan line SCL1 in a first direction. The second auxiliary pattern AUX2 is disposed along the second direction in the region of a second sub-pixel SP2 that is adjacent to the first sub-pixel SP1 in the first direction among a plurality of sub-pixels, and is electrically connected to the second scan line SCL2 through one or more second contact holes CTH2.

[0117] Reference Figure 7 and Figure 8B The second scan line SCL2 can extend in the vertical direction to be symmetrical about the longitudinal axis (i.e., the axis in the second direction). The second auxiliary pattern AUX2 can extend in the vertical direction to be symmetrical about the longitudinal axis (i.e., the axis in the second direction).

[0118] Reference Figure 7 and Figure 8B The second scan line SCL2 may include: a second line portion SCL2_LP having a first width D1 in a first direction; and a second contact portion SCL2_BS having a second width D2 in the first direction, wherein the second width D2 is wider than the first width D1. The second auxiliary pattern AUX2 may include: a second line pattern portion AUX2_LP having a third width D3 in a first direction; and a second placement pattern portion AUX2_BS having a fourth width D4 in a first direction, wherein the fourth width D4 is wider than the third width D3 in the first direction.

[0119] Reference Figure 7 and 8B The second contact portion SCL2_BS of the second scan line SCL2 can be connected to the second placement pattern portion AUX2_BS of the second auxiliary pattern AUX2 through one or more second contact holes CTH2. The second contact portion SCL2_BS of the second scan line SCL2 can be symmetrical about the central axis of the second line portion SCL2_LP of the second scan line SCL2 in a second direction.

[0120] The second placement pattern part AUX2_BS of the second auxiliary pattern AUX2 can be symmetrical about the central axis AX2' of the second line pattern part AUX2_LP of the second auxiliary pattern AUX2 in the second direction.

[0121] Reference Figure 8B In the second scan line SCL2, the length L1 of the second contact portion SCL2_BS protruding from the second line portion SCL2_LP in the direction opposite to the first direction can be the same as the second length L2 of the second contact portion SCL2_BS protruding from the second line portion SCL2_LP in the first direction.

[0122] Reference Figure 8B In the second auxiliary pattern AUX2, the length L3 of the second placement pattern portion AUX2_BS protruding from the second line pattern portion AUX2_LP in a direction opposite to the first direction can be the same as the length L4 of the second placement pattern portion AUX2_BS protruding from the second line pattern portion AUX2_LP in the first direction.

[0123] As described above, the first sub-pixel SP1 and the second sub-pixel SP2 have a flip structure relative to each other; that is, the second sub-pixel SP2 is a flip structure of the first sub-pixel SP1, and the first sub-pixel SP1 is a flip structure of the second sub-pixel SP2. Therefore, the positions of the first scanning transistor SCT1 and the second scanning transistor SCT2 can be symmetrical about each other with respect to the boundary line between the first sub-pixel SP1 and the second sub-pixel SP2.

[0124] Reference Figure 7 and Figure 8A as well as Figure 9 In the A-A' cross-sectional view, the first contact portion SCL1_BS of the first scan line SCL1 and the first placement pattern portion AUX1_BS of the first auxiliary pattern AUX1 can be symmetrical about the axes AX1 and AX', respectively.

[0125] Reference Figure 7 and Figure 8A as well as Figure 9 In the B-B' cross-sectional view, the first line portion SCL1_LP of the first scan line SCL1 and the first line pattern portion AUX1_LP of the first auxiliary pattern AUX1 can be symmetrical about the axes AX1 and AX' in the second direction.

[0126] Reference Figure 7 and 8A as well as Figure 10In the C-C' cross-sectional view, the first contact portion SCL1_BS of the first scan line SCL1 and the first placement pattern portion AUX1_BS of the first auxiliary pattern AUX1 can be connected to each other through one or more first contact holes CTH1. The first contact portion SCL1_BS of the first scan line SCL1 and the first placement pattern portion AUX1_BS of the first auxiliary pattern AUX1 can be located between the two first active layers ACT1.

[0127] Reference Figure 10 The driving voltage line DVL and data line DL can be located in a shielding metal layer beneath the buffer layer BUF. This shielding metal layer can be a layer in which shielding metal is formed beneath the channel of the driving transistor DRT. Here, the shielding metal will also be referred to as optical shielding.

[0128] Figure 11A and Figure 11B This is a plan view showing the area through which the first scan line SCL1 extends when the first auxiliary pattern AUX1 and the second auxiliary pattern AUX2 are offset in a first direction and in a direction opposite to the first direction, in response to a process deviation in the manufacturing process of the display device 100 according to an embodiment.

[0129] When no process deviation occurs in the panel manufacturing process, the entire first auxiliary pattern AUX1 can overlap with the first scan line SCL1. In this case, the first placement pattern portion AUX1_BS of the first auxiliary pattern AUX1 can be configured to include all or one or more first contact holes CTH1.

[0130] Conversely, when process deviations occur in the panel manufacturing process, such as Figure 11A and Figure 11B As shown, a portion of the first auxiliary pattern AUX1 may not overlap with the first scan line SCL1.

[0131] Reference Figure 11A and 11B This is because the first contact portion SCL1_BS of the first scan line SCL1 is configured to be symmetrical about the longitudinal axis (i.e., the axis in the second direction) while protruding from the surrounding portion in the first direction and in the direction opposite to the first direction, and the first placement pattern portion AUX1_BS of the first auxiliary pattern AUX1 is configured to be symmetrical about the longitudinal axis (i.e., the axis in the second direction) while protruding from the surrounding portion in the first direction and in the direction opposite to the first direction.

[0132] Therefore, process deviations can occur during panel manufacturing, even if a portion of the first auxiliary pattern AUX1 does not overlap with the first scan line SCL1, such as Figure 11A and Figure 11BAs shown, the first placement pattern portion AUX1_BS of the first auxiliary pattern AUX1 can be configured to include all or one or more first contact holes CTH1.

[0133] Reference Figure 11A When the first auxiliary pattern AUX1 is patterned at a position offset along the first direction due to process deviations occurring in the panel manufacturing process, a portion of the first auxiliary pattern AUX1 may not overlap with the first scan line SCL1.

[0134] Reference Figure 11B When the first auxiliary pattern AUX1 is patterned at a position offset in the opposite direction to the first direction due to process deviations occurring in the panel manufacturing process, a portion of the first auxiliary pattern AUX1 may not overlap with the first scan line SCL1.

[0135] Reference Figure 11A and Figure 11B In the event of a process deviation in the panel manufacturing process, when a portion of the first auxiliary pattern AUX1 does not overlap with the first scan line SCL1, a portion of the second auxiliary pattern AUX2 may not overlap with the second scan line SCL2.

[0136] Here, the area of ​​the portion of the first auxiliary pattern AUX1 that does not overlap with the first scan line SCL1 can be the same as the area of ​​the portion of the second auxiliary pattern AUX2 that does not overlap with the second scan line SCL2.

[0137] As described above, even if a process deviation has occurred in the panel manufacturing process, the first placement pattern portion AUX1_BS of the first auxiliary pattern AUX1 can be configured to include all or one or more first contact holes CTH1, and the second placement pattern portion AUX2_BS of the second auxiliary pattern AUX2 can be configured to include all or one or more second contact holes CTH2.

[0138] Therefore, the electrical connection between the first auxiliary pattern AUX1 and the first scan line SCL1 can be formed normally, and the electrical connection between the second auxiliary pattern AUX2 and the second scan line SCL2 can be formed normally.

[0139] Therefore, when the first sub-pixel SP1 and the second sub-pixel SP2, which are adjacent to each other, have a flip structure, even if the cover layer between the first scan line SCL1 and the first auxiliary pattern AUX1, or the cover layer between the second scan line SCL2 and the second auxiliary pattern AUX2, which are to be in contact with each other, is misaligned due to process deviation, capacitance deviation in the sub-pixel with the flip structure (i.e., symmetrical structure), that is, the deviation between the first parasitic capacitance Cp1 in the first sub-pixel SP1 and the second parasitic capacitance Cp2 in the second sub-pixel SP2, can be prevented, thereby reducing the brightness deviation between the first sub-pixel SP1 and the second sub-pixel SP2 with the flip structure (i.e., symmetrical structure).

[0140] When the first sub-pixel SP1 and the second sub-pixel SP2 do not have a flip structure, during panel manufacturing, even if the first plate PLT1 of the first storage capacitor Cst1 and the third plate PLT3 of the second storage capacitor Cst2 are patterned at a position offset in the first direction or in the opposite direction, both the first storage capacitor Cst1 and the second storage capacitor Cst2 can be increased or decreased. Therefore, there is no deviation between the first storage capacitor Cst1 and the second storage capacitor Cst2.

[0141] When the first sub-pixel SP1 and the second sub-pixel SP2 have a flip structure as described in the embodiment, process deviations may occur during the manufacturing of the panel. Therefore, when the first plate PLT1 of the first storage capacitor Cst1 and the third plate PLT3 of the second storage capacitor Cst2 are patterned at a position offset in the first direction or the opposite direction, one of the first storage capacitor Cst1 and the second storage capacitor Cst2 may increase in size, while the other may decrease. Thus, a deviation may occur between the first storage capacitor Cst1 and the second storage capacitor Cst2.

[0142] Figure 12 , Figure 13A and Figure 13B A storage capacitor structure suitable for a flip structure between a first sub-pixel SP1 and a second sub-pixel SP2 is shown in a display device according to an embodiment.

[0143] Reference Figure 12 In order to reduce the storage capacitor deviation in the sub-pixel flip structure, the first storage capacitor Cst1 may have a compensation pattern structure protruding in the first direction and in the direction opposite to the first direction, and the second storage capacitor Cst2 may have a compensation pattern structure protruding in the first direction and in the direction opposite to the first direction.

[0144] Reference Figure 12The first storage capacitor Cst1 of the first sub-pixel SP1 may include a first plate PLT1 and a second plate PLT2. The first plate PLT1 may include a first compensation pattern CCP1 extending in a direction opposite to the first direction such that it does not overlap with the second plate PLT2, and a second compensation pattern CCP2 extending in the first direction such that it does not overlap with the second plate PLT2.

[0145] Reference Figure 12 The second storage capacitor Cst2 of the second sub-pixel SP2 may include a third plate PLT3 and a fourth plate PLT4. The third plate PLT3 may include a third compensation pattern CCP3 extending in a direction opposite to the first direction such that it does not overlap with the fourth plate PLT4, and a fourth compensation pattern CCP4 extending in the first direction such that it does not overlap with the fourth plate PLT4.

[0146] Reference Figure 12 The shapes of the first storage capacitor Cst1 and the second storage capacitor Cst2 can be symmetrical about the boundary line between the first sub-pixel SP1 and the second sub-pixel SP2. Therefore, the shape of the first compensation pattern CCP1 can correspond to the shape of the fourth compensation pattern CCP4, and the shape of the second compensation pattern CCP2 can correspond to the shape of the third compensation pattern CCP3.

[0147] Reference Figure 12 The width W1 of the first compensation pattern CCP1 can be the same as the width W2 of the second compensation pattern CCP2. The width W3 of the third compensation pattern CCP3 can be the same as the width W4 of the fourth compensation pattern CCP4.

[0148] Reference Figure 12 When no process deviation occurs during panel manufacturing, the entire first auxiliary pattern AUX1 can overlap with the first scan line SCL1. When the entire first auxiliary pattern AUX1 overlaps with the first scan line SCL1, the area size S1 of the first compensation pattern CCP1 can be the same as the area size S4 of the fourth compensation pattern CCP4, and the area size S2 of the second compensation pattern CCP2 can be the same as the area size S3 of the third compensation pattern CCP3. Therefore, when no process deviation occurs, the first storage capacitor Cst1 and the second storage capacitor Cst2 can have the same capacitance.

[0149] Reference Figure 13A When a process deviation occurs during panel manufacturing, the first plate PLT1 of the first storage capacitor Cst1 and the third plate PLT3 of the second storage capacitor Cst2 can be patterned at a position offset along the first direction. In this case, a portion of the first auxiliary pattern AUX1 may not overlap with the first scan line SCL1.

[0150] Here, the area S1 of the first compensation pattern CCP1 can be smaller than the area S4 of the fourth compensation pattern CCP4, and the area S2 of the second compensation pattern CCP2 can be larger than the area S3 of the third compensation pattern CCP3. Therefore, even in the event of a process deviation, the overlap area between the first board PLT1 and the second board PLT2 can be maintained the same as before the process deviation occurred, and the overlap area between the third board PLT3 and the fourth board PLT4 can also be maintained the same as before the process deviation occurred. Therefore, even in the event of a process deviation, the first storage capacitor Cst1 and the second storage capacitor Cst2 can have the same capacitance.

[0151] Reference Figure 13B When a process deviation occurs during panel manufacturing, the first plate PLT1 of the first storage capacitor Cst1 and the third plate PLT3 of the second storage capacitor Cst2 can be patterned at a position offset in a direction opposite to the first direction. In this case, a portion of the first auxiliary pattern AUX1 may not overlap with the first scan line SCL1.

[0152] Here, the area size S1 of the first compensation pattern CCP1 can be larger than the area size S4 of the fourth compensation pattern CCP4, and the area size S2 of the second compensation pattern CCP2 can be smaller than the area size S3 of the third compensation pattern CCP3. Therefore, even in the event of a process deviation, the overlap area between the first board PLT1 and the second board PLT2 can be maintained as before the process deviation occurred, and the overlap area between the third board PLT3 and the fourth board PLT4 can also be maintained as before the process deviation occurred. Therefore, even in the event of a process deviation, the first storage capacitor Cst1 and the second storage capacitor Cst2 can have the same capacitance.

[0153] Furthermore, in the display device 100 according to the embodiment, a repair structure suitable for the first sub-pixel SP1 and the second sub-pixel SP2 having a flip structure can be disclosed. In the following description of the repair structure, the first sub-pixel SP1 and the second sub-pixel SP2 having a flip structure will be used as examples. Here, the defective sub-pixel SP is referred to as the bad sub-pixel, and the non-defective sub-pixel SP is referred to as the normal sub-pixel SP.

[0154] The repair in the display device 100 according to the embodiment can be done by stopping the operation of the pixel driver circuit SPC of the bad sub-pixel BadSP and driving the light-emitting device ED of the bad sub-pixel BadSP with the pixel driver circuit SPC of the normal sub-pixel NormalSP, so that light can be emitted from the bad sub-pixel BadSP.

[0155] Repair in the display device 100 according to an embodiment may include cutting repair and soldering repair. Cutting repair may be a process of cutting the main points (e.g., cutting points) of the pixel driver circuit SPC that may stop the operation of the bad sub-pixel Bad SP. Soldering repair may be a process of soldering the main points (e.g., solder joints) that can electrically connect the pixel driver circuit SPC of the normal sub-pixel Normal SP and the pixel electrode PE of the light-emitting device ED, so that the light-emitting device ED of the bad sub-pixel can be driven using the pixel driver circuit SPC of the normal sub-pixel.

[0156] The display device 100 according to the embodiment has a repair structure capable of bottom repair. Therefore, it does not cause a decrease in the aperture ratio of either the first sub-pixel SP1 or the second sub-pixel SP2.

[0157] The repair structure according to an embodiment may include a weld repair line WDRL, along which welding is performed during weld repair. The weld repair line WDRL is located only adjacent to the boundary line BL between the first sub-pixel SP1 and the second sub-pixel SP2. More specifically, one end of the weld repair line WDRL may overlap with a portion of one end of the first pixel electrode PE1 of the first sub-pixel SP1, and the other end of the weld repair line WDRL may overlap with a portion of one end of the second pixel electrode PE2 of the second sub-pixel SP2.

[0158] Since the weld repair line WDRL is located only adjacent to the boundary line BL between the first sub-pixel SP1 and the second sub-pixel SP2, the space for the first pixel driver circuit SPC1 (for the first sub-pixel SP1) and the space for the second pixel driver circuit SPC2 (for the second sub-pixel SP2) are not reduced. In other words, the repair structure according to the embodiment does not result in a reduction in aperture ratio or hinder the achievement of high resolution. The above-described repair structure according to the embodiment will be described in more detail below.

[0159] Figure 14 and Figure 15This is a schematic diagram and cross-sectional view showing the state of the repair structure in the display device 100 according to an embodiment, before the repair process, where the first sub-pixel SP1 and the second sub-pixel SP2, which have flip structures relative to each other, are both normal sub-pixels (Normal SP).

[0160] Reference Figure 14 and Figure 15 The first sub-pixel SP1 may include a first light-emitting device ED1 and a first pixel driver circuit SPC1 for driving the first light-emitting device ED1. The first light-emitting device ED1 may include a first pixel electrode PE1, and the first pixel driver circuit SPC1 may be connected to a data line DL, a drive voltage line DVL, and a reference voltage line RVL.

[0161] Reference Figure 14 and 15 The second sub-pixel SP2 may include a second light-emitting device ED2 and a second pixel driver circuit SPC2 for driving the second light-emitting device ED2. The second light-emitting device ED2 may include a second pixel electrode PE2, and the second pixel driver circuit SPC2 may be connected to the data line DL, the drive voltage line DVL, and the reference voltage line RVL.

[0162] Reference Figure 14 and Figure 15 Since both the first sub-pixel SP1 and the second sub-pixel SP2 are normal sub-pixels (NormalSP), the solder repair line WDRL can be connected to only one of the first pixel driver circuit SPC1 and the second pixel driver circuit SPC2. For example, the solder repair line WDRL can be electrically connected only to the second pixel driver circuit SPC2 of the first pixel driver circuit SPC1 and the second pixel driver circuit SPC2.

[0163] Reference Figure 14 and 15 When both the first sub-pixel SP1 and the second sub-pixel SP2 are normal sub-pixels, the first light-emitting device ED1 can be supplied with driving current Ied from the first driving transistor DRT1 of the first pixel driver circuit SPC1, and the second light-emitting device ED2 can be supplied with driving current Ied from the second driving transistor DRT2 of the second pixel driver circuit SPC2.

[0164] Reference Figure 14 and Figure 15 The first sub-pixel SP1 may include a first light-emitting device ED1 and a first pixel driver circuit SPC1, and the first pixel driver circuit SPC1 may include a first driving transistor DRT1, a first scanning transistor SCT1 and a first storage capacitor Cst1.

[0165] Reference Figure 14 and Figure 15 The second sub-pixel SP2 may include a second light-emitting device ED2 and a second pixel driver circuit SPC2. The second pixel driver circuit SPC2 may include a second driving transistor DRT2, a second scanning transistor SCT2, and a second storage capacitor Cst2.

[0166] Reference Figure 14 and Figure 15 The second sub-pixel SP2 can be configured to be adjacent to the first sub-pixel SP1 and have a flipped structure relative to the first sub-pixel SP1. The first driving transistor DRT1 and the second driving transistor DRT2 can be arranged adjacent to each other, such that the first sub-pixel SP1 and the second sub-pixel SP2 are configured to be inverted relative to each other and form a repair structure. Therefore, the first driving transistor DRT1 and the second driving transistor DRT2 can be located between the first scanning transistor SCT1 and the second scanning transistor SCT2 (see [link to documentation]). Figure 6 ).

[0167] Reference Figure 14 and Figure 15 The first shielding metal LS1 and the second shielding metal SL2 can be disposed on or above the substrate SUB. The first shielding metal LS1 can be located below the first driving transistor DRT1. The second shielding metal LS2 can be located below the second driving transistor DRT2.

[0168] Figure 16 and Figure 17 This is a schematic diagram and cross-sectional view showing the change in the repair structure after repair processing is performed when the first sub-pixel SP1, which has a flipped structure relative to each other, is a bad sub-pixel SP. Therefore, the change in the repair structure due to the repair processing will be described in the following text.

[0169] Reference Figure 16 and Figure 17 When the first sub-pixel SP1 in the first sub-pixel SP1 and the second sub-pixel SP2 is a bad sub-pixel, the first light-emitting device ED1 can be supplied with driving current from the second driving transistor DRT2.

[0170] Reference Figure 16 and Figure 17 When the first sub-pixel SP1 in the first sub-pixel SP1 and the second sub-pixel SP2 is a bad sub-pixel, the solder repair line WDRL can be electrically connected to the first shielding metal LS1.

[0171] Reference Figure 16 and Figure 17When the first sub-pixel SP1 in the first sub-pixel SP1 and the second sub-pixel SP2 is a bad sub-pixel, the drain node or source node of the first scanning transistor SCT1 can be electrically disconnected from the data line DL which is electrically connected to the drain node or source node of the second scanning transistor SCT2.

[0172] Reference Figure 16 and Figure 17 When the first sub-pixel SP1 in the first sub-pixel SP1 and the second sub-pixel SP2 is a bad sub-pixel, the drain node or source node of the first sensing transistor SENT1 can be electrically disconnected from the reference voltage line RVL which is electrically connected to the drain node or source node of the second sensing transistor SENT2.

[0173] Reference Figure 16 and 17 Due to the welding repair, the first portion PART1 of the welding repair line WDRL, inserted between the first shielding metal LS1 and the first source electrode SE1, can be electrically connected to the first shielding metal LS1. Due to the welding repair, a welding connection pattern WCP can be formed between the first portion PART1 of the welding repair line WDRL and the first shielding metal LS1.

[0174] The above description has been presented to enable any person skilled in the art to make and use the technical concepts of the invention, and the above description is provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The above description and drawings provide examples of the technical concepts of the invention and are for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the invention. Therefore, the scope of the invention is not limited to the embodiments shown, but should be accorded the widest scope consistent with the claims. The scope of protection of the invention should be interpreted based on the appended claims, and all technical concepts within their equivalent scope should be understood to be included within the scope of the invention.

Claims

1. A display device, comprising: substrate; A data line, wherein the data line is disposed on the substrate along a first direction; A first scan line extends through a first sub-pixel among a plurality of sub-pixels and is disposed along a second direction intersecting the first direction; A first auxiliary pattern is disposed in the region of the first sub-pixel along the second direction and electrically connected to the first scan line through one or more first contact holes; as well as An interlayer insulating film, wherein the interlayer insulating film is located between the first scan line and the first auxiliary pattern and has the one or more first contact holes. The first scan line includes a first line portion having a first width in the first direction and a first contact portion having a second width in the first direction, wherein the second width is wider than the first width. The first auxiliary pattern includes a first line pattern portion having a third width in the first direction and a first placement pattern portion having a fourth width in the first direction, wherein the fourth width is wider than the third width. The first contact portion of the first scan line is connected to the first placement pattern portion of the first auxiliary pattern through one or more first contact holes. The first contact portion of the first scan line is symmetrical about the central axis of the first line portion of the first scan line in the second direction, and The first placement pattern portion of the first auxiliary pattern is symmetrical about the central axis of the first line pattern portion in the second direction.

2. The display device according to claim 1, wherein, The first width corresponds to the third width, and the second width corresponds to the fourth width.

3. The display device according to claim 1, wherein, The first scan line is configured such that the length by which the first contact portion protrudes from the first line portion along the first direction is the same as the length by which the first contact portion protrudes from the first line portion along a direction opposite to the first direction.

4. The display device according to claim 1, wherein, The first auxiliary pattern is configured such that the length by which the first placement pattern portion protrudes from the first line pattern portion along the first direction is the same as the length by which the first placement pattern portion protrudes from the first line pattern portion along a direction opposite to the first direction.

5. The display device according to claim 1, wherein, The first scan line and the first auxiliary pattern intersect with the active layer of the first scan transistor included in the first sub-pixel, and The gate node of the first scanning transistor receives the first scan signal from the first scan line.

6. The display device according to claim 1, wherein, The entire first auxiliary pattern overlaps with the first scan line, and the first placement pattern portion of the first auxiliary pattern is configured to include all of the one or more first contact holes.

7. The display device according to claim 1, wherein, A portion of the first auxiliary pattern does not overlap with the first scan line, and the first placement pattern portion of the first auxiliary pattern is configured to include all of the one or more first contact holes.

8. The display device according to claim 1, further comprising: A second scan line is disposed along the second direction and is adjacent to the first scan line in the first direction; as well as A second auxiliary pattern is disposed along the second direction in the region of a second sub-pixel adjacent to the first sub-pixel in the first direction among the plurality of sub-pixels, and is electrically connected to the second scan line through one or more second contact holes. The interlayer insulating film is located between the second scan line and the second auxiliary pattern. The second scan line includes a second line portion having the first width in the first direction and a second contact portion having the second width in the first direction. The second auxiliary pattern includes a second line pattern portion having the third width in the first direction and a second placement pattern portion having the fourth width in the first direction. The second contact portion of the second scan line is connected to the second placement pattern portion of the first auxiliary pattern through one or more second contact holes. The second contact portion of the second scan line is symmetrical about the center line of the second line portion of the second scan line in the second direction, and The second placement pattern portion of the second auxiliary pattern is symmetrical about the center line of the second line pattern portion of the second auxiliary pattern in the second direction.

9. The display device according to claim 8, wherein, The first sub-pixel includes a first scanning transistor, and the second sub-pixel includes a second scanning transistor. The positions of the first scanning transistor and the second scanning transistor are symmetrical about each other with respect to the boundary line between the first sub-pixel and the second sub-pixel.

10. The display device according to claim 9, wherein, When a portion of the first auxiliary pattern does not overlap with the first scan line, a portion of the second auxiliary pattern does not overlap with the second scan line, and The first placement pattern portion of the first auxiliary pattern is configured to include all of the one or more first contact holes, and the second placement pattern portion of the second auxiliary pattern is configured to include all of the one or more second contact holes.

11. The display device according to claim 10, wherein, The area of ​​the portion of the first auxiliary pattern that does not overlap with the first scan line is the same as the area of ​​the portion of the second auxiliary pattern that does not overlap with the second scan line.

12. The display device according to claim 9, wherein, The first sub-pixel further includes a first storage capacitor, which comprises a first plate and a second plate. The first plate includes a first compensation pattern extending in a direction opposite to the first direction such that it does not overlap with the second plate, and a second compensation pattern extending in the first direction such that it does not overlap with the second plate. The second sub-pixel also includes a second storage capacitor, which comprises a third plate and a fourth plate. The third plate includes a third compensation pattern extending in a direction opposite to the first direction so as not to overlap with the fourth plate, and a fourth compensation pattern extending in the first direction so as not to overlap with the fourth plate.

13. The display device according to claim 12, wherein, The shapes of the first storage capacitor and the second storage capacitor are symmetrical about each other with respect to the boundary line between the first sub-pixel and the second sub-pixel.

14. The display device according to claim 12, wherein, The width of the first compensation pattern is the same as the width of the second compensation pattern, and the width of the third compensation pattern is the same as the width of the fourth compensation pattern.

15. The display device according to claim 12, wherein, When the entire first auxiliary pattern overlaps with the first scan line, the area of ​​the first compensation pattern is the same as the area of ​​the fourth compensation pattern, the area of ​​the second compensation pattern is the same as the area of ​​the third compensation pattern, and the first storage capacitor and the second storage capacitor have the same capacitance.

16. The display device according to claim 12, wherein, When a portion of the first auxiliary pattern does not overlap with the first scan line, the area of ​​the first compensation pattern is larger than the area of ​​the fourth compensation pattern, the area of ​​the second compensation pattern is smaller than the area of ​​the third compensation pattern, and the first storage capacitor and the second storage capacitor have the same capacitance.

17. The display device according to claim 12, wherein, When a portion of the first auxiliary pattern does not overlap with the first scan line, the area of ​​the first compensation pattern is smaller than the area of ​​the fourth compensation pattern, the area of ​​the second compensation pattern is larger than the area of ​​the third compensation pattern, and the first storage capacitor and the second storage capacitor have the same capacitance.

18. A display device, comprising: substrate; A first scan line is disposed on the substrate and extends through a first sub-pixel among a plurality of sub-pixels; A first auxiliary pattern is disposed in the region of the first sub-pixel and is electrically connected to the first scan line through one or more first contact holes; as well as An interlayer insulating film, wherein the interlayer insulating film is located between the first scan line and the first auxiliary pattern and has the one or more first contact holes. The first scan line protrudes symmetrically about the longitudinal axis in the vertical direction, and the first auxiliary pattern protrudes symmetrically about the longitudinal axis in the vertical direction. The line region including the portion protruding from the first scan line along the vertical direction and the line region including the portion protruding from the first auxiliary pattern along the vertical direction are connected through the one or more first contact holes.

19. The display device according to claim 18, wherein, A portion of the line region including the portion protruding from the first scan line along the vertical direction does not overlap with the line region including the portion protruding from the first auxiliary pattern along the vertical direction.

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