Semiconductor device

Abstract

A power semiconductor device is described herein having a semiconductor substrate including an active region and an edge termination region surrounding the active region, an edge termination structure located in the edge termination region of the semiconductor substrate, and a plurality of oxide segments located on an upper surface of the edge termination region of the semiconductor substrate, wherein the plurality of oxide segments are laterally spaced apart from one another. The power semiconductor device further includes a charge dissipation layer located on the upper surface of the edge termination region of the semiconductor substrate and on the plurality of oxide segments such that the charge dissipation layer is in contact with the upper surface of the semiconductor substrate only at a plurality of interface regions, wherein the interface regions include regions of the semiconductor substrate that are laterally between adjacent oxide segments.

Description

Technical Field

[0001] This disclosure relates to a power semiconductor device, and more particularly, but not exclusively, to a high-voltage edge termination region of a power semiconductor device. Background Technology

[0002] High-voltage termination structures in power devices are unstable under high-temperature reverse bias (HTRB). Therefore, devices with high-voltage JTE / VLD termination structures incorporate a voltage-stabilizing layer in contact with the silicon substrate to utilize breakdown voltage capability.

[0003] Existing devices use undoped polysilicon or semi-insulating polysilicon (SIPOS) layers as charge dissipation layers in contact with the terminal structure to stabilize voltage. Undoped polysilicon has a high density of stacking faults, which lead to high leakage currents at high temperatures. SIPOS is typically used because it offers improved surface voltage stability and leakage current compared to undoped polysilicon; however, existing devices using SIPOS still exhibit high leakage currents when operating at high temperatures due to discontinuities and stacking faults (high surface state charge density (Qss)) at the interface between the silicon substrate and the SIPOS layer. These high thermal leakage currents cause instability during HTRB and thermal runaway.

[0004] Figure 1 An edge termination region of a power semiconductor device according to the prior art, such as that shown in US8476691, is illustrated. The edge termination region includes several p-type regions. An undoped polysilicon layer or SIPOS layer is present on the edge termination region, on a tunnel oxide layer. The tunnel oxide layer passivates the interface between the undoped polysilicon or SIPOS layer and the underlying silicon substrate. The tunnel oxide layer is thin enough that hot carriers at the interface between the underlying silicon surface and the tunnel oxide layer can pass through the tunnel oxide layer into the charge dissipation layer.

[0005] In their article "Highly Reliable High Voltage Transistors by Use of the SIPOS Process," published in the December 1975 issue of IEDM Technical Digest in Washington, Matsushita et al. reported that increasing the oxygen concentration in SIPOS could reduce leakage current; however, if the SIPOS layer became too resistive due to excessive oxygen doping, the breakdown voltage stability would decrease.

[0006] Other conventional devices are found in US9171917, US2015 / 0349144, US6215168, US5093693, CN102263124, and EP0693772. SIPOS is described by Aoki et al. in "Oxygen-doped Polycrystalline Silicon Films Applied to Surface Passivation," published in J. Electrochem. Soc. Technical Digest in March 1975, on pages 167-170.

[0007] The purpose of this disclosure is to provide a power semiconductor device with an edge termination region that has reduced leakage current while maintaining breakdown voltage stability. Summary of the Invention

[0008] The aspects and preferred features are set forth in the appended claims.

[0009] According to a first aspect of this disclosure, a power semiconductor device is provided, comprising: a semiconductor substrate including a first region of a first conductivity type, the semiconductor substrate including an active region and an edge termination region surrounding the active region, wherein the edge termination region is laterally located between the active region and a side surface of the semiconductor device;

[0010] The first region of the second conductivity type is located in the active region and is above the first region of the first conductivity type;

[0011] An edge termination structure includes one or more regions of a second conductivity type located in the edge termination region of a semiconductor substrate and extending to the upper surface of the semiconductor substrate;

[0012] Multiple oxide segments are located on the upper surface of the edge termination region of the semiconductor substrate, wherein the multiple oxide segments are laterally spaced from each other; and

[0013] A charge dissipation layer is located on the upper surface of the edge terminal region of the semiconductor substrate and on a plurality of oxide segments, such that the charge dissipation layer contacts the upper surface of the semiconductor substrate only in a plurality of interface regions, wherein the interface regions include the regions of the semiconductor substrate located laterally between adjacent oxide segments.

[0014] The active region can be referred to as a cell region or the area of ​​an active device. “Contact” can refer to direct, physical contact; however, it can also refer to electrical contact that allows charge carriers to transfer from one region to another.

[0015] Because the charge dissipation layer only contacts the semiconductor substrate in multiple interface regions, the interface area between the charge dissipation layer and the semiconductor substrate is reduced compared to conventional devices. This reduces current leakage.

[0016] Power semiconductor devices can be diodes, IGBTs, RCIGBTs, MOSFETs, or thyristors.

[0017] The thickness of the oxide segment can range from 1 μm to 4 μm. This prevents charge carriers from being transferred from the semiconductor substrate through the oxide segment into the charge dissipation layer.

[0018] The oxide segment may include an oxide layer having small openings corresponding to the interface region.

[0019] The charge dissipation layer may include undoped polysilicon.

[0020] Alternatively, the charge dissipation layer may comprise semi-insulating polycrystalline silicon (SIPOS). Compared to undoped polycrystalline silicon, SIPOS offers improved surface voltage stability and leakage current.

[0021] The SIPOS charge dissipation layer may include 10%–25% oxygen by weight. A low percentage of oxygen can be used to achieve the desired SIPOS resistivity without affecting breakdown voltage stability.

[0022] The charge dissipation layer can have arrive The thickness of the charge dissipation (SIPOS) layer is crucial. This range of thickness provides a suitable level of resistance. A thicker charge dissipation layer reduces resistance, while a thinner layer increases resistance, thus affecting device performance.

[0023] Less than 30% of the surface area of ​​the lower surface of the charge dissipation layer can contact the semiconductor substrate. Less than 20% of the surface area of ​​the lower surface of the charge dissipation layer can contact the semiconductor substrate. 8% to 20% of the surface area of ​​the lower surface of the charge dissipation layer can contact the semiconductor substrate.

[0024] Each oxide region can form a toroidal structure surrounding the active region. The toroidal structure can be of any shape, such as circular, square, or rounded square. The toroidal structure of each oxide segment can be a continuous shape surrounding the active region. Multiple oxide regions can be concentric with each other.

[0025] The device may further include a channel stop structure located laterally between the edge termination structure and the side surface of the semiconductor device. The channel stop structure may extend to the side surface of the semiconductor device. The channel stop structure may include a second region of a first conductivity type, and the doping concentration of the second region of the first conductivity type is higher than that of the first region of the first conductivity type.

[0026] The edge termination structure may include a junction termination extension (JTE) or variable lateral doping (VLD) implantation layer formed by one or more second regions of a second conductivity type, wherein the second region of the second conductivity type may contact a first region of the second conductivity type.

[0027] JTE may include multiple second regions of a second conductivity type, wherein each second region of a second conductivity type has a different doping concentration and junction depth.

[0028] VLDs may include a second region of a second conductivity type, wherein the doping concentration of the second region of the second conductivity type is variable throughout the second region of the second conductivity type. Variations in doping concentration may be formed by multiple implant window openings, wherein the multiple implant window openings are separated by varying distances. VLDs consume less area and are therefore more area-efficient than JTEs.

[0029] The doping concentration of JTE or VLD can be 1x10. 15 cm -3 Up to 1x10 16 cm -3 This is likely due to the formation of boron implants and thermal annealing.

[0030] Alternatively, the edge termination structure may include a plurality of second regions of a second conductivity type, wherein the second regions of the second conductivity type may be laterally spaced apart from each other. The edge termination structure further includes a plurality of third regions of a second conductivity type with a higher doping concentration than the plurality of second regions of the second conductivity type, wherein each third region of the second conductivity type is in contact with a corresponding second region of the second conductivity type.

[0031] The second region of the second conductivity type is positioned such that each second region of the second conductivity type is at least partially located below the oxide segment and below a portion of the charge dissipation layer between adjacent oxide segments. The oxide segments may be laterally located between the second region of the corresponding second conductivity type and the side surface of the device. In other words, the oxide segments are offset from their respective second regions, further away from the center of the semiconductor device. This allows the oxide segments to be positioned such that the interface region is offset from the corresponding second region towards the center of the semiconductor device, thus placing the interface region only in the region of the electric field peak. This means that hot carriers can be dissipated through the charge dissipation layer, ensuring blocking stability under high voltage conditions, such as blocking stability under HTRB.

[0032] The third region of each second conductivity type is located in the interface region. The third region of each second conductivity type can extend into the edge terminal region between two adjacent oxide regions.

[0033] The doping concentration of the second region of the second conductivity type is 2x10. 15 cm -3 Up to 1x10 16 cm -3 The doping concentration of the third region of the second conductivity type is 1x10⁻⁶. 18 cm -3 Up to 1x10 19 cm -3 .

[0034] The second region of the second conductivity type may include a concentric ring structure surrounding the active region.

[0035] The third region for each second conductivity type may be laterally located between the second region of the corresponding second conductivity type and the active region of the device. In other words, the third region is offset from its corresponding second region and toward the center of the semiconductor device. This allows the third region to be located at the location of the electric field peak. This prevents the loss edge from reaching the interface region during blocking and from presenting surface conditions and inhomogeneities that affect termination stability and HTRB performance.

[0036] The device may further include a nitride layer located above the charge dissipation layer.

[0037] The device may further include a metal layer located between the semiconductor substrate and the charge dissipation layer. This allows the charge dissipation layer to be in electrical contact with the semiconductor substrate without direct physical contact. Therefore, this prevents the loss edge from making physical contact with the charge dissipation layer during high-voltage blocking.

[0038] According to another aspect of this disclosure, a method for manufacturing a power semiconductor device is provided, the method comprising:

[0039] A semiconductor substrate is formed, comprising a first region of a first conductivity type, the semiconductor substrate comprising an active region and an edge termination region surrounding the active region, wherein the edge termination region is laterally located between the active region and a side surface of the semiconductor device.

[0040] A first region of the second conductivity type is formed, which is located in the active region and above the first region of the first conductivity type;

[0041] An edge termination structure is formed, which includes one or more regions of a second conductivity type located at the edge termination region of the semiconductor substrate and extending to the upper surface of the semiconductor substrate;

[0042] Multiple oxide segments are formed on the upper surface of the edge termination region of the semiconductor substrate, wherein the multiple oxide segments are laterally spaced from each other; and

[0043] A charge dissipation layer is formed on the upper surface of the edge terminal region of the semiconductor substrate and on a plurality of oxide segments, such that the charge dissipation layer contacts the upper surface of the semiconductor substrate only in a plurality of interface regions, wherein the interface regions include the regions of the semiconductor substrate located laterally between adjacent oxide segments. Attached Figure Description

[0044] Some preferred embodiments of this disclosure will now be described by way of example only and with reference to the accompanying drawings, wherein:

[0045] Figure 1 The edge terminal region of a power semiconductor device according to the prior art is shown;

[0046] Figure 2 A cross-section of the edge terminal region of a power semiconductor device according to an embodiment of the present disclosure is shown;

[0047] Figure 3 It shows Figure 2 A top view of the device;

[0048] Figure 4 The relationship between leakage current and the area of ​​the terminal silicon and SIPOS interface is shown.

[0049] Figure 5 A cross-section of an alternative edge termination region of a power semiconductor device according to another embodiment of the present disclosure is shown; and

[0050] Figure 6 A cross-section of an alternative edge terminal region of a power semiconductor device according to another embodiment of the present disclosure is shown. Detailed Implementation

[0051] Figure 2 A cross-section of the edge terminal region 100 of a power semiconductor device according to an embodiment of the present disclosure is shown. Figure 2 It shows the way Figure 3 The cross-section of the cut line AA is shown in the diagram. The device includes a semiconductor substrate, which in this example is formed of silicon, although other semiconductor materials can be used. The semiconductor substrate includes two regions: an active region (not shown) for current conduction, and an edge termination region. Figure 3 As shown, the active region is located at the center of the semiconductor device, while the edge terminal region surrounds the active region and is located between the active region and the side surface of the semiconductor device.

[0052] In this embodiment, the semiconductor substrate includes an n-type voltage sustaining region or an n-type substrate (or drift region) 108 on the cathode 102. An N-type cathode layer 106 is located between the cathode 102 and the n-type substrate region 108. A p-type body region 112 is provided above the n-type substrate region 108 and at the outer edge of the active region (in the case of a power MOSFET or IGBT). An anode 104 is located above the p-type body region 112, and the anode metal 104 is in contact with the SIPOS layer.

[0053] The p-type body region 112 is surrounded by an edge termination structure (also referred to as a junction termination structure), which in this embodiment includes a p-type JTE / VLD implant layer 114. Those skilled in the art will understand that the types of power devices and junction termination structures are exemplary and not limited to those shown.

[0054] The channel stop region 110 is located on the side surface of the semiconductor device, on the side opposite to the active region in the edge termination region. The channel stop region 110 includes n-type diffusion with a higher doping concentration than the drift region 108. The channel stop region 110 prevents the formation of a channel at the edge of the device.

[0055] Multiple oxide segments 116 are located on and in contact with the top surface of the edge termination region of the semiconductor substrate. It is understood that while oxides are used in this embodiment, other insulating materials may also be used. For example, the oxide segments 116 may comprise a stack of layers with an oxide layer as the underlying layer. The multiple oxide segments 116 are laterally spaced from each other between the active region and the side surface of the semiconductor device. The oxide segment 116 closest to the active region contacts the p-type body region 112 and the anode 104, while the oxide segment closest to the side surface of the semiconductor device contacts the channel stop layer 110.

[0056] Multiple oxide segments 116 are separated, such that there are gaps or spaces between adjacent oxide segments. A charge dissipation layer 118 is located on the semiconductor substrate and the oxide segments 116. In this example, the charge dissipation layer 118 is a SIPOS layer, although the charge dissipation layer 118 can also be an undoped polysilicon layer. The SIPOS layer can include a three-layer structure comprising a thick layer of oxygen-doped polysilicon. Multiple interface regions or regions 124 of the charge dissipation layer 118 corresponding to the gaps between adjacent oxide segments 118 contact the top surface of the edge termination regions of the semiconductor substrate.

[0057] The oxide segment 116 has a thickness of 1 μm to 4 μm, which is sufficient to prevent charge carriers from the semiconductor substrate from reaching the SIPOS layer 118 through the oxide segment 116. This reduces the interface area between the silicon substrate and the SIPOS layer 118. Devices with this configuration, i.e., devices with a thick oxide segment 116 between SIPOS layers, can be used to reduce the proportion of the lower surface of the SIPOS layer in contact with the top surface of the silicon to below 20%.

[0058] A metal layer (not shown) may be provided between the substrate and the SIPOS layer 118. However, in this case, the substrate and SIPOS 118 will still be in electrical contact because the conductivity of the metal layer will allow charge carriers to transfer from the semiconductor substrate to the SIPOS layer 118. The metal layer can prevent loss edges from contacting the SIPOS layer during high-voltage blocking because there is no direct physical contact between the silicon substrate and the SIPOS layer, and there is no direct physical interface between the silicon substrate and the SIPOS layer.

[0059] A nitride layer 120 is situated above the SIPOS layer 118. The nitride layer prevents moisture from entering the termination region, which can disrupt the stability of the electric field distribution and reduce the breakdown voltage. Other materials with similar properties to nitrides (e.g., non-porous materials or materials impermeable to moisture) can be used instead of nitrides. Other passivation layers 122, such as oxides, nitrides, or polyimides, are situated above the nitride layer 120. The thickness of the nitride layer 120 is [missing information]. to The thickness of SIPOS layer 118 is to Between. The oxygen doping content of SIPOS layer 118 is 10% by weight.

[0060] Figure 3 yes Figure 2 A top view of the device shows the active region 130 and the edge terminal region 100 surrounding the active region 130. It is understood that... Figure 2 The device is a diode, however, the semiconductor device can also be an IGBT, in which case there will be a gate pad area.

[0061] from Figure 3As can be seen, each oxide segment 116 can form a ring around the active region 130, resulting in a series of concentric rings formed by multiple oxide segments 116 around the active region 130. The ring shape of the oxide segment 116 can be circular, elliptical, rectangular, square, rounded square or rounded rectangle, or any other shape surrounding the active region 130. The ring shape of the oxide segment 116 can have an inner periphery and an outer periphery, both of which are similar in shape to the active region 130. The space between the oxide segment 116 and each corresponding interface region 124 also has an inner periphery and an outer periphery with a similar shape to the active region 130.

[0062] Figure 4 The relationship between leakage current and terminal silicon / SIPOS interface area at 150°C is shown for conventional device 410 and three devices 420a, 420b, and 420c according to embodiments of the present disclosure. Conventional device 410 has a 100% terminal silicon / SIPOS interface area, meaning the lower surface of the SIPOS layer is 100% in contact with the top surface of the silicon substrate. Compared to conventional device 410, the devices 420a, 420b, and 420c disclosed herein have a reduced terminal Si / SIPOS interface area. In this example, devices 420a, 420b, and 420c have <20% contact between the lower surface of the SIPOS layer and the top surface of the silicon substrate. This indicates that at 150°C, the leakage current decreases with decreasing terminal Si / SIPOS interface area, by up to 40%.

[0063] Figure 5 A cross-section of an alternative edge termination region of a power semiconductor device according to another embodiment of the present disclosure is shown. In this embodiment, the edge termination structure includes a plurality of p-rings 142 located on the top surface of a semiconductor substrate. The top surface of each p-ring 142 contacts an oxide segment 116 and an interface region 124. In this example, the number of p-rings 142 corresponds to the number of oxide segments 116; however, the number of p-rings 142 may differ from the number of oxide segments 116.

[0064] In this cross-sectional view, the p-ring 142 appears as a p-type diffuser; however, in the top view, the p-ring 142 is a ring-shaped structure surrounding the active region of the device. Multiple p-ring structures 142 form a series of concentric rings around the active region. The ring shape of the p-ring 142 can be circular, elliptical, rectangular, square, rounded square, or rounded rectangle, or any other shape surrounding the active region. The ring shape of the p-ring 142 can have an inner circumference and an outer circumference, both of which are similar in shape to the active region.

[0065] Each p-type ring 142 is connected to a p+ implant 140, which is also located on the top surface of the semiconductor substrate. Compared to the p+ implant 140 (<1 μm), the p-type rings 142 extend to a greater depth (<20 μm) into the semiconductor substrate. For this reason, the p-type rings 142 are referred to as deep p-type rings, and the p+ implant 140 as shallow p+ implants. The p-type rings 142 are lightly doped and have a doping density of approximately 2 x 10⁻⁶. 15 cm -3 Up to 1x10 16 cm -3 The surface doping concentration is higher for p+ implants 140, approximately 1 x 10⁻⁶. 18 cm -3 Up to 1x10 19 cm -3 .

[0066] The p+ implant 140 is located in the peak electric field region of the semiconductor substrate; these regions are offset from the inner edge of the p-ring 142. In other words, the p+ implant 140 is located on the side of the corresponding p-ring 142 closest to the active region of the device (shown as the left-hand side in this figure). The offset of the p+ implant 140 relative to the p-ring 142 prevents the loss edge during blocking from reaching the interface region 124, thus preventing surface conditions and non-uniformity at the interface 124 from affecting the stability of the termination region and the HTRB performance. The peak electric field occurs at the inner edge of the p-ring 142; therefore, it is advantageous for the p+ implant 140 to be located above this peak electric field region for effectiveness. This offset is most advantageous when the p-ring 142 is lightly doped and should prevent the loss edge during high-voltage blocking from contacting the Si / SIPOS interface 124.

[0067] Since the area of ​​the Si / SIPOS interface 124 is to be reduced to decrease leakage current, the interface region 124 is located only on the inner edge of the p-type ring 142 where the electric field peak occurs (shown as the left-hand side in this figure). Therefore, despite the reduced area of ​​the interface 124, hot carriers can still be easily dissipated through the SIPOS layer 118. This ensures blocking stability under high-voltage conditions, such as during HTRB.

[0068] Figure 6A cross-section of an alternative edge termination region of a power semiconductor device according to another embodiment of the present disclosure is shown. In this embodiment, a metal layer 126 is located between a semiconductor substrate and a charge dissipation layer 118. In this example, the metal layer comprises a metal structure laterally located between adjacent oxide segments 116. In this example, the SIPOS layer 118 comprises segments separated by the metal layer 126. The SIPOS layer 118 is electrically connected to the silicon substrate through sidewalls that contact the metal layer 126. This allows the charge dissipation layer to not have direct physical contact with the semiconductor substrate, but still remain electrically contacted with the semiconductor substrate. Therefore, this prevents the loss edge from physically contacting the charge dissipation layer during high-voltage blocking. It is understood that the metal layer is not limited to devices having the termination structure shown in this figure, and the metal layer can be used in alternative embodiments with different edge termination structures.

[0069] List of reference numerals

[0070] 100 edge terminal areas

[0071] 102 Cathode Metal

[0072] 104 Anode Metal

[0073] 106 Cathode N+ layer

[0074] 108 Drift Area

[0075] 110 Ditch Stopping Area

[0076] 112 P-type well area

[0077] 114 JTE / VLD implant area

[0078] 116 Oxide Section

[0079] 118SIPOS layer

[0080] 120 Nitride Layer

[0081] 122 Passivation layer

[0082] 124 Silicon / SIPOS Interface Area

[0083] 126 Metal Layer

[0084] 130 active area

[0085] 140 p+ implant

[0086] 142 Slightly doped p-type region

[0087] 410 Traditional device

[0088] 420 Semiconductor Device

[0089] Those skilled in the art will understand that positional terms such as “above,” “overlapping,” “below,” and “lateral” in the foregoing description and appended claims are used with reference to conceptual illustrations of the device, such as those showing standard cross-sectional views and those illustrated in the appended figures. These terms are used for ease of reference and are not intended to be restrictive. Therefore, these terms should be understood to refer to the device in the orientation shown in the figures.

[0090] It is understood that all the doping polarities mentioned above can be reversed, and the resulting device still conforms to the embodiments of the present invention.

[0091] Although this disclosure has been described with reference to the preferred embodiments above, it should be understood that these embodiments are merely illustrative and the claims are not limited to these embodiments. Those skilled in the art will be able to make modifications and substitutions based on the disclosure, and such modifications and substitutions are considered to fall within the scope of the appended claims. Each feature disclosed or described in this specification may be incorporated into the disclosure, either alone or in any suitable combination with any other feature disclosed or described herein.

Claims

1. A power semiconductor device, comprising: A semiconductor substrate, the semiconductor substrate including a first region of a first conductivity type, the semiconductor substrate including an active region and an edge termination region surrounding the active region, wherein the edge termination region is laterally located between the active region and a side surface of the semiconductor device; A first region of a second conductivity type, wherein the first region of the second conductivity type is located in the active region and is above the first region of the first conductivity type; An edge termination structure, the edge termination structure including one or more regions of a second conductivity type located in the edge termination region of the semiconductor substrate and extending to the upper surface of the semiconductor substrate; A plurality of oxide segments, the plurality of oxide segments being located above the upper surface of the edge termination region of the semiconductor substrate, wherein the plurality of oxide segments are laterally spaced from each other; and A charge dissipation layer is located on the upper surface of the edge termination region of the semiconductor substrate and over the plurality of oxide segments, such that the charge dissipation layer contacts the upper surface of the semiconductor substrate only in a plurality of interface regions, wherein the interface regions include areas of the semiconductor substrate located laterally between adjacent oxide segments. The edge terminal structure further includes: A plurality of second regions of the second conductivity type, wherein the second regions of the second conductivity type are spaced apart from each other laterally; and The plurality of third regions of the second conductivity type have a higher doping concentration than the plurality of second regions of the second conductivity type, wherein each third region of the second conductivity type is in contact with a corresponding second region of the second conductivity type. The second region of the second conductivity type is positioned such that each second region of the second conductivity type is at least partially located below only one oxide segment and below a portion of the charge dissipation layer between adjacent oxide segments, such that each oxide segment is laterally located between the side surface of the semiconductor device and the corresponding second region of the second conductivity type. In this context, each third region of the second conductivity type is located in the interface region.

2. The power semiconductor device according to claim 1, wherein, The thickness of the oxide segment is 1 μm to 4 μm.

3. The power semiconductor device according to claim 1 or 2, wherein, The charge dissipation layer comprises undoped polycrystalline silicon.

4. The power semiconductor device according to claim 1 or 2, wherein, The charge dissipation layer comprises semi-insulating polycrystalline silicon, i.e., SIPOS.

5. The power semiconductor device according to claim 4, wherein, The SIPOS charge dissipation layer comprises 10%–25% oxygen by weight.

6. The power semiconductor device according to claim 1, wherein, The thickness of the charge dissipation layer is 4 kÅ to 6 kÅ.

7. The power semiconductor device according to claim 1, wherein, Less than 20% of the surface area of ​​the lower surface of the charge dissipation region is in contact with the semiconductor substrate.

8. The power semiconductor device according to claim 1, wherein, The oxide region forms a ring structure around the active region.

9. The power semiconductor device according to claim 1, wherein, The device further includes a channel stop structure; the channel stop structure is laterally located between the edge termination structure and the side surface of the semiconductor device, and extends to the side surface of the semiconductor device. The channel stop structure includes a second region of a first conductivity type, wherein the doping concentration of the second region of the first conductivity type is higher than that of the first region of the first conductivity type.

10. The power semiconductor device according to claim 1, wherein, The doping concentration of the second region of the second conductivity type is 2x10. 15 cm -3 Up to 1x10 16 cm -3 ,as well as The doping concentration of the third region of the second conductivity type is 1x10. 18 cm -3 Up to 1x10 19 cm -3 .

11. The power semiconductor device according to claim 1 or 10, wherein, The second region of the second conductivity type includes a concentric ring structure surrounding the active region.

12. The power semiconductor device according to claim 11, wherein, The third region of each second conductivity type is located laterally between the second region of the corresponding second conductivity type and the active region of the device.

13. The power semiconductor device according to claim 1, wherein, The device further includes a nitride layer located above the charge dissipation layer.

14. The power semiconductor device of claim 1, further comprising a metal layer located between the semiconductor substrate and the charge dissipation layer.

15. A method for manufacturing a power semiconductor device, the method comprising: A semiconductor substrate is formed, the semiconductor substrate including a first region of a first conductivity type, the semiconductor substrate including an active region and an edge termination region surrounding the active region, wherein the edge termination region is laterally located between the active region and a side surface of the semiconductor device; A first region of a second conductivity type is formed, the first region of the second conductivity type being located in the active region and above the first region of the first conductivity type; An edge termination structure is formed, the edge termination structure including one or more regions of a second conductivity type located in the edge termination region of the semiconductor substrate and extending to the upper surface of the semiconductor substrate; A plurality of oxide segments are formed, the plurality of oxide segments being located above the upper surface of the edge termination region of the semiconductor substrate, wherein the plurality of oxide segments are laterally spaced from each other; and A charge dissipation layer is formed on the upper surface of the edge termination region of the semiconductor substrate and over the plurality of oxide segments, such that the charge dissipation layer contacts the upper surface of the semiconductor substrate only in a plurality of interface regions, wherein the interface regions include areas of the semiconductor substrate located laterally between adjacent oxide segments. The edge terminal structure further includes: A plurality of second regions of the second conductivity type, wherein the second regions of the second conductivity type are spaced apart from each other laterally; and The plurality of third regions of the second conductivity type have a higher doping concentration than the plurality of second regions of the second conductivity type, wherein each third region of the second conductivity type is in contact with a corresponding second region of the second conductivity type. The second region of the second conductivity type is positioned such that each second region of the second conductivity type is at least partially located below only one oxide segment and below a portion of the charge dissipation layer between adjacent oxide segments, such that each oxide segment is laterally located between the side surface of the semiconductor device and the corresponding second region of the second conductivity type. In this context, each third region of the second conductivity type is located in the interface region.

Images