Bidirectional thyristor

Abstract

A bidirectional thyristor capable of improving (dv / dt)c tolerance is provided. The bidirectional thyristor of the present application has a first conductive type first semiconductor layer and a first conductive type second semiconductor layer (11, 21), a second conductive type first semiconductor layer and a second conductive type second semiconductor layer (13, 12), a plurality of carrier release portions (11a) disposed in a second conductive type third semiconductor layer, a second conductive type fourth semiconductor layer (15), a first electrode and a second electrode (31, 32), a gate electrode (16), and a passivation film (17), the plurality of carrier release portions (11a) form an opening in the second conductive type third semiconductor layer (14), the first conductive type first semiconductor layer (11) is positioned in the opening, the plurality of carrier release portions (11a) are disposed between a position at a predetermined distance from the gate electrode and an outer edge of the first electrode when viewed in plan view, the plurality of carrier release portions are disposed so as to be in contact with the outer edge of the first electrode, the outer edge of the first electrode at which two or more of the plurality of carrier release portions are in contact is in contact with the passivation film, and an area of a triangle (33) when viewed in plan view is smaller than an area of a quadrangle (22).

Description

Technical Field

[0001] This invention relates to bidirectional thyristors. Background Technology

[0002] In existing bidirectional thyristors, current flows from the first electrode (T1) to the second electrode (T2) for thyristor operation. Even immediately after the current flow ends, charge carriers remain and diffuse laterally. Therefore, if a bias voltage is applied to the second electrode (T2), these residual charge carriers exhibit the same effect as the gate trigger current, even without a bias voltage applied to the gate electrode. This can sometimes lead to false triggering, where the conduction operation is transferred. The ease of this false triggering is represented by the (dv / dt)c withstand capability, requiring an increase in the (dv / dt)c withstand capability while ensuring the thyristor's characteristics. It should be noted that existing bidirectional thyristors are described, for example, in Patent Document 1.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2010-245377 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] The purpose of various embodiments of the present invention is to provide a bidirectional thyristor capable of improving (dv / dt)c tolerance.

[0008] means for solving problems

[0009] The various aspects of the present invention will be described below.

[0010] [1]. A bidirectional thyristor, characterized in that the bidirectional thyristor has:

[0011] First conductivity type, first semiconductor layer;

[0012] A second conductivity type first semiconductor layer is disposed on the back side of the first conductivity type first semiconductor layer;

[0013] A first conductivity type second semiconductor layer is disposed on the back side of the second conductivity type first semiconductor layer;

[0014] A second conductivity type second semiconductor layer is disposed on the back side of the first conductivity type second semiconductor layer;

[0015] A second conductivity type third semiconductor layer is disposed on the surface side of the first conductivity type first semiconductor layer;

[0016] Multiple carrier release sections are disposed on the second conductivity type third semiconductor layer;

[0017] A second conductivity type fourth semiconductor layer is disposed on the surface side of the first conductivity type first semiconductor layer;

[0018] The first electrode is in contact with the second conductivity type third semiconductor layer, the plurality of carrier release sections, and the first conductivity type first semiconductor layer;

[0019] The second electrode is in contact with the second conductivity type second semiconductor layer and the first conductivity type second semiconductor layer;

[0020] The gate electrode is in contact with the second conductivity type fourth semiconductor layer and the first conductivity type first semiconductor layer; and

[0021] A passivation film is disposed on the boundary between the first conductive first semiconductor layer and the second conductive first semiconductor layer on the surface side of the first conductive first semiconductor layer, and on the boundary between the second conductive first semiconductor layer and the first conductive second semiconductor layer on the surface side of the first conductive first semiconductor layer.

[0022] Each of the plurality of carrier release sections is configured to form an opening in the second conductivity type third semiconductor layer, with the first conductivity type first semiconductor layer located within the opening.

[0023] The plurality of carrier release sections are arranged, when viewed from above, between a predetermined distance from the gate electrode and the outer edge of the first electrode.

[0024] Two or more of the multiple carrier release sections are arranged in a manner that connects to the outer edge of the first electrode.

[0025] The outer edge of the first electrode, where two or more of the multiple carrier release sections are connected, is in contact with the passivation film.

[0026] When viewed from above, the area of ​​the triangle formed by the adjacent carrier release portion located at the outer edge of the first electrode and the carrier release portion located at the position with the shortest distance from the straight line connecting the adjacent carrier release portions is smaller than the area of ​​the quadrilateral formed by the carrier release portions not located at the outer edge of the first electrode.

[0027] [2]. In the above [1],

[0028] Two or more carrier release sections arranged in a manner that connects to the outer edge of the first electrode have a notch shape, a polygonal shape, or an elliptical shape when viewed from above.

[0029] [3]. In [1] or [2] above,

[0030] When viewed from above, the density of the carrier release portion near the outer edge of the first electrode is higher than the density of the carrier release portion in the region outside the outer edge of the first electrode.

[0031] Invention Effects

[0032] According to the bidirectional thyristor of the present invention [1], two or more of the multiple carrier release sections are arranged in a manner that is in contact with the outer edge of the first electrode. Even if a portion of the multiple carrier release sections is arranged at the outer edge of the first electrode, the reduction in the area of ​​the second conductivity type third semiconductor layer in contact with the first electrode is very small, so it has almost no effect on the VT characteristics and the gate electrode characteristics.

[0033] By applying a negative voltage to the second electrode and the gate electrode at the first electrode ground (GND), a trigger current flows through the gate electrode. This triggers the thyristor, and the current flows in the order of the first electrode, the first semiconductor layer of the first conductivity type, the first semiconductor layer of the second conductivity type, the second semiconductor layer of the first conductivity type, the second semiconductor layer of the second conductivity type, and the second electrode. During this time, charge carriers 23 diffuse laterally, and even after the current flows through the thyristor, some charge carriers remain. Next, without applying a bias voltage to the gate electrode but with a positive voltage applied to the second electrode, these remaining charge carriers are treated as invalid current via multiple charge carrier release sections without passing through the third semiconductor layer of the second conductivity type, thus preventing false triggering. Furthermore, by making the area of ​​the triangle formed by the adjacent charge carrier release section located at the outer edge of the first electrode and the charge carrier release section located at the shortest distance from the line connecting the adjacent charge carrier release sections smaller than the area of ​​the quadrilateral 22 formed by the charge carrier release sections not located at the outer edge of the first electrode when viewed from above smaller than the area of ​​the quadrilateral 22 formed by the charge carrier release sections not located at the outer edge of the first electrode, the remaining charge carriers can be treated as invalid current more efficiently. Therefore, it can more effectively prevent false triggering and improve (dv / dt)c tolerance.

[0034] According to the bidirectional thyristor of the present invention [3], when viewed from above, the density of the carrier release portion near the outer edge of the first electrode is higher than the density of the carrier release portion in the region outside the outer edge of the first electrode. As a result, residual carriers can be processed as ineffective current more efficiently through the carrier release portion disposed near the outer edge of the first electrode without passing through the second conductivity type third semiconductor layer. Attached Figure Description

[0035] Figure 1 This is a top view illustrating a bidirectional thyristor according to one embodiment of the present invention.

[0036] Figure 2It is along Figure 1 The cross-sectional view of line A-A' shown.

[0037] Figure 3 Is with Figure 2 The corresponding accompanying drawing is a cross-sectional view used to illustrate the effect of a bidirectional thyristor involved in one aspect of the present invention.

[0038] Figure 4 Is with Figure 2 The corresponding accompanying drawing is a cross-sectional view used to illustrate the effect of a bidirectional thyristor involved in one aspect of the present invention.

[0039] Figure 5 It means from Figure 2 The cross-sectional view of a comparative example of a bidirectional thyristor according to one aspect of the present invention, with the carrier release section 11a removed, is shown.

[0040] Figure 6 Is with Figure 2 The corresponding accompanying drawings are comparative examples of the present invention.

[0041] Figure 7 It means Figure 1 The top view of the modified example 1 of the bidirectional thyristor shown.

[0042] Figure 8 It means Figure 1 The top view of the modified example 2 of the bidirectional thyristor shown.

[0043] Figure 9 It means preparation Figure 2 The bidirectional thyristor sample of the present invention shown is... Figure 5 The comparative example sample is shown in the figure, which shows the results of measuring the relationship between VT (conduction voltage) and (dv / dt)c withstand capacity.

[0044] Figure 10 It means preparation Figure 2 The bidirectional thyristor sample of the present invention shown is... Figure 5 The comparative example sample is shown in the figure, which shows the results of measuring the relationship between IGT (gate trigger current) and (dv / dt)c tolerance.

[0045] Figure 11 It means preparation Figure 2 The bidirectional thyristor sample of the present invention shown is... Figure 5 The comparative example sample is shown in the figure, which shows the results of measuring the relationship between VGT (gate trigger voltage) and (dv / dt)c tolerance. Detailed Implementation

[0046] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description, and those skilled in the art will readily understand that various changes can be made to its methods and details without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as limited to the description of the embodiments shown below.

[0047] The bidirectional thyristor described above [1] according to one aspect of the present invention is characterized in that the bidirectional thyristor has:

[0048] First conductivity type, first semiconductor layer;

[0049] A second conductivity type first semiconductor layer is disposed on the back side of the first conductivity type first semiconductor layer;

[0050] A first conductivity type second semiconductor layer is disposed on the back side of the second conductivity type first semiconductor layer;

[0051] A second conductivity type second semiconductor layer is disposed on the back side of the first conductivity type second semiconductor layer;

[0052] A second conductivity type third semiconductor layer is disposed on the surface side of the first conductivity type first semiconductor layer;

[0053] Multiple carrier release sections are disposed on the second conductivity type third semiconductor layer;

[0054] A second conductivity type fourth semiconductor layer is disposed on the surface side of the first conductivity type first semiconductor layer;

[0055] The first electrode is in contact with the second conductivity type third semiconductor layer, the plurality of carrier release sections, and the first conductivity type first semiconductor layer;

[0056] The second electrode is in contact with the second conductivity type second semiconductor layer and the first conductivity type second semiconductor layer;

[0057] The gate electrode is in contact with the second conductivity type fourth semiconductor layer and the first conductivity type first semiconductor layer; and

[0058] A passivation film is disposed on the boundary between the first conductive first semiconductor layer and the second conductive first semiconductor layer on the surface side of the first conductive first semiconductor layer, and on the boundary between the second conductive first semiconductor layer and the first conductive second semiconductor layer on the surface side of the first conductive first semiconductor layer.

[0059] Each of the plurality of carrier release sections is configured to form an opening in the second conductivity type third semiconductor layer, with the first conductivity type first semiconductor layer located within the opening.

[0060] The plurality of carrier release sections are arranged, when viewed from above, between a predetermined distance from the gate electrode and the outer edge of the first electrode.

[0061] Two or more of the multiple carrier release sections are arranged in a manner that connects to the outer edge of the first electrode.

[0062] The outer edge of the first electrode, where two or more of the multiple carrier release sections are connected, is in contact with the passivation film.

[0063] When viewed from above, the area of ​​the triangle formed by the adjacent carrier release portion located at the outer edge of the first electrode and the carrier release portion located at the position with the shortest distance from the straight line connecting the adjacent carrier release portions is smaller than the area of ​​the quadrilateral formed by the carrier release portions not located at the outer edge of the first electrode.

[0064] The following is a detailed explanation.

[0065] Figure 1 This is a top view illustrating a bidirectional thyristor according to one embodiment of the present invention. Figure 2 It is along Figure 1 The cross-sectional view of line A-A' shown. However, Figure 2 The cross-sectional view of the bidirectional thyristor shown is omitted. Figure 1 The diagram shows a portion of the bidirectional thyristor.

[0066] First conductivity type first semiconductor layer (P) + )11 was formed in Figure 2 The figure shown is P + The first conductivity type second semiconductor layer (P) of the type semiconductor substrate + )21 surface side (T1 electrode 31 side).

[0067] First conductivity type first semiconductor layer (P) + A second conductivity type first semiconductor layer (N) is disposed on the back side (T2 electrode 32 side) of 11. - )13 (refer to Figure 2 ).

[0068] Second conductivity type first semiconductor layer (N) - )13 peripheral ( Figure 2 The two ends shown extend to the first conductivity type first semiconductor layer (P). + Formed on the surface side of 11 (refer to) Figure 1 as well as Figure 2 In other words, such as Figure 2 As shown, the second conductivity type first semiconductor layer (N - )13 is surrounded by a first conductivity type first semiconductor layer (P) by a bottom portion 13a and a sidewall portion 13b. + It is formed in the manner of )11.

[0069] Second conductivity type first semiconductor layer (N) - A first conductivity type second semiconductor layer (P) is disposed on the back side (T2 electrode 32 side) of 13. + )twenty one.

[0070] First conductivity type second semiconductor layer (P + )21 has a second conductivity type second semiconductor layer (N) + )12, the second conductivity type second semiconductor layer (N + )12 is located in the first conductivity type second semiconductor layer (P + The back side of )21 (T2 electrode 32 side). That is, as Figure 2 As shown, in the first semiconductor layer (P) of the first conductivity type + A first conductivity type first semiconductor layer (P) is sequentially disposed on the surface of 11 in the direction of the back side (first direction). + 11. Second conductivity type first semiconductor layer (N - 13. First conductivity type second semiconductor layer (P + 21. Second conductivity type second semiconductor layer (N + )12, they become the first path for current to flow through the thyristor operation.

[0071] First conductivity type first semiconductor layer (P) + A second conductivity type third semiconductor layer (N) is disposed on the surface side (T1 electrode 31 side) of 11. + 14. That is, such as Figure 2 As shown, from the first conductivity type second semiconductor layer (P) + A first conductivity type second semiconductor layer (P) is sequentially disposed on the back side of 21 in the direction facing the surface (second direction). + 21. Second conductivity type first semiconductor layer (N) - 13. First conductivity type first semiconductor layer (P + 11. Second conductivity type third semiconductor layer (N + )14, they become the second path for current to flow through the thyristor operation.

[0072] like Figure 1 As shown, in the second conductivity type third semiconductor layer (N + )14 is equipped with multiple carrier release sections 11a.

[0073] like Figure 2 As shown, in the first conductivity type first semiconductor layer (P) + A second conductivity type fourth semiconductor layer (N) is disposed on the surface side of )11. + 15.

[0074] The first electrode (T1 electrode) 31 is configured to interact with the second conductivity type third semiconductor layer (N... + 14. Multiple carrier release sections 11a and a first conductivity type first semiconductor layer (P + )11 contact.

[0075] The second electrode (T2 electrode) 32 is configured to interact with the second conductivity type second semiconductor layer (N... + )12 and the first conductivity type second semiconductor layer (P + )21 contact.

[0076] Gate electrode 16 is configured to be connected to the second conductivity type fourth semiconductor layer (N + )15 and the first conductivity type first semiconductor layer (P + )11 contact.

[0077] like Figure 2 As shown, in the first conductivity type first semiconductor layer (P) + The first conductivity type first semiconductor layer (P) on the surface side of 11 + )11 and the second conductivity type first semiconductor layer (N - On the boundary of )13, and the first conductivity type first semiconductor layer (P) + The second conductivity type first semiconductor layer (N) on the surface side of 11 - )13 and the first conductivity type second semiconductor layer (P + A passivation film 17 is disposed on the boundary of 21. However, the passivation film 17 may be disposed only on the boundary, but it may also be disposed on the portion outside the boundary (see reference). Figure 2 ).

[0078] Figure 1 The plurality of carrier release sections 11a shown are each configured such that they are located in the second conductivity type third semiconductor layer (N + )14 forms an opening, the first conductivity type first semiconductor layer (P) + )11 is located within the opening. Therefore, the plurality of charge carrier release sections 11a are configured to... Figure 2 The first electrode (T1 electrode) shown is in contact.

[0079] like Figure 1As shown, a plurality of carrier release sections 11a are arranged, when viewed from above, between a position 16a at a predetermined distance from the gate electrode 16 and the outer edge 16b of the first electrode (T1 electrode) 31 and the inner edge of the passivation film 17.

[0080] Figure 3 as well as Figure 4 Is with Figure 2 The corresponding accompanying drawing is a cross-sectional view used to illustrate the effect of the bidirectional thyristor involved in one aspect of the present invention. Figure 2 The same parts are labeled with the same reference numerals.

[0081] Figure 5 It means from Figure 2 The cross-sectional view shown is a comparative example of a bidirectional thyristor according to one aspect of the present invention, with the carrier release section 11a removed. This cross-sectional view is used to illustrate the situation where false triggering 42 is easily generated without the carrier release section 11a. Figure 2 The same parts are labeled with the same reference numerals.

[0082] Two or more charge carrier release sections 11a are arranged in a manner that connects to the outer edge 16b of the first electrode (T1 electrode) 31. For example... Figure 1 As shown, even if a portion of the multiple carrier release sections 11a is disposed on the outer edge 16b of the first electrode (T1 electrode) 31, the second conductivity type third semiconductor layer (N) in contact with the first electrode (T1 electrode) 31 + The reduction in the area of ​​14 is also very small, so it has almost no impact on the VT characteristics and the gate electrode characteristics.

[0083] like Figure 3 As shown, by connecting the first electrode (T1 electrode) 31 to ground (GND), applying a negative voltage to the second electrode (T2 electrode) 32, and applying a negative voltage to the gate electrode 16, a trigger current flows through the gate electrode, which in turn operates the thyristor. The current flows according to the first electrode (T1 electrode) 31, the first conductivity type, and the first semiconductor layer (P). + 11. Second conductivity type first semiconductor layer (N - 13. First conductivity type second semiconductor layer (P + 21. Second conductivity type second semiconductor layer (N + 12. The flow of the second electrode (T2 electrode) 32 is as shown by arrow 41. At this time, as... Figure 4 As shown, charge carrier 23 diffuses laterally, and remains even after the current flows through the thyristor. Next, as... Figure 2 As shown, when no bias voltage is applied to the gate electrode 16 but a positive voltage is applied to the second electrode (T2 electrode) 32, the residual carrier 23 is transmitted via... Figure 1 The multiple carrier release sections 11a shown do not pass through the second conductivity type third semiconductor layer (N + )14, thus being treated as invalid current, can prevent false triggering. At this time, such as Figure 1 As shown, by making the area of ​​the triangle 33 formed by the adjacent carrier release section 11a located at the outer edge 16b of the first electrode (T1 electrode) 31 and the carrier release section 11a located at the shortest distance from the straight line connecting the adjacent carrier release section 11a smaller than the area of ​​the quadrilateral 22 formed by the carrier release section 11a not located at the outer edge 16b of the first electrode (T1 electrode) 31, the residual carriers 23 can be treated as inactive current more efficiently. Therefore, false triggering can be prevented more effectively, and the (dv / dt)c withstand capacity can be improved.

[0084] In detail, if there are not two or more carrier release sections 11a arranged in a manner that connects to the outer edge 16b of the first electrode (T1 electrode) 31, then as Figure 5 As shown, if a positive bias is applied to the second electrode (T2 electrode) 32, the residual charge carriers 23 described above have the same effect as the gate electrode trigger current. Even if no bias is applied to the gate electrode 16, false triggering of the conduction operation transfer is easily generated. In contrast, in the case of the charge carrier release section 11a... Figure 1 as well as Figure 2 In the bidirectional thyristor shown, residual charge carriers 23 are treated as invalid current. Therefore, when a positive voltage is applied to the second electrode (T2 electrode) 32 and a bias voltage is applied to the gate electrode 16 without causing false triggering, the thyristor operates, and the current flows according to the second electrode (T2 electrode) 32, the first conductivity type second semiconductor layer (P... + 21. Second conductivity type first semiconductor layer (N) - 13. First conductivity type first semiconductor layer (P + 11. Second conductivity type third semiconductor layer (N + 14. Sequential flow of the first electrode (T1 electrode) 31.

[0085] Furthermore, the outer edge 16b of the first electrode (T1 electrode) 31 to which two or more charge carrier release sections 11a are connected is in contact with the passivation film 17 (see reference). Figure 2 Therefore, the residual charge carriers 23 that are also retained under the passivation film 17 can be released more efficiently through the charge carrier release section 11a disposed on the outer edge 16b of the first electrode (T1 electrode) 31 without passing through the second conductivity type third semiconductor layer (N). + )14 is treated as an invalid current. Therefore, false triggering can be prevented more effectively.

[0086] The aforementioned Figure 5 The difficulty of generating a false trigger is called the (dv / dt)c tolerance. The current i when a false trigger occurs can be expressed by the following formula: the steeper the dv / dt of the positive bias, the larger the current based on the residual carrier 23, and the easier it is for a false trigger to occur.

[0087] (Formula) i=C·dv / dt

[0088] As a countermeasure to suppress this false triggering phenomenon, in order to form a structure that allows residual charge carriers 23 to disappear quickly, control based on the lifetime killer factor can be adopted. However, this introduces new problems that have a significant impact on the gate electrode characteristics.

[0089] In addition, as another countermeasure to suppress false triggering, a structure is considered that makes it difficult for residual charge carrier 23 to diffuse laterally. A bidirectional thyristor representing this structure is shown below. Figure 6 . Figure 6 Is with Figure 2 The corresponding accompanying drawings are comparative examples of the present invention, which are related to... Figure 2 The same parts are labeled with the same reference numerals.

[0090] like Figure 6 As shown, by ensuring the upper and lower N + The distance Δ (i.e., the distance between the second conductivity type and the third semiconductor layer (N)) + )14 and the second conductivity type second semiconductor layer (N + The distance Δ in the planar direction of 12 ensures the lateral (planar) movement distance of charge carrier 23. This makes it difficult for residual charge carrier 23 to reach adjacent thyristors. As a result, false triggering is prevented.

[0091] However, in Figure 6 The bidirectional thyristor shown in the comparative example is... Figure 2 The bidirectional thyristors shown are based on the same chip size. Figure 6 The bidirectional thyristor shown in the comparative example, due to the aforementioned distance Δ, has a second conductivity type third semiconductor layer (N) + )14 or the second conductivity type second semiconductor layer (N + The area of ​​12 and Figure 2 The number of bidirectional thyristors shown is reduced compared to the previous version. Therefore, this can lead to problems such as increased VT or negative impact on gate electrode characteristics.

[0092] In contrast, Figure 2 The bidirectional thyristor involved in one aspect of the present invention does not produce the aforementioned problems and can effectively prevent false triggering.

[0093] Figure 9 It means preparation Figure 2 The bidirectional thyristor sample of the present invention shown is... Figure 5 The comparative example sample is shown in the figure, which shows the results of measuring the relationship between VT (conduction voltage) and (dv / dt)c withstand capacity.

[0094] Figure 10 It means preparation Figure 2 The bidirectional thyristor sample of the present invention shown is... Figure 5 The comparative example sample is shown in the figure, which shows the results of measuring the relationship between IGT (gate trigger current) and (dv / dt)c tolerance.

[0095] Figure 11 It means preparation Figure 2 The bidirectional thyristor sample of the present invention shown is... Figure 5 The comparative example sample is shown in the figure, which shows the results of measuring the relationship between VGT (gate trigger voltage) and (dv / dt)c tolerance.

[0096] exist Figures 9-11 middle, Figure 2 The measurement results of the bidirectional thyristor sample of the present invention shown are for the "present invention". Figure 5 The measurement results for the comparative example sample shown are "existing countermeasures".

[0097] like Figures 9-11 As shown, the following was confirmed: Multiple carrier release sections 11a are formed. Figure 2 The bidirectional thyristor of the present invention shown is different from that without multiple carrier release sections 11a. Figure 5 Compared to the bidirectional thyristor shown in the comparative example, the (dv / dt)c withstand capacity is improved.

[0098] In one aspect of the present invention, the bidirectional thyristor described above [2] in [1] has two or more carrier release sections 11a arranged in connection with the outer edge 16b of the first electrode (T1 electrode) 31, which may have a notch shape, a polygonal shape or an elliptical shape when viewed from above.

[0099] The following is a detailed explanation.

[0100] Figure 7 It means Figure 1 The top view of the modified example 1 of the bidirectional thyristor shown. Figure 8 It means Figure 1 The diagram shows a top view of a modified example 2 of the bidirectional thyristor. It should be noted that... Figure 7 as well as Figure 8 In the middle, to and Figure 1 The same parts are labeled with the same reference numerals.

[0101] like Figure 1, Figure 7 as well as Figure 8 As shown, the two or more charge carrier release sections 11a arranged in connection with the outer edge of the first electrode (T1) may have a notch shape, a polygonal shape or an elliptical shape when viewed from above.

[0102] In one aspect of the present invention, the bidirectional thyristor described above [3] is preferably, based on the above [1] or [2], that when viewed from above, the density of the carrier release portion 11a near the outer edge 16b of the first electrode (T1 electrode) 31 is higher than the density of the carrier release portion 11a in the region outside the outer edge 16b of the first electrode (T1 electrode) 31.

[0103] The following is a detailed explanation.

[0104] like Figure 1 As shown, when viewed from above, the density of the carrier release section 11a near the outer edge 16b of the first electrode (T1) should be higher than the density of the carrier release section 11a in the region outside the outer edge 16b of the first electrode (T1). This density is... Figure 1 The value is obtained by dividing the number of carrier release sections 11a near the outer edge 16b of the first electrode (T1) by the area of ​​the planar region near the outer edge 16b of the first electrode (T1). As a result, it is possible to... Figure 2 The residual charge carriers 11a shown are released more efficiently via the charge carrier release section 11a disposed near the outer edge 16b of the first electrode (T1) without passing through the second conductivity type third semiconductor layer (N). + )14 is treated as an ineffective current. It should be noted that the carrier release section 11a near the outer edge 16b of the first electrode (T1) refers to the section forming... Figure 1 The carrier release section 11a of triangle 33 shown refers to the triangle 33 formed by the adjacent carrier release section 11a located at the outer edge 16b of the first electrode (T1) and the carrier release section 11a located at the position with the shortest distance from the straight line connecting the adjacent carrier release section 11a.

[0105] Explanation of reference numerals in the attached figures

[0106] 11: First conductivity type first semiconductor layer (P) + );

[0107] 11a: Carrier release section;

[0108] 12: Second conductivity type second semiconductor layer (N) + );

[0109] 13: Second conductivity type first semiconductor layer (N) - );

[0110] 14: Second conductivity type third semiconductor layer (N) + );

[0111] 15: Second conductivity type fourth semiconductor layer (N) + );

[0112] 16: Gate electrode;

[0113] 16b: Outer edge of the first electrode;

[0114] 17: Passivation film;

[0115] 21: First conductivity type second semiconductor layer (P) + Type semiconductor substrate: P + );

[0116] 22: A quadrilateral formed by the carrier release portion not located at the outer edge of the first electrode;

[0117] 31: First electrode (T1 electrode);

[0118] 32: Second electrode (T2 electrode);

[0119] 33: A triangle formed by the adjacent carrier release section located at the outer edge of the first electrode and the carrier release section located at the shortest distance from the straight line connecting the adjacent carrier release section.

Claims

1. A bidirectional thyristor, characterized in that, The bidirectional thyristor has the following characteristics: First conductivity type, first semiconductor layer; A second conductivity type first semiconductor layer is disposed on the back side of the first conductivity type first semiconductor layer; A first conductivity type second semiconductor layer is disposed on the back side of the second conductivity type first semiconductor layer; A second conductivity type second semiconductor layer is disposed on the back side of the first conductivity type second semiconductor layer; A second conductivity type third semiconductor layer is disposed on the surface side of the first conductivity type first semiconductor layer; Multiple carrier release sections are disposed on the second conductivity type third semiconductor layer; A second conductivity type fourth semiconductor layer is disposed on the surface side of the first conductivity type first semiconductor layer; The first electrode is in contact with the second conductivity type third semiconductor layer, the plurality of carrier release sections, and the first conductivity type first semiconductor layer; The second electrode is in contact with the second conductivity type second semiconductor layer and the first conductivity type second semiconductor layer; The gate electrode is in contact with the second conductivity type fourth semiconductor layer and the first conductivity type first semiconductor layer; as well as A passivation film is disposed on the boundary between the first conductive first semiconductor layer and the second conductive first semiconductor layer on the surface side of the first conductive first semiconductor layer, and on the boundary between the second conductive first semiconductor layer and the first conductive second semiconductor layer on the surface side of the first conductive first semiconductor layer. Each of the plurality of carrier release sections is configured to form an opening in the second conductivity type third semiconductor layer, with the first conductivity type first semiconductor layer located within the opening. The plurality of carrier release sections are arranged, when viewed from above, between a predetermined distance from the gate electrode and the outer edge of the first electrode. Two or more of the multiple carrier release sections are arranged in a manner that connects to the outer edge of the first electrode. The outer edge of the first electrode, which is connected to two or more of the plurality of charge carrier release sections, is in contact with the passivation film. When viewed from above, the area of ​​the triangle formed by the adjacent carrier release portion located at the outer edge of the first electrode and the carrier release portion located at the position with the shortest distance from the straight line connecting the adjacent carrier release portions is smaller than the area of ​​the quadrilateral formed by the carrier release portions not located at the outer edge of the first electrode. The residual charge carriers immediately after the current flows from the first electrode to the second electrode are treated as invalid current and do not flow through the second conductivity type third semiconductor layer, but instead flow to the first electrode through the multiple charge carrier release sections, thereby improving the (dv / dt)c withstand capacity by preventing false triggering.

2. The bidirectional thyristor according to claim 1, characterized in that, Two or more carrier release sections arranged in a manner that connects to the outer edge of the first electrode have a notch shape, a polygonal shape, or an elliptical shape when viewed from above.

3. The bidirectional thyristor according to claim 1 or 2, characterized in that, When viewed from above, the density of the carrier release portion near the outer edge of the first electrode is higher than the density of the carrier release portion in the region outside the outer edge of the first electrode.

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