Peak current detection circuit and electronic device

Abstract

The application provides a peak current detection circuit and an electronic device. The peak current detection circuit comprises a BOOST switching circuit, a MOS transistor NM1, a MOS transistor NM2, a MOS transistor NM3, a MOS transistor NM4, a MOS transistor NM5, a MOS transistor NM6, a first Nmos transistor group RM1, a second Nmos transistor group RM2, a first current source, a second current source and a third current source. The technical scheme provided by the application has the advantage of expanding the application range of the peak current detection circuit.

Description

Technical Field

[0001] This invention relates to the field of electronic devices, and more specifically to a peak current detection circuit and electronic device. Background Technology

[0002] Existing peak current detection circuits use compensated operational amplifiers, meaning they require amplifiers. This results in bandwidth limitations; generally, current detection cannot be performed at frequencies exceeding 1 MHz. Therefore, existing current detection circuits are not suitable for peak current detection at higher circuit frequencies (above 1 MHz). Summary of the Invention

[0003] This invention provides a peak current detection circuit and electronic device that can detect peak current without using an amplifier, thereby meeting the peak current detection requirements at high circuit frequencies and expanding the applicability of the current detection circuit.

[0004] In a first aspect, embodiments of the present invention provide a peak current detection circuit, the peak current detection circuit comprising: a BOOST switching circuit, MOSFETs NM1, NM2, NM3, NM4, NM5, and NM6, a first NMOSFET group RM1 and a second NMOSFET group RM2, a first current source, a second current source, and a third current source; wherein,

[0005] One end of the BOOST switch circuit, XL1, is connected to the drain of MOSFET NM2. The source of MOSFET NM2 is connected to the drain of MOSFET NM1, the gate of MOSFET NM3, the source of MOSFET NM3, and the output of the first NMOSFET group RM1. The other end of the BOOST switch circuit, including the sources of MOSFET NM1 and NM3, is grounded.

[0006] The input terminal of the first NMOS transistor group RM1 is connected to the source of MOSFET NM6 and the output terminal of the third current source. The input terminal of the second NMOS transistor group RM2 is connected to the source of MOSFET NM4. The output terminal of the second NMOS transistor group RM2 is grounded. The control terminals of RM1, the control terminals of the second NMOS transistor group RM2, and the gate of MOSFET NM1 are all connected to the power supply voltage PVIN. The gate of MOSFET NM2 is connected to the clock signal CLK1.

[0007] The drain of MOSFET NM6 is connected to the first current source. The drains of MOSFET NM4 and NM5, as well as the gate of MOSFET NM6, are all connected to the output of the second current source. The gate of MOSFET NM5 is connected to the output of the first current source. The source of MOSFET NM5 is connected to the input of RM2. The drain of MOSFET NM5 is connected to the peak current detection port.

[0008] In a second aspect, an electronic device is provided, the electronic device including the peak current detection circuit provided in the first aspect.

[0009] Implementing the embodiments of the present invention has the following beneficial effects:

[0010] The technical solution provided in this application achieves peak current detection through a combination of MOSFET, BOOST switching circuit and current source, without the need for amplifier, thereby enabling detection of high-frequency circuits and expanding the applicability of current detection circuits. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of a peak current detection circuit provided in this application;

[0013] Figure 2 This is a schematic diagram of a peak current detection circuit provided in Embodiment 1 of this application. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0016] In this document, the term "embodiment" means that a particular feature, result, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0017] See Figure 1 , Figure 1 This application provides a schematic diagram of a peak current detection circuit, as shown below. Figure 1 As shown, the peak current detection circuit includes: a BOOST switch circuit, MOSFETs NM1, NM2, NM3, NM4, NM5, and NM6, a first N-MOSFET group RM1 and a second N-MOSFET group RM2, a first current source, a second current source, and a third current source; wherein,

[0018] One end of the BOOST switch circuit, XL1, is connected to the drain of NM2. The source of NM2 is connected to the drain of NM1, the gate of NM3, the source of NM3, and the output of RM1. The source of NM1, the source of NM3, and the other end of the BOOST switch circuit are grounded.

[0019] The input of RM1 is connected to the source of NM6 and the output of the third current source. The input of RM2 is connected to the source of NM4. The output of RM2 is grounded. The control terminals of RM1 and RM2 and the gate of NM1 are all connected to the power supply voltage PVIN. The gate of NM2 is connected to the clock signal CLK1.

[0020] The drain of NM6 is connected to the first current source. The drain of NM4, the drain of MOSFET NM5, and the gate of NM6 are all connected to the output of the second current source. The gate of NM5 is connected to the output of the first current source. The source of NM5 is connected to the input of RM2. The drain of NM5 is connected to the peak current detection port.

[0021] The technical solution provided in this application achieves peak current detection through a combination of MOSFET, BOOST switching circuit and current source, without the need for an amplifier. The technical solution of this application does not have the parasitic large capacitor in the connection method of MOSFET NM3, thereby avoiding the influence of large capacitor on high frequencies (above 1 MHz). Therefore, it can realize the detection of high frequency circuits and expand the applicable range of current detection circuit.

[0022] Example,

[0023] Both RM1 and RM2 mentioned above include multiple NMOS transistors connected in series. The gate of the multiple NMOS transistors connected in series is the control terminal (RM1 or RM2), the drain of the multiple NMOS transistors connected in series is the input terminal, and the source is the output terminal.

[0024] For example, a BOOST switching circuit specifically includes: a resistor, a capacitor, an inductor, and a switching transistor; wherein,

[0025] One end of the first resistor R1 is connected to the voltage output terminal Vout. The source of the first switch SM1 and one end of the first capacitor C1 are both connected to the voltage output terminal Vout. The gate of the first switch SM1 is connected to one end of the inductor L1, and the other end of the inductor L1 is connected to the power supply voltage PVIN. The source of the second switch SM2 is connected to one end of the inductor L1, and the drain of the second switch SM2, the other end of the first resistor, and the other end of the first capacitor C1 are grounded.

[0026] For example, the first current source, the second current source, and the third current source mentioned above may specifically include: a reference current Iref, a PMOS transistor PM1, a PMOS transistor PM2, and multiple PMOS transistor groups;

[0027] In this circuit, the reference current Iref is connected to the source of PM2, the drain of PM2 is connected to the source of PM1, the drain of PM1 is connected to the equipotential terminal, the gate of PM1 is also connected to the control terminal of PMOS transistor groups PM3, PM5, and PM7, and the gate of PM2 is also connected to the control terminal of PMOS transistor groups PM4, PM6, and PM8. PMOS transistor groups PM3 and PM4 are connected in series, PMOS transistor groups PM5 and PM6 are connected in series, and PMOS transistor groups PM7 and PM8 are connected in series. The input terminals of PMOS transistor groups PM3, PM5, and PM7 are connected to the equipotential terminal. The output terminal of PMOS transistor group PM4 is the output terminal of the first current source, the output terminal of PMOS transistor group PM6 is the output terminal of the second current source, and the output terminal of PMOS transistor group PM8 is the output terminal of the third current source.

[0028] For example, the above PMOS transistor group includes multiple PMOS transistors connected in series. The gate of the multiple PMOS transistors connected in series is the control terminal, the drain of the multiple PMOS transistors connected in series is the input terminal, and the source is the output terminal.

[0029] For example, the ratio of the number of POS tubes in the above multiple Pmos tube groups is: PM1:PM3:PM5:PM7 = 1:m:m:n.

[0030] For example, the first current source, the second current source, and the third current source may further include: a current-limiting resistor R2, one end of which is connected to the reference current Iref, and the other end of which is connected to the source of PM2.

[0031] The aforementioned current-limiting resistor R2 limits the reference current once and provides some overcurrent protection for the current source.

[0032] Example 1

[0033] See Figure 2 , Figure 2 This is a schematic diagram of a peak current detection circuit provided in Embodiment 2 of this application, as shown below. Figure 2 As shown, in Embodiment 1 of this application, PM1:PM3:PM5:PM7 = 1:m:m:n. The above peak current detection circuit structure includes:

[0034] The reference current Iref is connected to the source of PM2, the drain of PM2 is connected to the source of PM1, the drain of PM1 is connected to the equipotential terminal, the gate of PM1 is also connected to the control terminal of PMOS transistor groups PM3, PM5, and PM7, and the gate of PM2 is also connected to the control terminal of PMOS transistor groups PM4, PM6, and PM8. PMOS transistor groups PM3 and PM4 are connected in series, PMOS transistor groups PM5 and PM6 are connected in series, and PMOS transistor groups PM7 and PM8 are connected in series. The input terminals of PMOS transistor groups PM3, PM5, and PM7 are connected to the equipotential terminal. The output terminal of PMOS transistor group PM4 is the output terminal of the first current source, the output terminal of PMOS transistor group PM6 is the output terminal of the second current source, and the output terminal of PMOS transistor group PM8 is the output terminal of the third current source.

[0035] One end of the BOOST switch circuit, XL1, is connected to the drain of NM2. The source of NM2 is connected to the drain of NM1, the gate of NM3, the source of NM3, and the output of RM1. The source of NM1, the source of NM3, and the other end of the BOOST switch circuit are grounded.

[0036] The input of RM1 is connected to the source of NM6 and the output of the third current source. The input of RM2 is connected to the source of NM4. The output of RM2 is grounded. The control terminals of RM1 and RM2 and the gate of NM1 are all connected to the power supply voltage PVIN. The gate of NM2 is connected to the clock signal CLK1.

[0037] The drain of NM6 is connected to the first current source. The drain of NM4, the drain of MOSFET NM5, and the gate of NM6 are all connected to the output of the second current source. The gate of NM5 is connected to the output of the first current source. The source of NM5 is connected to the input of RM2. The drain of NM5 is connected to the peak current detection port.

[0038] The specific structure of the BOOST switch circuit is as follows: Figure 1 The description of the illustrated embodiment will not be repeated here.

[0039] Figure 1 In the circuit, the reference current Iref comes from the reference circuit. MOSFETs PM1 to PM8 form a current mirror structure, which generates currents I1, I2, and I3. Let the ratio of the number of MOSFETs PM1 to MOSFETs PM3, PM5, and PM7 be 1:M:M:N.

[0040] The specific calculation methods for the first current source I1, the second current source I2, and the third current source I3 are as follows:

[0041] I1 = I2 = m * Iref;

[0042] I3 = n * Iref.

[0043] When SM2 is on and SM1 is off, the power supply voltage PVIN charges the inductor L1, and the current Io rises slowly over time. Therefore, during the on-time T of SM2, the current Io satisfies the following formula:

[0044] I0 = PVIN * T / L1.

[0045] During the inductor charging phase, the drain-source voltage of MOSFET SM2 is:

[0046] V SM2 =2*I0 / μ0C 0x *(W / L)*(V Gs -V th );

[0047] To ensure that the resistances of MOSFETs NM1 and NM2 are greater than those of MOSFET SM2, the widths of MOSFETs NM1 and NM2 should be much smaller than the width of MOSFET SM2. The voltage at terminal C can then be calculated as follows:

[0048] Vc = (R NM1 *V SM2 ) / (R NM1 +R NM2 ).

[0049] The MOSFET NM3 is connected to the C terminal in the form of a diode, which can ensure that the MOSFETs NM1 and NM2 always operate in the linear region.

[0050] The value of the resistor RM1 formed by MOSFETs NM1_1 to NM1_N is:

[0051] RM1 = 2 / μ0C 0x *(W / n*L)*(V Gs -V th );

[0052] Since MOSFETs NM5 and NM4 form negative feedback, the effect of the voltage at terminal C on the voltage at terminal A is approximately equal to the effect of the voltage at terminal C on the voltage at terminal B. Because the MOS resistor RM2 formed by MOSFETs NM2_1 to NM2_N is equal to the resistor RM1 formed by MOSFETs NM1_1 to NM1_N, and ignoring the influence of branch currents I1 and I3 on ​​the circuit, the current Ipeak is approximately:

[0053] Ipeak = Vc / RM_2;

[0054] Therefore, the detected peak current Isense is:

[0055] Isense≈Ipeak-I2.

[0056] Therefore, it is possible to detect peak current.

[0057] This application also provides an electronic device, which includes the above-described components. Figure 1 or Figure 2 The peak current detection circuit shown is shown.

[0058] The embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A peak current detection circuit, characterized in that, The peak current detection circuit includes: a BOOST switch circuit, MOSFETs NM1, NM2, NM3, NM4, NM5, and NM6, a first N-MOSFET group RM1 and a second N-MOSFET group RM2, a first current source, a second current source, and a third current source; wherein, One end of the BOOST switch circuit, XL1, is connected to the drain of MOSFET NM2. The source of MOSFET NM2 is connected to the drain of MOSFET NM1, the gate of MOSFET NM3, the drain of MOSFET NM3, and the output of the first NMOSFET group RM1. The other end of the BOOST switch circuit is grounded. The input terminal of the first NMOS transistor group RM1 is connected to the source of MOSFET NM6 and the output terminal of the third current source. The input terminal of the second NMOS transistor group RM2 is connected to the source of MOSFET NM4. The output terminal of the second NMOS transistor group RM2 is grounded. The control terminals of the first NMOS transistor group RM1, the control terminals of the second NMOS transistor group RM2, and the gate of MOSFET NM1 are all connected to the power supply voltage PVIN. The gate of MOSFET NM2 is connected to the clock signal CLK1. The drain of MOSFET NM6 is connected to the first current source. The drain, gate, and gate of MOSFET NM4 and MOSFET NM6 are all connected to the output of the second current source. The gate of MOSFET NM5 is connected to the output of the first current source. The source of MOSFET NM5 is connected to the input of the second NMOSFET group RM2. The drain of MOSFET NM5 is connected to the peak current detection port.

2. The peak current detection circuit according to claim 1, characterized in that, The first NMOS transistor group RM1 and the second NMOS transistor group RM2 both include multiple NMOS transistors connected in series. The gate of the multiple NMOS transistors connected in series is the control terminal, the drain of the multiple NMOS transistors connected in series is the input terminal, and the source is the output terminal.

3. The peak current detection circuit according to claim 1, characterized in that, The BOOST switching circuit specifically includes: a first resistor R1, a first capacitor C1, an inductor L1, a first switching transistor SM_1, and a second switching transistor SM_2. One end of the first resistor R1 is connected to the voltage output terminal Vout. The source of the first switch SM_1 and one end of the first capacitor C1 are both connected to the voltage output terminal Vout. The drain of the first switch SM_1 is connected to one end of the inductor L1. The other end of the inductor L1 is connected to the power supply voltage PVIN. The source of the second switch SM_2 is connected to one end of the inductor L1. The drain of the second switch SM_2, the other end of the first resistor, and the other end of the first capacitor C1 are grounded.

4. The peak current detection circuit according to claim 1, characterized in that, The first current source, the second current source, and the third current source specifically include: a reference current Iref, Pmos transistor PM1, Pmos transistor PM2, and multiple Pmos transistor groups. In this configuration, the reference current Iref is connected to the source of PMOS transistor PM2, the drain of PMOS transistor PM2 is connected to the source of PMOS transistor PM1, the drain of PMOS transistor PM1 is connected to the equipotential terminal, the gate of PMOS transistor PM1 is also connected to the control terminals of PMOS transistor groups PM3, PM5, and PM7, and the gate of PMOS transistor PM2 is also connected to the control terminals of PMOS transistor groups PM4, PM6, and PM8; PMOS transistor group PM3... The PMOS transistors PM4, PM5, and PM6 are connected in series, and PM7 and PM8 are connected in series. The input terminals of PMOS transistors PM3, PM5, and PM7 are connected to an equipotential terminal. The output terminal of PMOS transistor PM4 is the output terminal of the first current source, the output terminal of PMOS transistor PM6 is the output terminal of the second current source, and the output terminal of PMOS transistor PM8 is the output terminal of the third current source.

5. The peak current detection circuit according to claim 4, characterized in that, A PMOS transistor group consists of multiple PMOS transistors connected in series. The gate of the multiple PMOS transistors connected in series is the control terminal, the drain of the multiple PMOS transistors connected in series is the input terminal, and the source is the output terminal.

6. The peak current detection circuit according to claim 5, characterized in that, The ratio of the number of Pmos tubes in multiple Pmos tube groups is: PM1:PM3:PM5:PM7=1:m:m:n.

7. The peak current detection circuit according to claim 4, characterized in that, The peak current detection circuit further includes a current-limiting resistor R2, one end of which is connected to the reference current Iref, and the other end of which is connected to the source of the Pmos transistor PM2.

8. An electronic device, characterized in that, The electronic device includes the peak current detection circuit according to any one of claims 1-7.

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