直接内存访问电路及其操作方法
By optimizing data transmission in the direct memory access circuit through buffer circuits and arbitration mechanisms, the problem of latency mismatch between the data source and destination ends is solved, thereby improving the circuit's performance and data processing efficiency.
CN116204464BActive Publication Date: 2026-07-17SIGMASTAR TECH LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SIGMASTAR TECH LTD
- Filing Date
- 2023-03-28
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
In direct memory access circuits, the latency between the data source and the data destination is not fixed, which may cause data transmission to be blocked and affect performance.
Method used
By employing a buffer circuit, first and second channels, a write status judgment circuit, a read address generation circuit, and a control circuit, and through arbitration and count value management, data reading and writing operations are optimized to achieve out-of-order processing.
Benefits of technology
It improves the efficiency of direct memory access circuitry, ensuring that data transfer is not affected by single-channel latency, and that data writing and reading can be interrupted and performed discontinuously.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN116204464B_ABST
Abstract
本申请提供一种直接内存访问电路及其操作方法。直接内存访问电路包含缓冲电路、第一通道及第二通道，其操作方法包含：根据第一通道的第一读取请求及第二通道的第二读取请求，分别从缓冲电路确定第一起始地址及第二起始地址，第一读取请求及第二读取请分别对应于第一数据及第二数据；根据第一起始地址及读计数值确定读取地址；根据读取地址从缓冲电路读取第一数据的第一部分，并且更新读计数值；在读取第一数据的第一部分之后，根据第二起始地址从缓冲电路读取第二数据的至少一部分；根据第一起始地址及更新后的读计数值更新读取地址；以及，根据更新后的读取地址从缓冲电路读取第一数据的第二部分。
Need to check novelty before this filing date? Find Prior Art