A general serial port dynamic scanning test circuit

Abstract

This invention specifically relates to a general-purpose serial port dynamic scanning test circuit, including a control circuit. The control circuit includes a microcontroller U1, which is connected to a first interface CN1, a second interface CN2, a third interface CN3, a fourth interface CN4, and an I / O interface. The I / O interface is connected to port circuits. At least two DI port detection circuits are also connected between pins 39 and 40 of the microcontroller U1. The I / O interface is also connected to a continuity circuit. The beneficial effects of this invention are: the core hardware of this circuit is designed through the control circuit and the DI port detection circuit. The DI port detection circuit can realize dynamic scanning testing, greatly enhancing functionality. In addition, this circuit has at least two cascaded DI port detection circuits, solving the problem of insufficient DI ports on conventional I / O cards, thereby saving costs.

Description

Technical Field

[0001] This invention relates to the field of TP testing technology, and more specifically, to a general-purpose serial port dynamic scanning test circuit. Background Technology

[0002] Currently, serial port cards used in the market typically have only 8 DI detection ports. The limited number of DI detection ports requires multiple additional cards to be used in series, which takes up space and wastes costs. Furthermore, they generally do not integrate relay output functionality.

[0003] For example, Chinese patent application CN103227375A discloses a combined-installation bus serial port card, including: a connector plate, multiple connector plugs, a circuit board, connector wires, a connector plate, and multiple threaded holes. The connector plate has threaded holes at both ends. The circuit board is soldered to the edge of the connector plate. Three connector plugs are mounted on the surface of the connector plate, and connector wires connect the three connector plugs to the circuit board. The bottom of the circuit board is the connector plate. This serial port card lacks a scanning function for DI dynamic signals, requiring cumbersome secondary development by the user, and cannot perform intelligent testing of DI dynamic signals. Summary of the Invention

[0004] This invention aims to at least solve one of the technical problems existing in the prior art. Therefore, one objective of this invention is to provide a universal serial port dynamic scanning test circuit, which can reduce the difficulty and labor intensity of work, and improve the quality and efficiency of testing.

[0005] According to a general serial port dynamic scanning test circuit of the present invention, a control circuit is included. The control circuit includes a microcontroller U1. The microcontroller U1 is connected to a first interface CN1, a second interface CN2, a third interface CN3, a fourth interface CN4 and an IO interface. The IO interface is connected to a port circuit. At least two DI port detection circuits are also connected between pins 39 and 40 of the microcontroller U1. The IO interface is also connected to a continuity circuit.

[0006] Specifically, pin 1 of the microcontroller U1 is connected to the reset switch REST and the ICSP interface. Pin 3 of the ICSP interface is connected to the fifth capacitor C5. The fifth capacitor C5 is connected in parallel with the third capacitor C3 and the fourth capacitor C4. Pin 2 of the ICSP interface is connected to the first resistor R1. The first resistor R1 is connected to the sixth capacitor C6. Pin 32 of the microcontroller U1 is connected to the second resistor R2. Pins 13 and 14 of the microcontroller U1 are connected to the first capacitor C1 and the second capacitor C2, respectively. A crystal oscillator OCS is connected between the first capacitor C1 and the second capacitor C2.

[0007] Specifically, the port circuit includes a first resistor array RP1 and a second resistor array RP2, which are connected together, and the common terminal between the first resistor array RP1 and the second resistor array RP2 is connected to the IO interface.

[0008] Specifically, the microcontroller U1 is model PIC16F877A.

[0009] Specifically, the communication circuit includes a communication chip U2, a J-485 interface, an RS485 interface, and a seventh capacitor C7. Pins 1, 2, 3, and 4 of the communication chip U2 are connected to the J-485 interface, pins 7 and 6 of the communication chip U2 are connected to the RS485 interface, and pins 5 and 8 of the communication chip U2 are connected to the seventh capacitor C7.

[0010] Specifically, the communication chip U2 is model MAX485.

[0011] Specifically, the switching circuit includes a third resistor R3, a transistor Q1, a first diode D1, and a relay K1. One end of the third resistor R3 is connected to the base of the transistor Q1, and the collector of the transistor Q1 is connected to both the first diode D1 and the relay K1. The third resistor R3 in the switching circuit 4 is connected to the I / O interface. There are at least four switching circuits 4, and the transistor Q1 is an NPN transistor.

[0012] Specifically, the DI port detection circuit includes a detection chip U3, which is a 74HC165 chip. Pins 1 and 2 of the detection chip U3 are connected to pins 39 and 40 of the microcontroller U1, respectively.

[0013] The beneficial effects of this invention are as follows: This circuit uses a control circuit and a DI port detection circuit as its core hardware design. The DI port detection circuit enables dynamic scanning testing, greatly enhancing functionality. Furthermore, this circuit features at least two DI port detection circuits cascaded together, solving the problem of insufficient DI ports on conventional IO cards and thus saving costs. Attached Figure Description

[0014] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings.

[0015] Figure 1 This is the control circuit diagram of the present invention.

[0016] Figure 2 This is the port circuit diagram of the present invention.

[0017] Figure 3 This is the communication circuit diagram of the present invention.

[0018] Figure 4 This is the on / off circuit diagram of the present invention.

[0019] Figure 5 This is the DI port detection circuit diagram of the present invention.

[0020] Figure 6 This is the operational logic diagram of the present invention.

[0021] As shown in the attached diagram, the circuit diagram is labeled as follows: 1. Control circuit; 2. Port circuit; 3. Communication circuit; 4. On / off circuit; 5. DI port detection circuit. Implementation

[0022] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0023] The following is for reference. Figures 1 to 6 A general serial port dynamic scanning test circuit according to an embodiment of the present invention is described, including a control circuit 1. The control circuit 1 includes a microcontroller U1. The microcontroller U1 is connected to a first interface CN1, a second interface CN2, a third interface CN3, a fourth interface CN4 and an IO interface. The IO interface is connected to a port circuit 2. At least two DI port detection circuits 5 are also connected between pins 39 and 40 of the microcontroller U1. The IO interface is also connected to a continuity circuit 4.

[0024] This circuit uses control circuit 1 and DI port detection circuit 5 as its core hardware. DI port detection circuit 5 enables dynamic scanning testing, greatly enhancing functionality. Furthermore, this circuit incorporates at least two cascaded DI port detection circuits, solving the problem of insufficient DI ports on conventional I / O cards and thus saving costs.

[0025] like Figure 1 As shown, pin 1 of the microcontroller U1 is connected to the reset switch REST and the ICSP interface. Pin 3 of the ICSP interface is connected to the fifth capacitor C5. The fifth capacitor C5 is connected in parallel with the third capacitor C3 and the fourth capacitor C4. Pin 2 of the ICSP interface is connected to the first resistor R1. The first resistor R1 is connected to the sixth capacitor C6. Pin 32 of the microcontroller U1 is connected to the second resistor R2. Pins 13 and 14 of the microcontroller U1 are connected to the first capacitor C1 and the second capacitor C2, respectively. A crystal oscillator OCS is connected between the first capacitor C1 and the second capacitor C2. Figure 1As shown, the microcontroller U1 is model PIC16F877A. The microcontroller U1 has a central processing unit (CPU) with data processing capabilities, random access memory (RAM), read-only memory (ROM), multiple I / O ports and interrupt system, timer / counter and other functions (and can also add circuits including display driver circuit, pulse width modulation circuit, analog multiplexer, A / D converter and other circuits).

[0026] The ICSP interface is connected to communication circuit 3.

[0027] like Figure 2 As shown, the port circuit 2 includes a first resistor array RP1 and a second resistor array RP2, which are connected together. The common terminal between the first resistor array RP1 and the second resistor array RP2 is connected to the I / O interface. The first resistor array RP1 and the second resistor array RP2 can be used as inputs or outputs.

[0028] like Figure 3 As shown, the communication circuit 3 includes a communication chip U2, a J-485 interface, an RS485 interface, and a seventh capacitor C7. Pins 1, 2, 3, and 4 of the communication chip U2 are connected to the J-485 interface, pins 7 and 6 are connected to the RS485 interface, and pins 5 and 8 are connected to the seventh capacitor C7. The communication chip U2 is a MAX485. The communication circuit 3 operates on a single +5V power supply with a rated current of 300 μA and uses half-duplex communication. It converts TTL levels to RS-485 levels. The communication chip U2 has a very simple structure and pinout, containing an internal driver and receiver. The RO and DI terminals are the receiver output and driver input, respectively. When connecting to a microcontroller, simply connect them to the microcontroller's RXD1 and TXD1 pins, respectively. The RE and DE terminals are the receive and transmit enable terminals, respectively. When RE is logic 0, the device is in receive mode; when DE is logic 1, the device is in transmit mode. Because the MAX485 operates in half-duplex mode, only one pin of the microcontroller is needed to control these two pins. The A and B terminals are the differential signal terminals for receive and transmit, respectively. When the level of pin A is higher than that of pin B, it represents a transmitted data 1; when the level of pin A is lower than that of pin B, it represents a transmitted data 0. Wiring when connecting to a microcontroller is very simple. Only one signal is needed to control the MAX485's receive and transmit. A matching resistor, typically 100Ω, should be added between terminals A and B. The RS485 interface is connected to the ICSP interface.

[0029] like Figure 4As shown, the switching circuit 4 includes a third resistor R3, a transistor Q1, a first diode D1, and a relay K1. One end of the third resistor R3 is connected to the base of the transistor Q1, and the collector of the transistor Q1 is connected to both the first diode D1 and the relay K1. The third resistor R3 in the switching circuit 4 is connected to the I / O interface. The switching circuit 4 has at least four circuits, and the transistor Q1 is an NPN transistor. When the transistor Q1 is energized, it is energized, causing the relay K1 to conduct; conversely, when the transistor Q1 is de-energized, it is de-energized, causing the relay K1 to disconnect.

[0030] like Figure 5 As shown, the DI port detection circuit 5 includes a detection chip U3, model 74HC165. Pins 1 and 2 of the detection chip U3 are connected to pins 39 and 40 of the microcontroller U1, respectively. Eight DI port detection circuits 5 are configured in this circuit. The detection chips detect DI ports Net1 to Net8 respectively, and the DI port detection circuits 5 are cascaded. The signals output by the DI port detection circuits 5 are sent to the control circuit 1, and finally controlled by the microcontroller U1.

[0031] like Figure 6 As shown, the working principle of this embodiment is as follows.

[0032] Step 1: Control circuit 1 starts and performs system initialization.

[0033] Step 2: Detect the working status of communication circuit 3 and whether communication data is received from communication circuit 3. If communication data is received, proceed to determine whether it matches the local IP address; otherwise, return to system initialization.

[0034] Step 3: Control circuit 1 checks if the data CRC check passes; otherwise, it returns to step 2 to re-check communication circuit 3 until the CRC check is successful and proceeds to the next step.

[0035] Step 4: Reset the relevant variables through communication circuit 3 and resolve the data.

[0036] Step 5: The DI port detection circuit 5 enters the dynamic DI port scan detection mode to check if a start signal is received; otherwise, it restarts the DI port scan.

[0037] Step 6: Based on the communication circuit 3, monitor the status of each DI port, obtain the dynamic scan test results, and send the result data to the control circuit 1.

[0038] Additionally, in step 5: when the DI port detection circuit 5 enters the dynamic scanning detection mode, it enters the static reading of the status of all DI ports once. The control circuit 1 controls the on / off circuit 4 to engage or disengage according to the communication data, and the on / off circuit 4 sends the result data to the control circuit 1.

[0039] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A general-purpose serial port dynamic scanning test circuit, comprising a control circuit (1), characterized in that: The control circuit (1) includes a microcontroller U1, which is connected to a first interface CN1, a second interface CN2, a third interface CN3, a fourth interface CN4 and an IO interface. The IO interface is connected to the port circuit (2). At least two DI port detection circuits (5) are also connected between pins 39 and 40 of the microcontroller U1. The IO interface is also connected to a switching circuit (4). The port circuit (2) includes a first resistor array RP1 and a second resistor array RP2, the first resistor array RP1 and the second resistor array RP2 are connected to each other, and the common terminal between the first resistor array RP1 and the second resistor array RP2 is connected to the IO interface. The switching circuit (4) includes a third resistor R3, a transistor Q1, a first diode D1 and a relay K1. One end of the third resistor R3 is connected to the base of the transistor Q1, and the collector of the transistor Q1 is connected to the first diode D1 and the relay K1 respectively. The third resistor R3 on the switching circuit (4) is connected to the IO interface. There are at least 4 switching circuits (4), and the transistor Q1 is an NPN transistor. The DI port detection circuit (5) includes a detection chip U3, the model of which is 74HC165. Pins 1 and 2 of the detection chip U3 are connected to pins 39 and 40 of the microcontroller U1, respectively.

2. The universal serial port dynamic scanning test circuit according to claim 1, characterized in that: Pin 1 of the microcontroller U1 is connected to the reset switch REST and the ICSP interface. Pin 3 of the ICSP interface is connected to the fifth capacitor C5. The fifth capacitor C5 is connected in parallel with the third capacitor C3 and the fourth capacitor C4. Pin 2 of the ICSP interface is connected to the first resistor R1. The first resistor R1 is connected to the sixth capacitor C6. Pin 32 of the microcontroller U1 is connected to the second resistor R2. Pins 13 and 14 of the microcontroller U1 are connected to the first capacitor C1 and the second capacitor C2, respectively. A crystal oscillator OCS is connected between the first capacitor C1 and the second capacitor C2.

3. The universal serial port dynamic scanning test circuit according to claim 1, characterized in that: The microcontroller U1 is model PIC16F877A.

4. The universal serial port dynamic scanning test circuit according to claim 1, characterized in that: It also includes a communication circuit (3), which includes a communication chip U2, a J-485 interface and an RS485 interface and a seventh capacitor C7. Pins 1, 2, 3 and 4 of the communication chip U2 are connected to the J-485 interface, pins 7 and 6 of the communication chip U2 are connected to the RS485 interface, and pins 5 and 8 of the communication chip U2 are connected to the seventh capacitor C7.

5. The universal serial port dynamic scanning test circuit according to claim 4, characterized in that: The communication chip U2 is model MAX485.

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