Implementation method and system of FPGA bare metal server

Abstract

In order to solve the problem that the existing cloud FPGA resource abstract description method only considers from the perspective of I / O external device, resulting in low abstract description level, limiting the flexibility of cloud FPGA resource management and tenant usage, the application provides an FPGA bare metal server implementation method and system, a method for making cloud FPGA resources have similar usage of general cloud computing resources as x86 cloud hosts, without the need for custom development of new cloud FPGA resource management components, simplifying the cloud FPGA resource management method, reducing the complexity of resource management; making cloud tenants directly apply, deploy and use FPGA hosts as needed, without the need for supporting application of general computing resources such as x86, which is a feasible way to improve the flexibility of cloud FPGA management and usage, and reduce the dependence on general x86 computing resources.

Description

Technical Field

[0001] This invention relates to the fields of cloud computing technology and data center architecture technology that support FPGA heterogeneous acceleration, and particularly to one such field. Background Technology

[0002] FPGA (Field-Programmable Gate Array) is a type of dedicated programmable hardware chip. Users can design and program (configure) their own dedicated hardware logic architectures to meet application needs, thereby achieving better application processing performance. Furthermore, due to the use of a more dedicated and streamlined hardware logic architecture than the traditional von Neumann computer architecture, application-specific accelerators implemented on FPGAs ensure lower power consumption, improve the energy efficiency of applications, and flexibly and efficiently overcome the "performance wall" and "energy wall" faced by existing application processing.

[0003] Microsoft first deployed FPGAs in its internal data center in 2014 to accelerate its search engine web services, prompting many internet companies to deploy FPGAs in their data centers to accelerate internet applications. As the scale of FPGA deployments in data centers continues to grow, it has become possible to offer FPGAs as a type of shareable public cloud computing resource for tenants to rent on demand. Amazon AWS first launched rentable FPGA computing instances in 2016, allowing cloud users to customize application acceleration as needed; leading domestic companies such as Alibaba Cloud, Tencent Cloud, and Huawei Cloud have followed suit, launching FPGA public cloud infrastructure and rental services.

[0004] Figure 1 This diagram illustrates the architecture of a PCIe-based FPGA cloud environment in existing technologies. In mainstream public cloud environments, cloud FPGA resources are typically abstracted and described as I / O devices connected to physical or virtual PCIExpress (PCIe) standard bus interfaces. Both the public cloud resource management platform and public cloud tenants need to deploy, access, and control cloud FPGA resources within x86 general-purpose cloud hosts via physical or virtual PCIExpress bus interfaces.

[0005] In current mainstream public cloud environments, cloud FPGA resources are still abstracted and described as I / O devices, resulting in the following problems in the management and use of cloud FPGA resources:

[0006] 1) Cloud FPGA hardware boards are managed as an adjunct resource to general-purpose resources such as x86 servers (including physical machines or virtual machines). The working and running status of cloud FPGA boards is deeply bound to the x86 server they reside on. This means that the cloud resource management platform cannot directly obtain the device status information of each FPGA board. Therefore, a dedicated FPGA device management component needs to be custom-designed within the cloud platform's resource management framework, reducing the technical versatility of FPGA resource management and increasing the development cost of the cloud FPGA resource management system.

[0007] 2) During use, tenants need to apply for a general-purpose x86 cloud host equipped with cloud FPGA hardware resources, and deploy, control, and access the cloud FPGA hardware resources on this x86 cloud host via the standard PCI-Express (PCIe) bus. Tenants cannot directly and flexibly access heterogeneous cloud FPGA acceleration resources in the same way as general cloud computing resources.

[0008] The specific methods for managing and using cloud FPGA resources include:

[0009] 1) Cloud Resource Management (Management Plane): Utilizing the PCI Express (PCIe) of a general-purpose x86 server physical machine, all visible cloud FPGA boards are discovered and managed as external I / O devices. During use, virtualization technologies of the x86 server physical machine (such as PCIe Passthrough) are used to bind several cloud FPGA hardware boards to a specific cloud tenant virtual machine. This allows the cloud tenant to access FPGA programmable logic resources within the virtual machine.

[0010] 2) FPGA Hardware Programming Configuration (Management Plane): The FPGA hardware logic resources are divided into static and dynamic areas. The static area includes memory and peripheral interfaces, including PCIe interfaces, and consists of fixed logic that remains unchanged during tenant use. The dynamic area is used to deploy user application acceleration logic and can be dynamically adjusted according to the cloud tenant's needs. During cloud FPGA hardware programming configuration, the cloud tenant requests and transmits the dynamic area's configuration file (bitstream) to the cloud FPGA administrator. The cloud administrator then uses the PCIe-based FPGA configuration interface provided by the FPGA vendor (such as Xilinx Virtual Cable, or XVC) to dynamically reconfigure the cloud FPGA's dynamic area.

[0011] 3) Tenant-Accelerated Applications (Data Plane): Cloud tenants, within an x86 virtual machine, transfer raw data to be processed to memory on the cloud FPGA board via the PCIe virtualization interface and a customized FPGA driver. Simultaneously, they access the memory-mapped I / O registers provided by the FPGA through the PCIe virtualization interface, activating the application accelerator in the FPGA's dynamic area to begin processing the raw data. After application processing is complete, the FPGA hardware logic notifies the tenant application running on the x86 virtual machine to read the computation results from memory on the cloud FPGA board via interrupts or I / O register notifications. Summary of the Invention

[0012] The purpose of this invention is to address the problem that the abstract description methods of cloud FPGA resources in the prior art only consider the perspective of I / O external devices, resulting in a low level of abstraction and limiting the flexibility of cloud FPGA resource management and tenant usage. This invention proposes a method to abstract FPGAs in the public cloud as bare metal server resources, enabling cloud FPGA resources to have similar usage as x86 cloud hosts—a method of general cloud computing resources. 1) It eliminates the need for custom development of new cloud FPGA resource management components, simplifying cloud FPGA resource management and reducing resource management complexity; 2) It allows cloud tenants to directly apply for, deploy, and use FPGA hosts on demand, without needing to apply for general computing resources such as x86, providing a feasible way to improve the flexibility of cloud FPGA management and usage, and reduce dependence on general x86 computing resources.

[0013] Specifically, this invention proposes a method for implementing an FPGA bare metal server, including:

[0014] Step 1: Construct a cloud service system consisting of a baseboard management unit and multiple bare metal servers connected to it, wherein the bare metal servers include FPGA boards;

[0015] Step 2: Build a device driver layer for the baseboard management unit to start the FPGA board, expose the device objects located in the kernel mode of the operating system of the baseboard management unit to the user interface, and encapsulate them as a service program daemon process that resides in the background of the operating system to receive and process resource control requests from the upper management software at any time.

[0016] Step 3: Using a RESTful interface, present the bare metal server to the resource management software above the substrate management unit in the form of a network URL address, and encapsulate the operation of the FPGA board into specific attributes under the URL address;

[0017] Step 4: Upload the image file of the FPGA logic to be configured to the image storage system, and power on the bare metal server through the URL address. After power-on, the bare metal server reads and executes the image file from the image storage system to complete the FPGA logic configuration. The client transmits the computing task and the required data to the bare metal server through the data network, and starts the computing components on the bare metal server through the network to start running and obtain the execution results.

[0018] The implementation method of the FPGA bare metal server, wherein the FPGA board is an FPGA board with a standard PCIe interface, includes step 4 as follows:

[0019] The image file is a bitstream image file. By modifying the management software running on the baseboard management unit, the bare metal server is powered on through the URL address. The baseboard management unit software configures the bitstream image file into the corresponding dynamic area of ​​the bare metal server through the PCIe device driver, and sets the management register between the dynamic and static areas of the FPGA of the bare metal server to the working state, so that the FPGA board of the bare metal server enters the working state.

[0020] Once the task is completed, the client powers off the bare metal server via the URL address.

[0021] The implementation method of the FPGA bare metal server, wherein the FPGA board is a private SoC-FPGA board with a custom interface design, includes step 4 as follows:

[0022] The image file is a bitstream image file. The client uploads this bitstream image file as the installation initrd to the image storage system of the cloud computing management platform.

[0023] By modifying the management software running on the substrate management unit, a URL for setting the startup mode is provided for each bare metal server managed by the substrate management unit;

[0024] The boot mode is set to NETWORK via the POST method provided by the URL; when the boot mode URL corresponding to the bare metal server managed by the baseboard management unit is set to the string "NETWORK", the baseboard management unit will modify the BIOS EEPROM corresponding to the bare metal server node.

[0025] The client powers on the bare metal server. The baseboard management unit directly controls the power management interface of the bare metal server through the GPIO device driver, so that the bare metal server powers on. After power-on, the bare metal server starts according to the BIOSEEPROM settings, automatically retrieves and runs the installation initrd.

[0026] Based on the installation initrd, the task file to be installed is written directly to the storage system on the bare metal server; after writing is complete, the boot mode is changed to local, and the bare metal server is restarted.

[0027] After the bare metal server restarts, the task file is automatically loaded from the local bare metal server's storage system; once the task is completed, the client powers off the bare metal server via the URL address.

[0028] The method for implementing an FPGA bare metal server, wherein the computing task is an accelerated application supported by the FPGA, including deep neural networks, data encryption / decryption, and data compression / decompression tasks.

[0029] This invention also proposes an implementation system for an FPGA bare metal server, comprising:

[0030] An initial module is used to build a cloud service system consisting of a baseboard management unit and multiple bare metal servers connected thereto, the bare metal servers including FPGA boards;

[0031] The startup module is used to build a device driver layer for the baseboard management unit to start the FPGA board, expose the device objects located in the kernel mode of the operating system of the baseboard management unit to the user interface, and encapsulate them as a service program daemon process that resides in the background of the operating system to receive and process resource control requests from the upper management software at any time.

[0032] The configuration module is used to present the bare metal server to the resource management software above the substrate management unit in the form of a network URL address using a RESTful interface, and to encapsulate the operation of the FPGA board into specific attributes under the URL address.

[0033] The running module is used to upload the image file to be configured for the FPGA logic to the image storage system and power on the bare metal server through the URL address. After power-on, the bare metal server reads and executes the image file from the image storage system to complete the FPGA logic configuration. The client transmits the computing task and the required data to the bare metal server through the data network and starts the computing component on the bare metal server through the network to start running and obtain the execution result.

[0034] The aforementioned FPGA bare metal server implementation system, wherein the FPGA board is an FPGA board with a standard PCIe interface, and the operating module includes:

[0035] The image file is a bitstream image file. By modifying the management software running on the baseboard management unit, the bare metal server is powered on through the URL address. The baseboard management unit software configures the bitstream image file into the corresponding dynamic area of ​​the bare metal server through the PCIe device driver, and sets the management register between the dynamic and static areas of the FPGA of the bare metal server to the working state, so that the FPGA board of the bare metal server enters the working state.

[0036] Once the task is completed, the client powers off the bare metal server via the URL address.

[0037] The aforementioned FPGA bare metal server implementation system, wherein the FPGA board is a proprietary SoC-FPGA board with a custom interface design, and the running module includes:

[0038] The image file is a bitstream image file. The client uploads this bitstream image file as the installation initrd to the image storage system of the cloud computing management platform.

[0039] By modifying the management software running on the substrate management unit, a URL for setting the startup mode is provided for each bare metal server managed by the substrate management unit;

[0040] The boot mode is set to NETWORK via the POST method provided by the URL; when the boot mode URL corresponding to the bare metal server managed by the baseboard management unit is set to the string "NETWORK", the baseboard management unit will modify the BIOS EEPROM corresponding to the bare metal server node.

[0041] The client powers on the bare metal server. The baseboard management unit directly controls the power management interface of the bare metal server through the GPIO device driver, so that the bare metal server powers on. After power-on, the bare metal server starts according to the BIOSEEPROM settings, automatically retrieves and runs the installation initrd.

[0042] Based on the installation initrd, the task file to be installed is written directly to the storage system on the bare metal server; after writing is complete, the boot mode is changed to local, and the bare metal server is restarted.

[0043] After the bare metal server restarts, the task file is automatically loaded from the local bare metal server's storage system; once the task is completed, the client powers off the bare metal server via the URL address.

[0044] The aforementioned FPGA bare metal server implementation system, wherein the computing task is an accelerated application supported by the FPGA, including deep neural networks, data encryption / decryption, and data compression / decompression tasks.

[0045] The present invention also proposes a storage medium for storing a program that executes any of the implementation methods of the FPGA bare metal server.

[0046] The present invention also proposes a client for implementing any of the FPGA bare metal server systems.

[0047] As can be seen from the above solutions, the advantages of the present invention are:

[0048] To address the issue that existing cloud FPGA resources can only serve as auxiliary resources for I / O external devices, this invention proposes a method to enhance the abstract description level of cloud FPGAs, converting heterogeneous FPGA resources into bare-metal cloud server resources with the same standardized interface as x86 general-purpose computing resources. By improving the abstraction level of heterogeneous computing resources, the following can be achieved:

[0049] 1) FPGA heterogeneous computing resources and x86 general-purpose computing resources have the same interface view. Heterogeneous FPGA resources can be managed using the existing general-purpose x86 bare metal server management interface without the need to customize and develop new cloud FPGA resource management components.

[0050] 2) FPGA heterogeneous computing resources can be used as independent cloud hosts for cloud tenants to apply for and use directly, providing services to tenants without relying on x86 general computing resources; and through simple resource management interface function expansion, users can be allowed to deploy programming. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of the existing PCIe-based FPGA cloud environment architecture;

[0052] Figure 2 An abstract diagram of existing technology cloud services;

[0053] Figure 3 Abstract block diagram of cloud service of this invention

[0054] Figure 4 This is a chassis-level abstract block diagram;

[0055] Figure 5 A diagram of the software stack architecture designed for BMC. Detailed Implementation

[0056] Current cloud FPGA resource management and tenant usage methods lack flexibility and are incompatible with the management and usage methods of general cloud computing resources (such as x86 servers). The core issue stems from the fact that existing abstraction methods for cloud FPGA resources only consider the perspective of I / O external devices, treating FPGAs as secondary computing resources of general cloud servers. This limits cloud FPGA resources to being shared, first-class computing resources in public cloud computing, just like x86 cloud servers. The reason cloud FPGAs can currently only be considered secondary computing resources of x86 general cloud servers is that they still follow the traditional usage methods of FPGAs in non-cloud computing environments, only connecting to x86 servers or PCs to complete FPGA programming, deployment, and application processing. No new abstraction methods for FPGA resources have been proposed for the new application scenarios of cloud and data centers.

[0057] When designing and building their self-developed FPGA cloud computing platform and customizing the architecture of their self-developed FPGA cloud server, the inventors discovered that the key to solving the problem of existing cloud FPGA resources only serving as auxiliary resources for I / O external devices lies in raising the abstraction level of the cloud FPGA, abstracting the FPGA as a bare-metal cloud server resource. Traditional FPGA resources, under the original model, cannot be abstracted into an independent machine (whether a virtual machine or a bare-metal server); they are merely I / O devices attached to a machine. The idea behind this invention is to directly treat the FPGA as a machine in the cloud, namely a bare-metal server (a physical machine server in the cloud), for resource management and use. FPGA bare-metal servers can reduce management overhead, allowing cloud resource administrators to manage resources using the same interface as general-purpose computing resources, eliminating the need to develop additional FPGA resource management software.

[0058] By increasing the level of abstraction of heterogeneous computing resources, it is possible to:

[0059] 1) FPGA heterogeneous computing resources and x86 general-purpose computing resources have the same interface view. Heterogeneous FPGA resources can be managed using the existing general-purpose x86 bare metal server management interface without the need to customize and develop new cloud FPGA resource management components.

[0060] 2) FPGA heterogeneous computing resources can be used as independent cloud hosts for cloud tenants to apply for and use directly, providing services to tenants without relying on x86 general computing resources; and through simple resource management interface function expansion, users can be allowed to deploy programming.

[0061] Specifically, this application includes the following key technical points:

[0062] Key Point 1: The method of abstracting cloud FPGA resources using bare metal cloud servers can achieve remote management and status monitoring of cloud FPGA resources through two levels of abstraction: host (System) and chassis (Chassis).

[0063] Key Point 2: The process and method for remotely managing FPGA bare metal servers (such as power-on and power-off operations of cloud FPGA boards, hardware programming, operating system installation, etc.), providing a standard access interface for users to remotely deploy and use cloud FPGAs;

[0064] To make the above features and effects of the present invention clearer and easier to understand, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings.

[0065] 1. Abstraction method for FPGA bare metal cloud server

[0066] First, this invention proposes a method to separate the management plane and data plane of a cloud FPGA, breaking the existing situation where the management plane and data plane of cloud FPGA resources are all tightly coupled to the PCIe physical interface, thus alleviating the absolute dependence of cloud resource management and application acceleration processes on x86 general-purpose computing resources. This method decouples cloud FPGA resource management and data interaction to different physical interfaces by physically isolating the control plane and data plane hardware interfaces, thereby providing physical support for decoupling the resource management and data interaction planes.

[0067] This invention is suitable for cloud environments such as FPGA public cloud environments (FPGA boards with standard PCIe interfaces) and FPGA clouds with custom interface designs. Specific embodiments include:

[0068] For existing FPGA public cloud environments, the standard PCIe bus (and its associated I2C bus) interface can be used as the physical interface for the control plane of the cloud FPGA, handling only FPGA resource management, configuration management, and status monitoring operations. Meanwhile, existing cloud FPGAs often have high-speed Ethernet interfaces, forming an auxiliary interconnect independent of PCIe through network switches. Therefore, this invention uses a standard Ethernet interconnect interface as the physical interface for the data plane, thereby separating the data plane physical interface from the control plane physical interface.

[0069] For FPGA cloud servers designed with custom interfaces (such as IBM cloudFPGA and the authorized patent ZL2020100190139), custom interfaces (including power management interfaces, I2C bus connections, etc.) can be used as the physical interface for the control plane of the cloud FPGA. Simultaneously, high-speed Ethernet pathways (such as IBM cloudFPGA) or on-chip interconnect interfaces of tightly coupled SoC-FPGA chips (such as Xilinx Zynq series FPGA chips) (such as patent ZL2020100190139) can be used as the data plane interface.

[0070] Building upon this, this invention proposes abstracting the general-purpose processor used for the control plane physical interface into a Baseboard Management Controller (BMC), which can be achieved by deploying general-purpose or customized BMC baseboard management software (such as the open-source OpenBMC baseboard management software). Specific implementation methods include:

[0071] For existing FPGA public cloud environments, a general-purpose x86 processor can be used as the BMC to manage cloud FPGA boards deployed within the same physical server chassis, such as... Figure 2 As shown, this invention abstracts the x86 processor into a Baseboard Management Unit (BMC), which uses PCIe to monitor the status and manage resources of different FPGA boards, and provides a RESTful API interface to the cloud resource management framework.

[0072] For FPGA cloud servers designed with custom interfaces (such as the authorized patent ZL2020100190139), the custom interface can be used to control the tightly coupled SoC-FPGA chip used on the baseboard as the BMC to manage all cloud FPGA board nodes within the FPGA cloud server.

[0073] Secondly, based on the aforementioned separation of the control plane and BMC abstraction, this invention further proposes a method for performing a cloud FPGA bare metal server abstraction description of the cloud FPGA physical boards managed by the BMC in the baseboard management software running in the BMC, specifically including:

[0074] System-level abstraction: Describes the basic attributes of each independently running cloud FPGA bare-metal server host, including processing unit information, memory status, power status / operation, and startup method. The specific abstraction methods for different types of cloud FPGA chips and board types are as follows:

[0075] 1. For the simple FPGA chips and boards used in the existing FPGA public cloud environment, different PCIe bus device numbers visible to the BMC can be used to distinguish cloud FPGA bare metal servers.

[0076] The challenge of abstracting bare-metal servers using only FPGA chips and boards lies in representing the programming configuration of FPGA hardware resources through power states. Powering on the bare-metal server host signifies dynamically reconfigurable programming of the FPGA's dynamic area via the BMC host's PCIe interface, and enabling the management interface between the FPGA's dynamic and static areas (such as Xilinx PartialReconfiguration Decoupler). Powering off the bare-metal server host signifies disabling the management interface between the FPGA's dynamic and static areas via the BMC host's PCIe interface, thus resetting the dynamic area and ceasing application acceleration processing.

[0077] 2. For FPGA cloud servers designed with custom interfaces (such as the authorized patent ZL2020100190139), BMC can utilize custom physical interfaces to differentiate and manage the SoC-FPGA board nodes within the cloud server. Specifically, based on the custom management interface, power-on / off management of the SoC-FPGA bare metal server can be achieved through the GPIO control software in the BMC substrate management software, such as... Figure 3 As shown.

[0078] The challenge of abstracting a SoC-FPGA board into a bare-metal server lies in how to utilize the BMC board management software for dynamically reconfigurable configuration of the FPGA's dynamic area. This invention, through the EEPROM read / write driver and application interface of the BMC board management software, allows the SoC-FPGA bare-metal server to be configured for network boot. During boot, the installation agent operating system image running on the SoC-FPGA, in conjunction with the installation process provided by the OpenStack Ironic resource management framework, performs partial reconfigurable configuration of the FPGA's dynamic area. After user completion, the SoC-FPGA can be powered down directly through the BMC power-on / off management interface, invalidating the current FPGA dynamic area configuration. The specific process of dynamically reconfiguring the FPGA dynamic area includes:

[0079] 1. Cloud resource management frameworks (such as OpenStack) can remotely control a SoC-FPGA board (i.e., a bare metal server node) through the access interface provided by the BMC baseboard management software.

[0080] 2. The cloud resource management framework sets the SoC-FPGA board's boot status to network boot through the aforementioned access interface.

[0081] 3. After the SoC-FPGA board boots up, the SoC portion loads and runs the installation agent operating system image from the network. Once running, it communicates with the cloud resource management framework via the network.

[0082] 4. The cloud resource management framework transmits dynamic partition bitstream files to the installed operating system.

[0083] 5. After the installed operating system receives the complete bitstream file, it writes the dynamic area bitstream into the FPGA dynamic area through the SoC-FPGA configuration interface (such as the Xilinx MCAP interface) driver, thus enabling complete reconfigurable configuration.

[0084] Chassis-level abstraction: such as Figure 4 As shown, this describes the operating status of the cloud FPGA bare metal server hardware boards, including indicators such as server voltage, current, power, power management, temperature, and fan speed, and manages and monitors the sensor hardware or board-level modules that monitor these operating statuses. For existing FPGA public clouds or custom FPGA cloud servers, the BMC can control and manage sensor or hardware circuit modules through the I2C hardware and software access interface.

[0085] 2. Cloud Management Process for FPGA Bare Metal Servers. To achieve cloud management of FPGA bare metal server resources, it is necessary to design, as shown in this invention, on the abstract substrate management unit (BMC). Figure 5 The software stack architecture shown specifically includes:

[0086] Linux device driver layer: Software running on the Baseboard Management Unit (BMC). The BMC itself is unaware that it is managing an FPGA board node and therefore does not perceive the existence of the FPGA. The Linux device driver layer is used to manage the key hardware components for the startup and operation of the cloud FPGA hardware board, specifically including the FPGA board's power management module (PCIe device driver or GPIO device driver), the FPGA board's temperature / electrical sensors and other hardware resources (I2C device driver), the FPGA boot BIOS storage medium (I2CEEPROM device driver), and the FPGA hardware logic programming configuration interface (GPIO device driver), etc.

[0087] User-mode device interface layer: Through the Linux sysfs file system or dedicated device access library functions (such as libgpiod), device objects located in the BMC operating system kernel mode are exposed to the user interface for use by upper-layer applications.

[0088] Service program layer: The peripheral access interfaces exposed by the user-mode device interface layer are further encapsulated into service program daemons that reside in the background of the BMC operating system, and receive and process resource control requests from the upper-layer management software at any time.

[0089] Bare Metal Server Management Interface Layer: Utilizing the management software running on the Baseboard Management Unit (BMC), the management and control RESTful interface provided by the cloud resource management framework (such as OpenStack) presents the bare metal server to the resource management software above the BMC via a network URL address (e.g., https: / / IP address / Systems / bare metal server ID). Key operations such as FPGA board power-on and power-off are encapsulated as specific attributes under the URL address (e.g., https: / / IP address / Systems / bare metal server ID / Actions / ComputerSystem.Reset). Attribute values ​​are modified through the POST method provided by the RESTful interface, thereby achieving control over the bare metal server. POST is an API of the RESTful interface used for updating resource attributes or creating new resources.

[0090] Building upon this, and combining the OpenStack Ironic bare metal server deployment interface, specific hardware and software deployment and installation interfaces and processes are implemented for different types of FPGA clouds:

[0091] For bare metal servers using simple FPGA chips and boards in existing FPGA public cloud environments, the hardware programming configuration startup process is as follows:

[0092] 1. Users upload the bitstream image file to be configured to the OpenStack image storage system through the OpenStack management interface. The bitstream file is responsible for FPGA logic configuration. Specific computing tasks can be performed via the data network, where users transmit the raw data required for the computing task to the FPGA, and the computing components on the FPGA are started running over the network. Runnable computing tasks include various accelerated applications, such as deep neural networks, data encryption / decryption, data compression / decompression, and other FPGA-supported accelerated applications.

[0093] 2. Modify the management software running on the BMC (x86 server physical CPU) to provide a URL for boot mode settings (https: / / IP address / Systems / bare metal server ID number / Actions / BootSource) for each FPGA bare metal server managed by the BMC.

[0094] The OpenStack Ironic bare metal server management framework can set the boot mode using the POST method provided by the URL mentioned above. The default setting value is the string "BIT". When the boot mode URL corresponding to a FPGA bare metal server managed by the BMC is set to the string "BIT", the BMC will actively send an access request to the OpenStack image storage system to store the bitstream configuration file uploaded in step 1 to a fixed path in the BMC file system.

[0095] 3. Users can power on the FPGA bare metal server whose boot mode has been modified in step 2 using the OpenStack Ironic bare metal server management framework (by performing a POST operation on https: / / IP address / Systems / bare metal server ID / Actions / ComputerSystem.Reset and writing the string "On"). At this time, the BMC software will obtain the bitstream file acquired in step 2, configure it in the corresponding dynamic area of ​​the FPGA bare metal server through the PCIe device driver, and set the management register between the FPGA dynamic area and static area to the working state, enabling the FPGA to enter the normal working state for application acceleration.

[0096] 4. After the application acceleration task stops, the user can perform a power-off operation through the OpenStack Ironic bare metal server management framework (by performing a POST operation on https: / / IP address / Systems / bare metal server ID / Actions / ComputerSystem.Reset and writing the string "ForceOff"). After receiving the power-off command, the BMC sets the management register between the FPGA's dynamic and static areas to the off state through the PCIe interface, thereby resetting the dynamic area and ceasing application acceleration processing.

[0097] For FPGA cloud servers designed with custom interfaces (such as the authorized patent ZL2020100190139), the process for deploying and booting the remote operating system software and configuring FPGA hardware for bare metal servers with tightly coupled SoC-FPGA chips and boards is as follows:

[0098] 1. Users upload the operating system image file to be deployed to the OpenStack image storage system through the OpenStack management interface; at the same time, they configure the OpenStackIronic network installation service image (installation initrd).

[0099] 2. Modify the management software running on the BMC chip on the customized cloud server motherboard to provide a URL for boot mode settings (https: / / IP address / Systems / bare metal server ID number / Actions / BootSource) for each FPGA bare metal server managed by the BMC.

[0100] The OpenStack Ironic bare metal server management framework can set the boot mode to the string "NETWORK" (i.e., network boot) via the POST method provided in the URL mentioned above. When the boot mode URL for a specific FPGA bare metal server managed by the BMC is set to the string "NETWORK", the BMC will modify the BIOSEEPROM of the corresponding SoC-FPGA bare metal server node.

[0101] 3. Users can power on the FPGA bare metal server (with the boot mode modified in step 2) via the OpenStackIronic bare metal server management framework controller (Conductor) by performing a POST operation on https: / / IP address / Systems / bare metal server ID / Actions / ComputerSystem.Reset and writing the string "On". At this time, the BMC will directly control the power management interface of the SoC-FPGA bare metal server through the GPIO device driver, powering on the SoC-FPGA bare metal server. After power-on, the SoC-FPGA bare metal server will boot from the network according to the boot mode set in the BIOSEEPROM in step 2, automatically retrieve and start the installation initrd deployed in step 1, and automatically connect to the OpenStackIronic controller after startup.

[0102] 4. The OpenStackIronic controller directly controls the installation initrd running on the SoC-FPGA bare metal server. It remotely copies the operating system image to be installed directly to the storage system (such as an NVMe SSD) on the SoC-FPGA bare metal server. After the write operation is complete, the user can change the boot mode (https: / / IP address / Systems / bare metal server ID / Actions / BootSource) to "LOCAL" through the OpenStackIronic controller and restart the bare metal server (by performing a POST operation on https: / / IP address / Systems / bare metal server ID / Actions / ComputerSystem.Reset, writing the string "ForceReset").

[0103] 5. After the bare metal server restarts, it will automatically load the operating system deployed and installed in the storage system in step 4 and start network services. Tenants can directly access the rented and deployed bare metal server via the network.

[0104] 6. During tenant usage, tightly coupled FPGA hardware logic can be dynamically configured within the operating system running on the bare metal server SoC.

[0105] 7. Users can perform power-down operations through the OpenStack Ironic bare metal server management framework (by performing a POST operation on https: / / IP address / Systems / bare metal server ID / Actions / ComputerSystem.Reset and writing the string "ForceOff"). After receiving the power-down command, the BMC will directly control the power management interface of the SoC-FPGA bare metal server through the GPIO device driver, thereby powering down the SoC-FPGA bare metal server.

[0106] The following are system embodiments corresponding to the above method embodiments. This embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0107] This invention also proposes an implementation system for an FPGA bare metal server, comprising:

[0108] An initial module is used to build a cloud service system consisting of a baseboard management unit and multiple bare metal servers connected thereto, the bare metal servers including FPGA boards;

[0109] The startup module is used to build a device driver layer for the baseboard management unit to start the FPGA board, expose the device objects located in the kernel mode of the operating system of the baseboard management unit to the user interface, and encapsulate them as a service program daemon process that resides in the background of the operating system to receive and process resource control requests from the upper management software at any time.

[0110] The configuration module is used to present the bare metal server to the resource management software above the substrate management unit in the form of a network URL address using a RESTful interface, and to encapsulate the operation of the FPGA board into specific attributes under the URL address.

[0111] The running module is used to upload the image file to be configured for the FPGA logic to the image storage system and power on the bare metal server through the URL address. After power-on, the bare metal server reads and executes the image file from the image storage system to complete the FPGA logic configuration. The client transmits the computing task and the required data to the bare metal server through the data network and starts the computing component on the bare metal server through the network to start running and obtain the execution result.

[0112] The aforementioned FPGA bare metal server implementation system, wherein the FPGA board is an FPGA board with a standard PCIe interface, and the operating module includes:

[0113] The image file is a bitstream image file. By modifying the management software running on the baseboard management unit, the bare metal server is powered on through the URL address. The baseboard management unit software configures the bitstream image file into the corresponding dynamic area of ​​the bare metal server through the PCIe device driver, and sets the management register between the dynamic and static areas of the FPGA of the bare metal server to the working state, so that the FPGA board of the bare metal server enters the working state.

[0114] Once the task is completed, the client powers off the bare metal server via the URL address.

[0115] The aforementioned FPGA bare metal server implementation system, wherein the FPGA board is a proprietary SoC-FPGA board with a custom interface design, and the running module includes:

[0116] The image file is a bitstream image file. The client uploads this bitstream image file as the installation initrd to the image storage system of the cloud computing management platform.

[0117] By modifying the management software running on the substrate management unit, a URL for setting the startup mode is provided for each bare metal server managed by the substrate management unit;

[0118] The boot mode is set to NETWORK via the POST method provided by the URL; when the boot mode URL corresponding to the bare metal server managed by the baseboard management unit is set to the string "NETWORK", the baseboard management unit will modify the BIOS EEPROM corresponding to the bare metal server node.

[0119] The client powers on the bare metal server. The baseboard management unit directly controls the power management interface of the bare metal server through the GPIO device driver, so that the bare metal server powers on. After power-on, the bare metal server starts according to the BIOSEEPROM settings, automatically retrieves and runs the installation initrd.

[0120] Based on the installation initrd, the task file to be installed is written directly to the storage system on the bare metal server; after writing is complete, the boot mode is changed to local, and the bare metal server is restarted.

[0121] After the bare metal server restarts, the task file is automatically loaded from the local bare metal server's storage system; once the task is completed, the client powers off the bare metal server via the URL address.

[0122] The aforementioned FPGA bare metal server implementation system, wherein the computing task is an accelerated application supported by the FPGA, including deep neural networks, data encryption / decryption, and data compression / decompression tasks.

[0123] The present invention also proposes a storage medium for storing a program that executes any of the implementation methods of the FPGA bare metal server.

[0124] The present invention also proposes a client for implementing any of the FPGA bare metal server systems.

Claims

1. A method for implementing an FPGA bare metal server, characterized in that, include: Step 1: Construct a cloud service system consisting of a baseboard management unit and multiple bare metal servers connected to it, wherein the bare metal servers include FPGA boards; Step 2: Build a device driver layer for the baseboard management unit to start the FPGA board, expose the device objects located in the kernel mode of the baseboard management unit's operating system to the user interface, and encapsulate them as a service program daemon process that resides in the background of the operating system to receive and process resource control requests from the upper-level management software at any time. Step 3: Using a RESTful interface, present the bare metal server to the resource management software above the substrate management unit in the form of a network URL address, and encapsulate the operation of the FPGA board into specific attributes under the URL address; Step 4: Upload the image file of the FPGA logic to be configured to the image storage system, and power on the bare metal server through the URL address. After power-on, the bare metal server reads and executes the image file from the image storage system to complete the FPGA logic configuration. The client transmits the computing task and the required data to the bare metal server through the data network, and starts the computing components on the bare metal server through the network to start running and obtain the execution results.

2. The implementation method of the FPGA bare metal server as described in claim 1, characterized in that, The FPGA board is an FPGA board with a standard PCIe interface. Step 4 includes: The image file is a bitstream image file. By modifying the management software running on the baseboard management unit, the bare metal server is powered on through the URL address. The baseboard management unit software configures the bitstream image file into the corresponding dynamic area of ​​the bare metal server through the PCIe device driver, and sets the management register between the dynamic and static areas of the FPGA of the bare metal server to the working state, so that the FPGA board of the bare metal server enters the working state. Once the task is completed, the client powers off the bare metal server via the URL address.

3. The implementation method of the FPGA bare metal server as described in claim 1, characterized in that, This FPGA board is a proprietary SoC-FPGA board with a custom interface design. Step 4 includes: The image file is a bitstream image file. The client uploads this bitstream image file as the installation initrd to the image storage system of the cloud computing management platform. By modifying the management software running on the substrate management unit, a URL for setting the startup mode is provided for each bare metal server managed by the substrate management unit; The boot mode is set to NETWORK via the POST method provided by the URL; when the boot mode URL corresponding to the bare metal server managed by the baseboard management unit is set to the string "NETWORK", the baseboard management unit will modify the BIOS EEPROM corresponding to the bare metal server node. The client powers on the bare metal server. The baseboard management unit directly controls the power management interface of the bare metal server through the GPIO device driver, so that the bare metal server powers on. After power-on, the bare metal server starts according to the BIOS EEPROM settings, automatically retrieves and runs the installation initrd. Based on the installation initrd, the task files to be installed are written directly to the storage system on the bare metal server; after writing is complete, the boot mode is changed to local, and the bare metal server is restarted. After the bare metal server restarts, the task file is automatically loaded from the local bare metal server's storage system; once the task is completed, the client powers off the bare metal server via the URL address.

4. The implementation method of the FPGA bare metal server as described in claim 1, characterized in that, This computational task enables FPGA-supported accelerated applications, including deep neural networks, data encryption / decryption, and data compression / decompression tasks.

5. An implementation system for an FPGA bare-metal server, characterized in that, include: An initial module is used to build a cloud service system consisting of a baseboard management unit and multiple bare metal servers connected thereto, the bare metal servers including FPGA boards; The startup module is used to build a device driver layer for the baseboard management unit to start the FPGA board, expose the device objects located in the kernel mode of the baseboard management unit's operating system to the user interface, and encapsulate them as a service program daemon process that resides in the background of the operating system to receive and process resource control requests from the upper-level management software at any time. The configuration module is used to present the bare metal server to the resource management software above the substrate management unit in the form of a network URL address using a RESTful interface, and to encapsulate the operation of the FPGA board into specific attributes under the URL address. The running module is used to upload the image file to be configured for the FPGA logic to the image storage system and power on the bare metal server through the URL address. After power-on, the bare metal server reads and executes the image file from the image storage system to complete the FPGA logic configuration. The client transmits the computing task and the required data to the bare metal server through the data network and starts the computing component on the bare metal server through the network to start running and obtain the execution result.

6. The implementation system of the FPGA bare metal server as described in claim 5, characterized in that, This FPGA board is an FPGA board with a standard PCIe interface, and the operating module includes: The image file is a bitstream image file. By modifying the management software running on the baseboard management unit, the bare metal server is powered on through the URL address. The baseboard management unit software configures the bitstream image file into the corresponding dynamic area of ​​the bare metal server through the PCIe device driver, and sets the management register between the dynamic and static areas of the FPGA of the bare metal server to the working state, so that the FPGA board of the bare metal server enters the working state. Once the task is completed, the client powers off the bare metal server via the URL address.

7. The implementation system of the FPGA bare metal server as described in claim 5, characterized in that, This FPGA board is a proprietary SoC-FPGA board with a custom interface design. The running module includes: The image file is a bitstream image file. The client uploads this bitstream image file as the installation initrd to the image storage system of the cloud computing management platform. By modifying the management software running on the substrate management unit, a URL for setting the startup mode is provided for each bare metal server managed by the substrate management unit; The boot mode is set to NETWORK via the POST method provided by the URL; when the boot mode URL corresponding to the bare metal server managed by the baseboard management unit is set to the string "NETWORK", the baseboard management unit will modify the BIOS EEPROM corresponding to the bare metal server node. The client powers on the bare metal server. The baseboard management unit directly controls the power management interface of the bare metal server through the GPIO device driver, so that the bare metal server powers on. After power-on, the bare metal server starts according to the BIOS EEPROM settings, automatically retrieves and runs the installation initrd. Based on the installation initrd, the task files to be installed are written directly to the storage system on the bare metal server; after writing is complete, the boot mode is changed to local, and the bare metal server is restarted. After the bare metal server restarts, the task file is automatically loaded from the local bare metal server's storage system; once the task is completed, the client powers off the bare metal server via the URL address.

8. The implementation system of the FPGA bare metal server as described in claim 5, characterized in that, This computational task enables FPGA-supported accelerated applications, including deep neural networks, data encryption / decryption, and data compression / decompression tasks.

9. A storage medium for storing a program that executes a method of implementing an FPGA bare metal server as described in any one of claims 1 to 4.

10. A client for implementing the FPGA bare metal server of any one of claims 5 to 8.

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