Integrated circuit optimization system and method based on multi-phase level sensitive latches

Abstract

The invention relates to an integrated circuit optimization system and method, which method comprises converting edge-triggered sequential elements (e.g. flip-flops) into equivalent modules containing multi-phase level-sensitive latches, followed by applying certain level-sensitive latch-based optimization techniques, such as level-sensitive latch retiming, and design-for-worst-case based on predicting or detecting signal transmission through level-sensitive latches. The invention also relates to an integrated circuit comprising: edge-triggered sequential elements; multi-phase level-sensitive latches deployed on a timing critical path; and a network of logic wires between the multi-phase level-sensitive latches, the input signals of the network of logic wires coming from a first set of phase-identical or similar level-sensitive latches, the output signals of the network of logic wires going to a second set of phase-identical or similar level-sensitive latches, the first set of level-sensitive latches and the second set of level-sensitive latches being different in phase.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 201910917462.2, filed on September 26, 2019, entitled "Integrated Circuit Optimization System and Method Based on Multiphase Level Sensitive Latch".

[0002] Related applications

[0003] This application is based on U.S. Provisional Patent Application US62 / 743,248, filed October 9, 2018, entitled "Integrated Circuit Optimization System and Method Based on Transformation from Edge-Triggered Sequential Elements to Level-Sensitive Latches," and U.S. Provisional Patent Application US62 / 833,127, filed April 12, 2019, entitled "Integrated Circuit Optimization System and Method Based on Transformation from Edge-Triggered Sequential Elements to Level-Sensitive Latches." The entire contents of these applications are incorporated herein by reference. Technical Field

[0004] This invention relates to integrated circuit design optimization technology. Background Technology

[0005] Synchronous sequential circuits consist of sequential elements and combinational logic networks. Combinational logic forms logic levels between sequential elements. Sequential elements are typically clock-edge triggered flip-flops. The logic expression is first synthesized into a network of logic gates from a cell library, and then optimization techniques such as logic optimization or register retiring can be used. Logic optimization finds equivalent implementations of the same logic through logic transformations while achieving specific design metrics such as timing performance. Register or latch retiring better balances the propagation paths of critical signals in two adjacent logic levels by moving a clock-edge triggered flip-flop or level-sensitive latch within the circuit structure.

[0006] Traditional flip-flop-based integrated circuits require the data signal to arrive at the flip-flop before the clock signal. Traditional static timing analysis verifies this by checking if the worst-case signal propagation delay in the combinational logic network is less than the clock cycle (details include setup time, hold time, clock drift, uncertainty, etc.). Level-sensitive latches have different timing requirements than flip-flops; for example, level-sensitive latches allow the data signal to arrive later than the latch enable signal.

[0007] In static timing analysis, time borrowing occurs when the data signal arrives at the level-sensitive latch later than the latch enable signal. This is not a timing error because the latch is transparently enable signal transmission. The borrowed time, or the time the data signal arrives later than the latch enable signal, needs to be repaid in subsequent signal transmissions, which must be completed in the next clock cycle in subsequent logic stages. Specifically, static timing analysis verifies this situation by applying the same timing requirements to level-sensitive latches as to flip-flops, i.e., the signal transmission path delay must be less than the clock cycle, but the time borrowed by a level-sensitive latch must be included in the delay of the signal transmission path originating from that latch. Related technology can be found in Mau-Chung Chang's US Patent 2009 / 0055786 A1, filed August 5, 2008, entitled "Method for Verifying Timing of a Circuit".

[0008] Advances in integrated circuit manufacturing processes have led to significant increases in perturbations in manufacturing processes, power supply voltage, on-chip temperature, and other parameters. Therefore, even if the normal value of a parameter decreases with process advancements, its best and worst values ​​do not decrease proportionally. This impacts integrated circuit performance because traditional synchronous sequential circuit design methods require that logic operations within a logic level be completed within one clock cycle, including worst-case scenarios. This requirement also applies to level-sensitive latches, taking into account borrowing and compensation times.

[0009] Another approach to integrated circuit design is to design better than worst-case to achieve performance improvements, reduced power consumption, and / or smaller area. For example, logic operations may not be required to complete within a single clock cycle. In some applications, such as image and speech processing, a certain error rate is acceptable, so approximations can be used to improve power consumption, performance, and area. A simple approximation technique is overclocking, which allows delays in certain critical signal transmission paths to exceed a clock cycle. If the resulting error rate is acceptable, overclocking can be employed. In other applications, the system ensures a zero error rate by detecting and correcting errors or predicting and preventing errors. Specific technologies include the use of error detection codes or error correction codes in integrated circuits, or error detection timing designs such as Razor. For Razor designs, see U.S. Patent 10 / 392,382, filed March 20, 2003, entitled "Error Detection and Recovery Within Processing Stages of an Integrated Circuit" by Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, and Trevor Nigel Mudge, and U.S. Patent 14 / 702,426, filed May 1, 2015, entitled "Timing Violation Resilient Asynchronous Template" by Peter A. Beerel, Melvin Breuer, Benmao Cheng, and Dylan Hand.

[0010] A practical timing error prediction scheme can be found in the article “Application-Specific Cross-Layer OptimizationBased on Predictive Variable-Latency VLSI Design” by V. De, ABKahng, T. Karnik, B. Liu, M. Maleki and L. Wang published in ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Cross-Layer System Design and Regular Papers, 12(3), September 2015, pp. 21:1-21:19. Summary of the Invention

[0011] This invention relates to an integrated circuit optimization system and method. The method includes converting edge-triggered sequential elements (e.g., flip-flops) into equivalent modules containing multiphase level-sensitive latches, and then employing level-sensitive latch-based optimization techniques, such as level-sensitive latch retiming and better-than-worst-case design based on predicting or detecting signal transmission through the level-sensitive latches. The optimized integrated circuit includes mutually separated multiphase level-sensitive latches, edge-triggered sequential elements, and combinational logic networks.

[0012] In one embodiment of the present invention, the timing performance improvement of the integrated circuit comes from the retiming of level-sensitive latches. In other words, moving a level-sensitive latch at the beginning or end of a timing-critical signal transmission path in the circuit structure can reduce signal transmission path delay. In comparison, existing register retiming techniques, or techniques for moving clock-edge triggered flip-flops in the circuit structure, can balance the signal transmission path delay at the input and output of the flip-flop, but they only achieve limited timing performance improvement. Converting the flip-flop into an equivalent module containing master-slave latches provides additional degrees of freedom for circuit optimization. Moving one level-sensitive latch in the circuit structure can reduce the delay of the signal transmission path connected to it without affecting the signal transmission path connected to the other level-sensitive latch.

[0013] In one embodiment of the invention, the time when a data signal arrives at a level-sensitive latch is compared with the time when a latch-off signal arrives, the latch-off signal being determined by the signal transmission path. This timing requirement differs from traditional time-borrowing-based timing requirements and provides additional flexibility for integrated circuit performance optimization.

[0014] Level-sensitive latch retiming causes many signal transmission paths to pass through the level-sensitive latch, a low-probability event. Ignoring these low-probability events in integrated circuit optimization can improve power consumption, performance, and area; predicting or detecting and handling these low-probability events ensures correct system function. In one embodiment of the invention, predicting signal transmission through the critical path is based on observing certain edge inputs of that path. In another embodiment, timing errors are detected by comparing the input and output of the level-sensitive latch when it is closed along with the latch preceding it.

[0015] According to a first aspect of the present invention, an optimization method for an integrated circuit including edge-triggered timing elements is provided, the optimization method comprising the steps of: a. converting the edge-triggered timing elements into an equivalent module including a multiphase level-sensitive latch; b. moving one of the level-sensitive latches in the circuit structure of the integrated circuit.

[0016] According to a second aspect of the invention, an apparatus is provided comprising a finite state machine that receives signals from a plurality of combinational logic levels and outputs signals to indicate signal transmission through a timing-critical path passing through a level-sensitive latch.

[0017] According to a third aspect of the invention, an apparatus is provided comprising a comparator that, in an integrated circuit comprising a multiphase level-sensitive latch, compares the input-output signals of the level-sensitive latch when the level-sensitive latch and all previous-stage level-sensitive latches are opaque.

[0018] According to a fourth aspect of the invention, a computer-readable medium is provided for storing computer instructions that, when executed by a computer, implement the method according to a first aspect of the invention. Attached Figure Description

[0019] The advantages of the present invention are demonstrated in the following detailed description of the embodiments and accompanying drawings.

[0020] Figure 1 A schematic diagram of a traditional trigger retiming technique is shown.

[0021] Figure 2 A schematic diagram of a traditional level-sensitive latch retiming technique is shown.

[0022] Figure 3 A schematic diagram of converting an edge-triggered flip-flop into an equivalent module according to an embodiment of the present invention is shown, the equivalent module comprising two level-sensitive latches that are transparent at two opposite clock phases.

[0023] Figure 4 A schematic diagram of an example of an integrated circuit optimization method according to an embodiment of the present invention is shown.

[0024] Figure 5 A schematic diagram of another example of an integrated circuit optimization method according to an embodiment of the present invention is shown.

[0025] Figure 6 A schematic diagram of yet another example of an integrated circuit optimization method according to an embodiment of the present invention is shown.

[0026] Figure 7 A schematic diagram illustrating yet another example of an integrated circuit optimization method according to an embodiment of the present invention is shown.

[0027] Figure 8 A schematic diagram of existing static timing analysis methods for synchronous digital systems is shown.

[0028] Figure 9A schematic diagram of the time borrowing method in existing static time series analysis is shown.

[0029] Figure 10 A schematic diagram illustrating timing constraints for an integrated circuit containing a biphase level-sensitive latch, according to an embodiment of the present invention, is shown.

[0030] Figure 11 A schematic diagram of timing constraints for an integrated circuit containing a four-phase level-sensitive latch, according to an embodiment of the present invention, is shown.

[0031] Figure 12 A block diagram of a timing error prediction device in the form of a finite state machine according to an embodiment of the present invention is shown.

[0032] Figure 13 A block diagram of a timing error detection apparatus according to an embodiment of the present invention is shown.

[0033] Figure 14 A flowchart of an integrated circuit optimization method according to an embodiment of the present invention is shown.

[0034] This invention may have various modifications and different forms, and certain specific embodiments are illustrated and described in detail with reference to the accompanying drawings. The drawings may not be to scale. It should be understood that the drawings and detailed description are not intended to limit the invention to certain specific forms, but rather to cover all modifications, equivalents, and different forms within the spirit and scope of the invention as defined by the claims. Detailed Implementation

[0035] It should be understood that the present invention is not limited to any particular device or system, and devices or systems can certainly differ from one another. It should also be understood that the terminology used herein is merely for describing particular embodiments and is not intended to limit the invention.

[0036] Figure 1 A schematic diagram of a traditional trigger retiming technique is shown. Timing performance improvements come from better balancing the delays of signal propagation paths terminating at and beginning at a trigger. Similarly, Figure 2 This diagram illustrates a traditional level-sensitive latch retiming technique. Timing performance improvements come from better balancing the delays of signal transmission paths terminating at and beginning at a level-sensitive latch.

[0037] Figure 3 A schematic diagram illustrating the conversion of an edge-triggered sequential element into an equivalent module containing a multiphase level-sensitive latch according to an embodiment of the present invention is shown. Specifically, a D flip-flop is converted into a pair of master-slave latches that are transparent in two opposite clock phases. More complex edge-triggered sequential elements can be similarly converted into an equivalent module containing a multiphase level-sensitive latch.

[0038] Figure 4 A schematic diagram illustrating an example of an integrated circuit optimization method according to an embodiment of the present invention is shown. The method includes performing a timing element shift and moving a latch from the input of a NAND gate to the output of that gate. Specifically, in Figure 4 In the method shown, two edge-triggered flip-flops are converted into level-sensitive latches. Then, the two level-sensitive latches are removed from the input of the NAND gate, and a new level-sensitive latch is inserted at the output of the NAND gate. At the same time, another level-sensitive latch is inserted at the fan-out node of the NAND gate's fan-in cone, which is the input of the NOT gate.

[0039] Figure 5 A schematic diagram illustrating another example of an integrated circuit optimization method according to an embodiment of the present invention is shown. This method may include inserting a level-sensitive latch in a timing-critical path, performing timing element conversion and level-sensitive latch removal at the fan-in input of the inserted latch a, and inserting a latch at the output of the fan-in cone. These steps can be used after converting an edge-triggered timing element to a level-sensitive latch. Specifically, in Figure 5 In the method shown, firstly, the timing-critical path that needs to be shortened is identified, for example, for setup time constraints. Secondly, the flip-flops at the beginning of this path are converted into equivalent modules containing level-sensitive latches. Thirdly, the level-sensitive latches are moved from the beginning of the critical path to a new location. The new location (1) satisfies the timing constraints and (2) minimizes costs such as chip area and / or power consumption. Next, the gate-level network is traversed from the newly inserted latch (a) to the initial input to obtain the latch's fan-in cone. The input of this fan-in cone is a set of timing elements, where each edge-triggered timing element needs to be converted into an equivalent module containing level-sensitive latches (including level-sensitive latches b and c). Next, each level-sensitive latch at the input of the fan-in cone is removed, while a level-sensitive latch (including d, e, and f) is inserted at each fan-out node of the fan-in cone, such that no signal transmission path passes consecutively through two simultaneously transparent level-sensitive latches, even after the edge-triggered timing elements have been converted into equivalent modules containing level-sensitive latches.

[0040] Figure 6 A schematic diagram illustrating yet another example of an integrated circuit optimization method according to an embodiment of the present invention is shown. The method may include performing timing element switching and moving a latch from the output of a NAND gate to the input of that gate. Specifically, in Figure 6In the method shown, two flip-flops are converted into level-sensitive latches, and then the two level-sensitive latches are removed from the fan-out cone output of the NAND gate. Two new level-sensitive latches are inserted into the input of the NAND gate, and another level-sensitive latch is inserted into a fan-in node of the NAND gate's fan-out cone, which is also an input of the AND gate.

[0041] Figure 7 A schematic diagram illustrating another example of an integrated circuit optimization method according to an embodiment of the present invention is shown. The method may include inserting a level-sensitive latch in a timing-critical path, performing timing element conversion and level-sensitive latch removal at the fan-out cone output of the inserted latch a, and inserting a latch at the input of the fan-out cone. These steps can be used after converting an edge-triggered timing element into a level-sensitive latch. Specifically, in Figure 7 In the method shown, firstly, the timing-critical path that needs to be shortened is identified, for example, for setup time constraints. Secondly, the trigger at the end of the path is converted into an equivalent module containing a level-sensitive latch. Thirdly, the level-sensitive latch is moved from the end of the critical path to a new location. The new location (1) satisfies the timing constraints and (2) minimizes costs such as chip area and / or power consumption. Next, the gate network is traversed from the newly inserted latch (a) to the initial output to obtain the fan-out cone of the latch. The output of the fan-out cone is a set of timing elements, where each edge-triggered timing element needs to be converted into an equivalent module containing a level-sensitive latch (including level-sensitive latches b and c). Next, each level-sensitive latch at the output of the fan-out cone is removed, while a level-sensitive latch (including d) is inserted at each fan-in node of the fan-out cone, such that no signal transmission path passes consecutively through two simultaneously transparent level-sensitive latches, even after an edge-triggered timing element has been converted into an equivalent module containing a level-sensitive latch.

[0042] Integrated circuits are subject to timing constraints. Figure 8 A schematic diagram of existing static timing analysis methods for synchronous digital systems is shown. Figure 8 In this method, the signal arrival time is constrained by the signal setup time and signal hold time. Additionally, in... Figure 8 In the example, the trigger is triggered on the rising clock edge. Specifically, Figure 8 The signal setup and hold time constraints in a traditional flip-flop-based synchronous sequential circuit are given, where d is the signal propagation delay in a logic level, and T... c It is the clock cycle, T hold It is a signal hold time constraint, T setupIt is a signal setup time constraint. In this traditional static timing analysis method, the logic gate and interconnect delays accumulate in each logic level, and the resulting signal transmission path delay is compared with the signal setup and hold time constraints of the receiving flip-flops.

[0043] Figure 9 A schematic diagram of the time borrowing method in existing static time series analysis is shown. Figure 9 In this method, the arrival time of the signal at the level-sensitive latch is adjusted by a borrow time. The borrow time is the portion of the signal arrival time that exceeds the arrival time of the latch's enable clock edge. The latch's setup and hold times are relative to the latch's disable clock edge. The maximum borrow time is derived from the setup time constraint, and any borrow time needs to be compensated for in the next logic level. In the diagram, the level-sensitive latch is transparent when the clock signal is high, and the clock signal is high for half a clock cycle. Specifically, Figure 9 The setup and hold times of an integrated circuit based on single-phase level-sensitive latches are given, where signal transmission passes through a series of level-sensitive latches controlled by a single-phase clock signal. d is the signal transmission delay in the logic level, and T... c It is the clock cycle, T hold It is a signal hold time constraint, T setup This refers to the signal setup time constraint. In the diagram, the level-sensitive latch is transparent when the clock signal φ is high, meaning the clock signal is high for half a clock cycle. Each level-sensitive latch has setup and hold times relative to the latch enable or disable clock edge; these are the minimum times the data signal must remain stable before and after the latch enable or disable clock edge. Time borrowing occurs when the signal arrives at the data terminal of the level-sensitive latch after the latch enable or enable clock edge. The borrowed time T... borrow This is the portion of the data signal arrival time that exceeds the arrival time of the latch enable signal or the enable clock signal. The maximum borrow time is the time between the arrival time of the latch enable signal and the arrival time of the deactivation signal, or the arrival time of the enable clock edge and the arrival time of the disable clock edge, minus the setup time. Compensation time T compensate This is the borrowing time of the signal at the input of the latch transmitting the signal or the output of the previous logic stage. In traditional static timing analysis, the gate and interconnect delays in each logic stage are accumulated. The latest signal arrival time from all possible paths to the level-sensitive latch at the receiver is used to calculate the borrowing time or compensation time of the level-sensitive latch. For a signal transmission path that starts at a level-sensitive latch and terminates at an edge-triggered flip-flop, the path delay check is based on the setup and hold time of the signal arriving at the edge-triggered flip-flop. Figure 8 The same applies, but any compensation time for the start-end level-sensitive latch needs to be taken into account in the signal transmission path delay.

[0044] In multiphase latch-based integrated circuits, signal transmission occurs through a series of level-sensitive latches activated by a set of multiphase clock signals. In a typical design, when the clock signal makes a latch transparent, the data signal passes through that latch (usually through a combinational logic network) to the latch that becomes transparent in the next clock cycle. If the signal arrives before the receiving latch becomes transparent, the signal waits for transmission to the next stage. If the signal arrives while the receiving latch is transparent, time borrowing occurs, and the signal continues transmission through the next logic stage. If the signal arrives after the receiving latch has become transparent and then opaque, the signal cannot be transmitted through the latch. The signal must wait another clock cycle to pass through the latch, during which time logic calculations in the next clock cycle may destroy the signal, causing a logic error.

[0045] Therefore, the signal must arrive before the receiver latch becomes opaque. Setup time describes the minimum permissible time between the signal arriving at the level-sensitive latch and the arrival time of the clock edge that makes the level-sensitive latch opaque. The data signal must remain stable after the clock edge makes the level-sensitive latch opaque. Hold time describes the minimum time interval after the clock edge makes the level-sensitive latch opaque that the data signal must remain stable.

[0046] Figure 10 A schematic diagram illustrating timing constraints for an integrated circuit containing a biphase level-sensitive latch, according to an embodiment of the present invention, is shown. In this diagram, n is the number of logic levels traversed by the signal transmission path. Specifically, Figure 10 The signal setup and hold time constraints are given in an integrated circuit based on biphase level-sensitive latches, in which signal transmission passes through a sequence of level-sensitive latches alternately controlled by two clock signals of opposite phases. Where d i T is the signal transmission delay in the i-th logic level. c It is the clock cycle, T hold It is a signal hold time constraint, T setup It is a signal setup time constraint.

[0047] Figure 11 A schematic diagram illustrating timing constraints for an integrated circuit comprising a four-phase level-sensitive latch, according to an embodiment of the present invention, is shown. In this diagram, n is the number of logic levels traversed by the signal transmission path, k is the number of clock phases, and m is the number of high-level phases of the clock signal. Specifically, Figure 11Setup and hold time constraints for an integrated circuit based on four-phase level-sensitive latches are given, where signal transmission passes through a series of level-sensitive latches controlled by four clock signals of different phases. The four clock signals of different phases rise at 0%, 25%, 50%, and 75% of the clock cycle, and fall at 50%, 75%, 100%, and 25% of the clock cycle, respectively. i T is the signal transmission delay in the i-th logic level. c It is the clock cycle, T hold It is a signal hold time constraint, T setup This is a signal setup time constraint. On any data signal transmission path, level-sensitive latches become transparent sequentially: after a level-sensitive latch becomes transparent, the data signal is transmitted from it through the logic network, and the level-sensitive latch receiving the signal at the output of the logic network becomes transparent in the next clock phase. Each level-sensitive latch is transparent for two consecutive clock phases and opaque for another two consecutive clock phases. The delay of signal transmission through the first logic level must be less than three clock phases minus the setup time of the receiving-end level-sensitive latch, allowing the signal time to establish before the receiving-end level-sensitive latch becomes opaque; it must also be greater than the hold time of the receiving-end level-sensitive latch minus one clock cycle, allowing the signal of the previous cycle to be held after the receiving-end level-sensitive latch becomes opaque. This hold time constraint is usually easy to satisfy because it requires the signal transmission delay to be greater than a certain negative value. Any clock drift and / or uncertainties need to be taken into account.

[0048] Figure 11 A general form for setup and hold time constraints of integrated circuits based on multiphase level-sensitive latches is also given, where signal transmission passes through a series of level-sensitive latches controlled by clock signals of different phases. Let k be the number of clock phases, m be the number of opaque clock phases of the level-sensitive latches, and n be the number of logic levels traversed by the signal transmission path. Figure 14 This paper presents the general forms of setup and hold times in integrated circuits based on multiphase level-sensitive latches. Specifically, increasing n by one increases the maximum and minimum allowable data transmission path delay across n logic levels by the duration of one clock phase. This applies to circuits based on multiphase level-sensitive latches, where signal transmission passes through a series of level-sensitive latches controlled by clock signals with consecutive phases. In some cases, certain clock phases may be missing in a sequence of level-sensitive latches along a signal transmission path. More generally, the setup time constraint of a data signal arriving at a level-sensitive latch depends on the next latch's turn-off signal, and its hold time constraint depends on the previous latch's turn-off signal. This also applies to flip-flops constructed from level-sensitive latches.

[0049] When the number of logic levels n through which the signal is transmitted approaches infinity Figure 10 Or the timing constraints in 11 approach Figure 8 Or the timing constraints in point 9. But in reality, in most cases, n is very small. Figure 10 Or the timing constraints in 11 Figure 8 Or, the timing constraints in option 9 are more lenient, giving more room for performance optimization of integrated circuits. This is because: (1) The signal transmission path passes through the level-sensitive latch only when the data signal arrives at the latch later than the latch enable signal; otherwise, the arrival time of the level-sensitive latch output signal depends on the arrival time of the latch enable signal. (2) Considering parameter perturbations, when the parameter perturbations are not perfectly correlated, the longer the signal transmission path, the greater the mutual cancellation effect of the parameter perturbations, resulting in the worst-case negative time margin appearing on a finite-length signal transmission path; the exception is when the signal is transmitted in a closed loop, in which the worst-case negative time margin appears on an infinite-length signal transmission path. The above exceptions need to be considered in timing analysis. Timing analysis does not need to track the signal transmission through an infinite number of logic levels because as the number of logic levels n through which the signal transmission passes increases, the contribution of each logic level to any negative time margin decreases, so calculating the signal arrival time at a certain moment can obtain sufficient accuracy.

[0050] Compared to traditional static timing analysis methods that use time borrowing for level-sensitive latches, based on Figure 10 The static timing analysis method with timing constraints in step 11 requires tracing the signal transmission through the level-sensitive latch over multiple clock phases or cycles and comparing the arrival time of the data signal at the level-sensitive latch with the arrival time of the latch's enable signal, which immediately disables the latch after the data signal arrives in the original design. This timing analysis method requires more computation, more time, and more storage space to obtain the signal arrival time over multiple clock cycles. However, this method provides a complete signal transmission path across multiple logic levels, which is beneficial for implementing the optimization method of this invention, such as identifying the start and end points of the signal transmission path. Another advantage of this method is that its timing constraints are more lenient than the traditional time-borrowing-based timing constraints on level-sensitive latches, providing more room for performance optimization. This is because in the traditional time-borrowing-based method, the signal transmission path does not pass through the level-sensitive latch, and the maximum signal arrival time on the level-sensitive latch gives the borrowing time or the compensation time for all signal transmission paths originating from the level-sensitive latch. This compensation time is excessive for some paths.

[0051] The timing constraints described above provide greater flexibility for improving integrated circuit performance. Furthermore, converting edge-triggered timing elements into equivalent modules containing multi-phase level-sensitive latches offers more freedom in optimizing integrated circuits. For example, if a timing-critical path p1 terminates at the input of a flip-flop, while another timing-critical path p2 begins at the output of that flip-flop, moving the flip-flop in the circuit structure will not improve the circuit's performance or shorten the clock cycle. This is because shortening the timing-critical path p2, which begins at the flip-flop, inevitably degrades the performance of the timing-critical path p1, which terminates at the flip-flop, and vice versa. By converting the flip-flop into an equivalent module containing a pair of master-slave level-sensitive latches using this invention, for example, moving the slave latch can reduce the delay of the timing-critical path p2, which begins at the slave latch's output, without affecting the timing-critical path p1, which terminates at the master latch's input. The delay of the master latch can be reduced in the next optimization step, for example, by moving the level-sensitive latch at the starting point of the timing-critical path p1.

[0052] Repeating this process reduces latency along each critical path. As the number of edge-triggered sequential elements converted into equivalent modules containing level-sensitive latches increases, so too does the number of timing critical paths via level-sensitive latches or across multiple logic levels. The probability of a signal traveling through such long paths is low. Therefore, such circuits are well-suited for worst-case integrated circuit design techniques. In one embodiment of the invention, long signal transmission paths can be simply configured as pseudo-paths, resulting in better power consumption, performance, and / or area optimization if the resulting error rate is acceptable. In another embodiment of the invention, to guarantee a zero error rate, the integrated circuit detects and then corrects or predicts and then prevents any possible timing errors.

[0053] Figure 12 A block diagram of a timing error prediction device in the form of a finite state machine according to an embodiment of the present invention is shown. The device predicts timing errors by sampling signals in different logic levels of an integrated circuit containing multiphase level-sensitive latches. Specifically, Figure 12 This paper illustrates one embodiment of the invention based on better-than-worst-case integrated circuit design techniques, in which the signal transmission path delay exceeds the clock cycle. To guarantee a zero error rate, whenever a signal is transmitted in this path, a monitoring module generates a signal that activates a clock control logic gate, providing an additional clock cycle to allow the slow logic operation to complete, and then resumes system operation.

[0054] Figure 12A monitoring module in the form of a finite state machine is shown, which extracts input signals from a combinational logic network across multiple clock phases. Constructing this finite state machine first identifies a timing-critical path across one or more logic levels in an integrated circuit containing multiphase level-sensitive latches. Then, selects a subset of the edge inputs of this timing-critical path and designs a finite state machine that outputs logic 1 after receiving a predetermined pattern of signals at the edge inputs across multiple clock phases. For a logic gate on a signal propagation path, the edge input is an input to a logic gate not on the path. For the signal to propagate through the path, the edge input needs to take a non-control logic value for that logic gate. For the signal to propagate through the timing-critical path across multiple clock phases, the edge input needs to take specific non-control logic values ​​at specific phases. For example, Figure 12 This diagram illustrates two AND gates on a timing-critical path spanning two logic levels. The two edge inputs of each AND gate need to take the logic value 1 on two consecutive clock phases. A finite state machine can be constructed that outputs the logic value 1 after both edge inputs have taken the logic value 1 on two consecutive clock phases.

[0055] The probability of a signal transmission traversing a path depends on the probability that all edge inputs along that path take their respective non-control logic values, which can be estimated using the probability of some of the smallest edge inputs taking non-control logic values. Therefore, it is best to select the edge inputs with the smallest number of non-control logic values ​​as inputs to the finite state machine in the timing error prediction device, minimizing the probability of the device predicting timing errors, while also reducing the silicon cost of the device by selecting a few edge inputs. Such a device predicts every event of signal transmission along a given timing-critical path; any incorrect prediction results in performance degradation but not a logic error.

[0056] Figure 13 A block diagram of a timing error detection device according to an embodiment of the present invention is shown. The device is integrated into an integrated circuit containing a multi-phase level-sensitive latch, which compares the input-output signals of the level-sensitive latch when both the current level-sensitive latch and the preceding level-sensitive latch are opaque. Specifically, Figure 13 Another embodiment of the invention, superior to the worst-case design, is shown. Figure 13In the integrated circuit shown, signal transmission passes through a series of level-sensitive latches controlled by a four-phase clock signal. The latches sequentially become transparent and then sequentially become opaque. Each latch remains opaque for two consecutive clock phases. When a level-sensitive latch is opaque, and its preceding level-sensitive latch is also opaque, no signal should reach the logic network between them; otherwise, such a signal is a delayed signal that cannot pass through the receiving level-sensitive latch and will be destroyed in subsequent logic operations. Such delayed signals can be detected by a timing error detection device comprising a set of comparators, each comparing the input and output of the level-sensitive latch at the end of the timing critical path. Alternatively, if the signal is too late to be detected by the device at the end of the timing critical path, a level-sensitive latch and timing error detection device can be inserted in the middle of the timing critical path, with the inserted level-sensitive latch controlled by the same clock signal as the latch at the end of the timing critical path.

[0057] Inserting such a timing error detection device involves identifying a set of timing critical paths whose delay relative to a given set of clock signals does not exceed a given margin. Upon detecting a timing error, a timing error recovery mechanism is invoked, such as re-executing the erroneous operation, or a timing error correction mechanism is invoked, such as shifting the clock phase to catch a late signal.

[0058] The average performance of such an integrated circuit with a timing error prediction / detection device and a timing error recovery / correction mechanism depends on the probability of timing error prediction / detection, the performance when timing errors do not occur, and the performance when timing errors occur, including the performance degradation caused by timing error recovery / correction. Therefore, the combinational logic network optimization in this integrated circuit can be tailored to probabilistic objectives such as average performance, while also considering the probability of timing error prediction / detection. For example, timing critical paths with a small signal transmission probability are suitable for worst-case design and can incorporate timing error prediction / detection devices; timing critical paths with a large signal transmission probability are suitable for combinational logic optimization or latch removal and insertion to reduce signal transmission delay.

[0059] Figure 14 A flowchart of an integrated circuit optimization method according to an embodiment of the present invention is shown. The method includes the following steps: converting edge-triggered timing elements into equivalent modules containing multi-phase level-sensitive latches, retiming the level-sensitive latches, performing further conversions to level-sensitive latches, retiming the level-sensitive latches again, and employing better-than-worst-case design techniques. Specifically, Figure 14This illustration shows a preferred embodiment of the invention, namely an integrated circuit optimization system and method, comprising the following steps: converting an edge-triggered timing element into an equivalent module containing a multiphase level-sensitive latch, retiming the level-sensitive latch, further conversion to a level-sensitive latch, retiming the level-sensitive latch, and better-than-worst-case design techniques. Typically, there is an iterative process in which the integrated circuit is progressively optimized, ultimately meeting all design specifications and achieving design completion.

[0060] This invention relates to an integrated circuit optimization system and method, the method comprising converting edge-triggered sequential elements (e.g., flip-flops) into equivalent modules containing multiphase level-sensitive latches, and then employing certain level-sensitive latch-based optimization techniques, such as level-sensitive latch retiming and better-than-worst-case design based on predicting or detecting signal transmission through the level-sensitive latches.

[0061] This patent references certain patents, patent applications, and other materials (such as articles). The text of these patents, patent applications, and other materials is referenced only where it does not conflict with other texts and diagrams. Any conflicting patents, patent applications, and other materials are excluded from the scope of this patent's references.

[0062] Those skilled in the art will clearly understand from this description that further modifications and different embodiments of the invention are possible. The purpose of this description is to show and explain the general embodiments of the invention to those skilled in the art. It should be understood that the embodiments shown and described are examples of specific implementations. Key points and materials shown and described may be substituted, components and processes may be reversed, and certain functions of the invention may be used independently; these will be clearly understood by those skilled in the art from this description. Some key points described herein may be changed without departing from the spirit and scope of the invention as described in the following claims.

Claims

1. An integrated circuit comprising: Edge-triggered sequential elements, Multiphase level-sensitive latches deployed on timing-critical paths, In the logic network between the multi-phase level-sensitive latches, the input signal of the logic network comes from a first group of level-sensitive latches with the same phase, and the output signal of the logic network is sent to a second group of level-sensitive latches with the same phase. The first group of level-sensitive latches and the second group of level-sensitive latches have different phases. The integrated circuit is configured to be obtained through the following steps: a. Convert edge-triggered sequential elements into equivalent modules containing multi-phase level-sensitive latches; b. Moving one of the level-sensitive latches in the circuit structure of the integrated circuit, wherein the converted edge-triggered sequential element is at the beginning of the timing critical path; c. By traversing the netlist, starting from the input of the level-sensitive latch being moved and ending at the timing element or initial input, find the fan-in cone of the level-sensitive latch being moved; d. Insert edge-triggered timing elements into any initial input of the fan-in cone, and then convert each edge-triggered timing element of the fan-in cone into an equivalent module containing a multiphase level-sensitive latch; e. Remove the level-sensitive latch at a specific clock phase at the input of the fan-in cone; and f. Insert a level-sensitive latch of the clock phase at the output of the fan-in cone.

2. An integrated circuit comprising: Edge-triggered sequential elements, Multiphase level-sensitive latches deployed on timing-critical paths, In the logic network between the multi-phase level-sensitive latches, the input signal of the logic network comes from a first group of level-sensitive latches with the same phase, and the output signal of the logic network is sent to a second group of level-sensitive latches with the same phase. The first group of level-sensitive latches and the second group of level-sensitive latches have different phases. The integrated circuit is configured to be obtained through the following steps: a. Convert edge-triggered sequential elements into equivalent modules containing multi-phase level-sensitive latches; b. Moving one of the level-sensitive latches in the circuit structure of the integrated circuit, wherein the converted edge-triggered sequential element is at the end of the timing critical path; c. By traversing the netlist, starting from the output of the moved multiphase level-sensitive latch and ending at the timing element or initial output, find the fan-out cone of the moved level-sensitive latch; d. Insert edge-triggered timing elements into any final output of the input of the fan-out cone, and then convert each edge-triggered timing element at the output of the fan-out cone into an equivalent module containing a multiphase level-sensitive latch; e. Remove the level-sensitive latch at a specific clock phase at the output of the fan-out cone; and f. Insert a level-sensitive latch of the clock phase into the input terminal of the fan-out cone.

3. The integrated circuit according to claim 1 or 2, wherein the first group of level-sensitive latches and the second group of level-sensitive latches are out of phase.

4. The integrated circuit according to claim 3, wherein the first group of level-sensitive latches and the second group of level-sensitive latches with opposite phases form a flip-flop.

5. The integrated circuit according to claim 1 or 2, further comprising: A timing-critical path that passes through at least one level-sensitive latch. A finite state machine extracts input signals from a plurality of logic gates on the timing critical path, and the output signal of the finite state machine has a definite value when a signal passes through the timing critical path.

6. The integrated circuit according to claim 5, wherein the output signal of the finite state machine controls the clock signal.

7. The integrated circuit according to claim 1 or 2 further includes a comparator that compares the input signal and the output signal of the level-sensitive latch when the level-sensitive latch and all its parent level-sensitive latches are turned off.

8. The integrated circuit of claim 7, wherein the output of the comparator triggers a re-execution of the erroneous operation.

9. The integrated circuit of claim 7, wherein the output of the comparator triggers a shifted clock phase to capture a delayed signal.

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