Pixel circuit and display panel

Abstract

This invention discloses a pixel circuit and a display panel. The pixel circuit includes a light-emitting module connected between a first power supply and a second power supply; a driving transistor connected between the first power supply and the light-emitting module, the driving transistor including a first gate and a second gate; an initialization module connected between an initialization line and the first gate; and a second gate used to input a first bias control signal in an initial stage and a second bias control signal in a brightness holding stage; wherein at least a portion of the amplitude of the second bias control signal is smaller than the amplitude of the first bias control signal. The technical solution provided by this invention solves the problem of screen flicker in display panels.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a pixel circuit and a display panel. Background Technology

[0002] With the development of display technology, people have increasingly higher requirements for display technology, needing display panels to display images at lower driving frequencies. Existing display panels exhibit screen flicker when displaying images at lower frequencies, affecting the display effect. Summary of the Invention

[0003] This invention provides a pixel circuit and a display panel to solve the problem of screen flickering when the display panel displays images at a low frequency.

[0004] According to one aspect of the present invention, a pixel circuit is provided, comprising:

[0005] The light-emitting module is connected between the first power supply and the second power supply.

[0006] A driving transistor is connected between a first power supply and a light-emitting module. The driving transistor includes a first gate and a second gate.

[0007] An initialization module is connected between the initialization line and the first gate.

[0008] The second gate is used to input a first bias control signal in the initial stage and a second bias control signal in the brightness holding stage; wherein at least a portion of the amplitude of the second bias control signal is smaller than the amplitude of the first bias control signal.

[0009] Optionally, the pixel circuitry also includes:

[0010] The initialization module includes a first initialization module, the first terminal of which is connected to the first gate of the driving transistor, and the second terminal of which is connected to the second terminal of the driving transistor.

[0011] The first initialization module includes a third gate and a fourth gate; the third gate is used to input the first light-emitting control signal.

[0012] The fourth gate is used to input the first light emission control signal; or, the fourth gate is used to input the first bias control signal in the initial stage and the second bias control signal in the brightness holding stage.

[0013] Optionally, when displaying the image in the first frequency range, the second gate and / or the fourth gate are configured to input a first bias control signal in the initial stage and a second bias control signal in the brightness holding stage;

[0014] Preferably, the first frequency range includes frequencies less than 60 Hz.

[0015] Optionally, the voltage of the first bias control signal is constant;

[0016] The second bias control signal has at least one of the following: constant voltage, gradually decreasing voltage, or pulsed voltage.

[0017] Optionally, the second gate and / or the fourth gate are configured such that the voltage of the input second bias control signal decreases linearly; or,

[0018] The second gate and / or the fourth gate are configured to have the same or gradually decreasing duty cycle as the second bias control signal input.

[0019] Optionally, the brightness maintenance phase includes N sub-emission periods;

[0020] The second gate and / or the fourth gate are configured such that the voltage of the second bias control signal input in each sub-light emission period gradually decreases, and the voltage amplitude of the second bias control signal input in the (i+1)th sub-light emission period is less than the voltage amplitude of the second bias control signal transmitted in the ith sub-light emission period.

[0021] Where N is a positive integer greater than or equal to 1, and i is a positive integer less than N.

[0022] Optionally, the brightness maintenance phase includes N sub-emission periods;

[0023] The second gate and / or the fourth gate are configured such that the voltage amplitude of the second bias control signal input in the (j+1)th sub-light emission period is greater than the voltage amplitude of the second bias control signal input in the jth sub-light emission period, and equal to the voltage amplitude of the second bias control signal transmitted in the (j-1)th sub-light emission period.

[0024] Where N is a positive integer greater than or equal to 1, and j is a positive integer less than N.

[0025] Optionally, the initialization module may also include:

[0026] Second initialization module;

[0027] The first electrode of the second initialization module is connected to the anode of the light-emitting module, and the second electrode of the second initialization module is connected to the initialization line;

[0028] The second initialization module includes a fifth gate and a sixth gate;

[0029] The fifth gate is used to input the second light-emitting control signal, and the sixth gate is used to input the first light-emitting control signal.

[0030] In a second aspect, embodiments of the present invention provide a display panel, including: the pixel circuit proposed in any of the first aspects.

[0031] Optionally, the display panel may also include:

[0032] At least one first bias line extends along a first direction and is used to connect to the second gate of the pixel circuit.

[0033] At least one switching module is connected between the first bias line and the second gate of the pixel circuit;

[0034] Along the first direction, the second gates of pixel circuits located in the same column are connected to the same first bias line;

[0035] Along the second direction, the control signals input to the control terminals of the switch modules located in adjacent rows are different; wherein, the second direction intersects with the first direction.

[0036] The technical solution of this invention configures the pixel circuit to include a light-emitting module and a driving transistor. The driving transistor includes a first gate and a second gate. The second gate is used to input a first bias control signal in the initial stage and a second bias control signal in the brightness holding stage. At least a portion of the amplitude of the second bias control signal is smaller than the amplitude of the first bias control signal. This configuration ensures that during the brightness holding stage, the pixel circuit receives a second bias control signal with a smaller amplitude, resulting in less change in the driving current of the pixel circuit. When the display panel displays images with low frequency, the driving current of the pixel driving circuit can remain consistent, improving the display effect of the display panel.

[0037] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention;

[0040] Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0041] Figure 3 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention;

[0042] Figure 4 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0044] Figure 6 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0045] Figure 7 This is a driving timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0046] Figure 8 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0047] Figure 9 This is a schematic diagram of the pixel circuit structure of another display panel provided in an embodiment of the present invention. Detailed Implementation

[0048] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0050] As mentioned in the background section, display panels suffer from screen flicker when displaying images at lower frequencies. The inventors discovered that LTPO (Low Temperature Polycrystalline Oxide) screen technology can achieve a minimum refresh rate of 1Hz. Lower refresh rates result in lower power consumption, saving significant amounts of electricity. However, because LTPO screens display images at lower frequencies, such as 1Hz or even 0.1Hz, data is written to the pixel circuits of the display panel at 60Hz. The characteristics of the driving transistors in the pixel circuits are prone to change, leading to variations in the driving current and thus causing screen flicker.

[0051] Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. See also: Figure 1 The display device 200 includes a display panel 100. The display panel 100 includes a plurality of pixel circuits 1.

[0052] The display panel 100 may also include multiple scan lines Scan 1-Scan n, multiple data lines Data1-Data n, multiple light emission control lines EM 1-EM n, and a driver chip 300. The pixel circuit 1 is set in the area defined by the intersection of the scan lines and the data lines. The scan lines input scan signals to the corresponding pixel circuit 1. Under the action of the scan signals input by the scan lines electrically connected to it, the pixel circuit 1 connects to the corresponding electrically connected data lines. The driver chip 300 inputs data signals to the corresponding pixel circuit 1 through the data lines. The voltage of the data signals corresponds to the driving voltage, which determines the light emission brightness of the light emission module, that is, determines the display grayscale of the light emission module.

[0053] The light-emitting module may include light-emitting modules with different emitting colors. It should be noted that this application uses light-emitting modules with red, green, and blue emitting colors as examples for illustration. The light-emitting module may also include light-emitting modules of other colors, and no limitation is made here.

[0054] The display panel 100 also includes an initialization line Vref. Each pixel circuit 1 is connected to a first power line VDD, a second power line VSS, and the initialization line Vref, respectively. The first power line VDD is used to transmit a first voltage signal to the anode of the light-emitting module, which is typically a high-level signal. The second power line VSS is used to transmit a second voltage signal to the cathode of the light-emitting module, which is typically a low-level signal. See also Figure 1 The display panel 100 also includes a first bias line Vini, which is used to transmit a first bias control signal to the pixel circuit 1.

[0055] Pixel circuit 1 may include multiple thin-film transistors and a memory module. The thin-film transistors may include driving transistors and switching transistors. The driving transistors and the light-emitting module are sequentially connected between a first power line VDD and a second power line VSS. The driving transistors generate a driving current to drive the light-emitting module connected to pixel circuit 1 to emit light. The switching transistors primarily function as switches.

[0056] Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 3 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention. Figure 4 This is a driving timing diagram for another pixel circuit provided in an embodiment of the present invention. Combined with... Figures 1 to 4 The pixel circuit 1 provided in this embodiment includes a light-emitting module D1 connected between a first power supply VDD and a second power supply VSS; a driving transistor M1 connected between the first power supply VDD and the light-emitting module D1. The driving transistor M1 includes a first gate and a second gate; an initialization module 2 connected between an initialization line Vref and the first gate; the second gate is used to input a first bias control signal in the initial stage t1 and a second bias control signal in the brightness holding stage t2; wherein at least a portion of the amplitude of the second bias control signal is smaller than the amplitude of the first bias control signal.

[0057] Specifically, the light-emitting module D1 emits light by being driven by a driving circuit, which can be, for example, a... Figure 2 The driving circuit shown. Combined with... Figures 1 to 4 The pixel circuit 1 provided in this embodiment can correspond to Figure 1 A specific circuit structure of the pixel circuit 1 in the display panel 100 shown. Combined with... Figure 1 and Figure 2 The pixel circuit 1 includes a driving transistor M1, an initialization module 2, a data writing module 3, a light emission control module 5, and a storage module 4.

[0058] The operation of the pixel circuit 1 includes an initialization phase t1 and a brightness maintenance phase t2. The initialization phase t1 includes an initialization phase T1, a data writing phase T2, and a subthreshold swing compensation phase T3. The brightness maintenance phase t2 includes an emission phase T4.

[0059] See Figure 3During the initialization phase T1, the first light-emitting control line EM1 is at a high level, the second light-emitting control line EM2 is at a low level, the initialization module 2 is turned on, and the initialization line Vref transmits the initialization signal to the gate G of the driving transistor M1 and the anode of the light-emitting module D1. The total time of the initialization phase T1 is the overlap time between the light-emitting signal of the second light-emitting control signal EM1 and the extinguishing signal of the first light-emitting control signal EM2 before the data writing phase T2. The initialization time can be adjusted by timing.

[0060] During the data writing phase T2, both the first light-emitting control line EM1 and the second light-emitting control line EM2 are at a high level, the scan signal Scan is at a low level, and both the initialization module 2 and the data writing module 3 are turned on. The data voltage is written to the gate G of the driving transistor M1 through the conducting data writing module 3 and the initialization module 2. The total time of the data writing phase T2 is the time during which the scan signal Scan is turned off before the subthreshold swing compensation phase T3.

[0061] During the subthreshold swing compensation phase T3, the scan signal Scan is high, data writing module 3 is off, the first light emission control line EM1 is high, initialization module 2 is on, and the driving transistor M1 continues to charge its gate G. The storage module 4 maintains the voltage at point S of the driving transistor M1, allowing it to continue charging the gate G to compensate for the threshold voltage Vth of the driving transistor M1. The compensation time can be adjusted as needed via timing adjustments.

[0062] During the light-emitting stage T4, both the first light-emitting control line EM1 and the second light-emitting control line EM2 are at a low level, the light-emitting control module 5 is turned on, the driving transistor M1 is turned on, and the light-emitting module D1 emits light.

[0063] See Figure 4 In this embodiment, the second gate of the driving transistor M1 of the pixel circuit 1 is used to input a first bias control signal in the initial stage t1 and a second bias control signal in the brightness holding stage t2. The second gate of the driving transistor M1 is connected to a first bias line Vini, which provides a bias control signal to the second gate of the driving transistor M1 of the pixel circuit 1. When the pixel circuit 1 displays an image on the display panel, the first bias line Vini transmits the first bias control signal to the second gate in the initial stage t1 and the second bias control signal to the second gate in the brightness holding stage t2. At least a portion of the amplitude of the second bias control signal is smaller than the amplitude of the first bias control signal.

[0064] Specifically, pixel circuit 1 includes a light-emitting module D1 and a driving circuit. Responding to scan and data signals, pixel circuit 1 writes data to the gate G of the driving transistor M1 in the driving circuit during the initial stage t1, and maintains stable light emission from the light-emitting module D1 during the brightness holding stage t2. A first bias line, Vini, provides a bias control signal to pixel circuit 1. This bias control signal adjusts the threshold voltage of the driving transistor, thereby regulating the magnitude of the driving current transmitted from the driving circuit to the light-emitting module D1. This configuration minimizes the variation in driving current during the brightness holding stage t2, resulting in better uniformity of the light emission brightness of the light-emitting module D1 and resolving the flickering problem that exists when the display panel displays images in a low-frequency range.

[0065] Because the characteristics of the driving transistor in pixel circuit 1 are prone to change in the lower frequency range of the driving frequency, the amplitude of the threshold voltage of the driving transistor gradually increases with the increase of the light emission time, causing the driving current flowing through the driving transistor to gradually decrease, thereby reducing the brightness of the light emission module D1. By setting the second gate of pixel circuit 1 to receive a first bias control signal in the initial stage t1 and a second bias control signal in the brightness holding stage t2 when displaying the image, at least part of the amplitude of the second bias control signal is smaller than the amplitude of the first bias control signal. This setting ensures that in the initial stage t1, the light emission module D1 of pixel circuit 1 receives a first bias control signal with a larger amplitude. In the brightness holding stage t2, the amplitude of the threshold voltage of driving transistor M1 gradually increases. By setting a bias control signal with a larger amplitude, the fluctuation of the threshold voltage of driving transistor M1 is reduced, thereby reducing the fluctuation of the driving current and making the driving current as consistent as possible in the brightness holding stage t2, thereby improving the brightness uniformity of the display panel in the first frequency range and improving the display effect of the display panel.

[0066] The technical solution of this invention configures the pixel circuit to include a light-emitting module and a driving transistor. The driving transistor includes a first gate and a second gate. The second gate is used to input a first bias control signal in the initial stage and a second bias control signal in the brightness holding stage. At least a portion of the amplitude of the second bias control signal is smaller than the amplitude of the first bias control signal. This configuration ensures that during the brightness holding stage, the pixel circuit receives a second bias control signal with a smaller amplitude, resulting in less change in the driving current of the pixel circuit. When the display panel displays images with low frequency, the driving current of the pixel driving circuit can remain consistent, improving the display effect of the display panel.

[0067] Optional, Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Based on the above embodiments, and combined with… Figure 5 and Figure 6 The initialization module 2 provided in this embodiment includes: a first initialization module 21; the first terminal of the first initialization module 21 is connected to the first gate of the driving transistor M1, and the second terminal of the first initialization module 21 is connected to the second terminal of the driving transistor M1; the first initialization module 21 includes a third gate and a fourth gate; the third gate is used to input a first light emission control signal; see also Figure 5 The fourth gate is used to input the first light-emitting control signal; or, see [link to relevant documentation]. Figure 6 The fourth gate is used to input the second bias control signal.

[0068] An alternative implementation method is described in [reference]. Figure 5 The fourth gate of the first initialization module 21 can be connected to the first light-emitting control line EM1. This configuration allows both the third and fourth gates of the first initialization module 21 to be connected to the same first light-emitting control line EM1, which facilitates wiring, simplifies the driving process, and makes it easy to implement.

[0069] Optionally, based on the above embodiments, see also... Figure 5 The pixel circuit 1 of the display panel provided in this embodiment of the invention includes: a light-emitting module D1 connected between a first power supply VDD and a second power supply VSS; a driving transistor M1 connected between the first power supply VDD and the light-emitting module D1 to control the driving current, the driving transistor M1 including a first gate and a second gate; and a storage module 4 connected to the first gate of the driving transistor M1. A first bias line Vini is connected to the second gate, the second gate inputs a first bias control signal in the initial stage t1, and inputs a second bias control signal in the brightness holding stage t2.

[0070] Specifically, when the display panel displays an image, and the driving frequency is within the first frequency range, the threshold voltage of the driving transistor M1 will gradually increase in amplitude during the brightness holding phase t2 due to negative bias. The longer the brightness holding phase t2 lasts, the greater the fluctuation in the amplitude of the threshold voltage of the driving transistor M1. Since at least a portion of the amplitude of the second bias control signal is smaller than the amplitude of the first bias control signal, the second gate is configured to input the first bias control signal in the initial phase t1 and the second bias control signal in the brightness holding phase t2. This configuration ensures that in the initial phase t1, the second gate receives a first bias control signal with a larger amplitude, allowing data signals to be written to the first gate of the driving transistor M1 during the initial phase t1.

[0071] During the brightness holding phase t2, the amplitude of the threshold voltage of the driving transistor M1 gradually increases. By setting a second bias control signal input to the second gate during the brightness holding phase t2, the bias control signal with a larger amplitude acts on the second gate of the driving transistor M1, reducing the fluctuation of the threshold voltage of the driving transistor M1, thereby reducing the fluctuation of the driving current and making the driving current as consistent as possible during the brightness holding phase t2. This results in better uniformity of the display panel 100's brightness within the first frequency range with a lower driving frequency, further improving the display effect of the display panel 100.

[0072] Another alternative implementation method is described in [reference 1]. Figure 6 The display panel also includes a second bias line, Vini2, which connects the fourth gate of the first initialization module 21 to the second bias line, Vini2. The fourth gate of the first initialization module 21 receives a second bias control signal.

[0073] Optional, Figure 7 This is a driving timing diagram for another pixel circuit provided in an embodiment of the present invention. Based on the above embodiments, combined with... Figure 6 and Figure 7 When the fourth gate of the first initialization module 21 is connected to the second bias line Vini2, the fourth gate of the first initialization module 21 inputs the first bias control signal in the initial stage t1 and inputs the second bias control signal in the brightness holding stage t2.

[0074] Specifically, the first initialization module 21 may include a first transistor M3, which may include an indium gallium zinc oxide (IGZO) transistor. Since the threshold voltage of an IGZO transistor is easily biased, and the first initialization module 21 is connected to the first gate of the driving transistor M1, fluctuations in the threshold voltage of the first transistor M3 can easily couple and affect the voltage of the first gate of the driving transistor M1. By setting the fourth gate of the first initialization module 21 to input a first bias control signal in the initial stage t1 and a second bias control signal in the brightness holding stage t2, this setting allows a larger amplitude bias control signal to act on the fourth gate of the first initialization module 21, reducing the fluctuation of the threshold voltage of the first initialization module 12. This reduces the fluctuation of the threshold voltage of the first initialization module 12, making the coupling between the first initialization module 12 and the first gate of the driving transistor M1 more consistent. Consequently, the voltage fluctuation of the first gate of the driving transistor M1 connected to the first terminal of the first initialization module 12 is smaller, making the driving current as consistent as possible in the brightness holding stage t2. This results in better uniformity of brightness display on the display panel within the first frequency range with a lower driving frequency, further improving the display effect of the display panel.

[0075] Optionally, based on the above embodiments, see also... Figure 6 The initialization module 2 of the pixel circuit 1 of the display panel provided in this embodiment of the invention may further include: a second initialization module 22; the first electrode of the second initialization module 22 is connected to the anode of the light-emitting module D1, and the second electrode of the second initialization module 22 is connected to the initialization line Vref; the second initialization module 22 includes a fifth gate and a sixth gate; the fifth gate is used to input a second light-emitting control signal, and the sixth gate is used to input a first light-emitting control signal.

[0076] Specifically, the second initialization module 22 may include a second transistor M4, the data writing module 3 may include a third transistor M2, the light emission control module 4 may include a fourth transistor M5 and a fifth transistor M6, and the storage module 4 may include a first storage module C1 and a second storage module C2.

[0077] It should be noted that the driving transistor M1, the switching transistor, and the storage module 4 can be connected in various ways to form various forms of pixel circuit 1. Figure 5 and Figure 6 The pixel circuit 1 shown is just an example. Pixel circuit 1 can also be other forms of pixel circuit 1, such as 6T2C pixel circuit 1, 7T1C pixel circuit 1 and 8T2C pixel circuit 1, etc., where T represents transistor and C represents capacitor. Figure 5 and Figure 6 The example shown is of the 6T2C pixel circuit 1 and is not intended to limit the pixel circuit 1.

[0078] Optionally, based on the above embodiments, see also... Figure 4 and Figure 7 In the pixel circuit provided in this embodiment, when displaying an image in the first frequency range, the second gate and / or the fourth gate are configured to input a first bias control signal in the initial stage and input a second bias control signal in the brightness holding stage.

[0079] Specifically, the first bias line Vini and / or the second bias line Vini2 are used to provide bias control signals to the pixel circuit 1. When the pixel circuit 1 displays an image in the first frequency range, the first bias line Vini and / or the second bias line Vini2 are configured to transmit the first bias control signal in the initial stage t1 and transmit the second bias control signal in the brightness holding stage t2. At least a portion of the amplitude of the second bias control signal is smaller than the amplitude of the first bias control signal. This configuration ensures that in the brightness holding stage t2, the first bias line Vini and / or the second bias line Vini2 transmit a second bias control signal with a smaller amplitude to the pixel circuit 1, resulting in smaller changes in the driving current of the pixel circuit 1. This allows the display panel to maintain a consistent driving current when displaying images in the lower first frequency range, thereby improving the display effect of the display panel.

[0080] Optionally, based on the above embodiments, the first frequency range includes frequencies less than 60Hz.

[0081] Specifically, the first frequency range includes frequencies less than 60Hz, such as 30Hz, 1Hz, 0.1Hz, etc.

[0082] For example, when the display panel displays an image at a frequency of 1Hz, in the initial stage t1, the data line still writes data at a frequency of 60Hz. In the brightness holding stage t2, the drive frequency is maintained at 1Hz. At this time, because the drive frequency of 1Hz is lower than 60Hz, the duration of the brightness holding stage t2 is longer. As the brightness holding stage t2 extends, the amplitude of the threshold voltage of the drive transistor M1 gradually increases. By setting a second bias control signal with a larger amplitude input to the second gate and / or the fourth gate in the brightness holding stage t2, the fluctuation of the threshold voltage of the drive transistor is reduced, thereby reducing the fluctuation of the drive current and making the drive current as consistent as possible in the brightness holding stage t2. This reduces the flickering problem that exists when the display panel displays images in the lower first frequency range, improving the display effect of the display panel.

[0083] Optionally, based on the above embodiments, see also... Figure 4 and Figure 7 In the embodiments of the present invention, the voltage of the first bias control signal of the display panel is constant; the voltage of the second bias control signal is constant, gradually decreasing, or pulsed. The second bias control signal transmitted through the second gate and the second bias control signal transmitted through the fourth gate can be set to be the same or different.

[0084] Specifically, since the frequency of the initial stage t1 is 60Hz, the time of the initial stage t1 is relatively short, and the driving current of the pixel circuit 1 is not easy to change. This keeps the voltage of the first bias control signal constant, making the first bias control signal easier to implement and reducing the implementation difficulty of the driver chip 300 that generates the first bias control signal, thereby reducing the manufacturing cost of the display panel.

[0085] See also Figure 4 and Figure 7By setting the voltage of the second bias control signal to be constant, gradually decreasing, or pulsed, the second gate and / or fourth gate of the pixel circuit 1 receive a second bias control signal with a small amplitude for at least a portion of the brightness holding phase t2. This compensates for the changes in the driving current during the brightness holding phase t2, resulting in smaller fluctuations in the driving current of the pixel circuit 1. This configuration allows the light-emitting module D1 to display the image more uniformly during the brightness holding phase t2, further improving the display effect of the display panel. Optionally, based on the above embodiment, see... Figure 4 and Figure 7 In the embodiments of the present invention, the voltage of the second bias control signal of the display panel configured as input is linearly reduced; or the duty cycle of the second bias control signal of the second gate and / or the fourth gate configured as input is equal or gradually reduced.

[0086] Specifically, the duty cycles of the second bias control signals input to the second gate and / or the fourth gate during the brightness holding phase t2 are set to be equal or gradually decreased, so that the amplitude of the second bias control signals is reduced to a certain extent during the brightness holding phase t2, thereby compensating for the increase in the threshold voltage of the driving transistor of the pixel circuit 1. On the other hand, the duty cycles of the second bias control signals can be set to be equal or gradually decreased as needed, so that the second bias control signals can compensate for the fluctuations in the driving current of the display panel as much as possible, thereby improving the display effect of the display panel.

[0087] As the threshold voltage amplitude of the driving transistor M1 of the pixel circuit 1 gradually increases during the brightness holding phase t2, the threshold voltage of the driving transistor M1 changes approximately linearly. The second bias control signal input to the second gate and / or the fourth gate decreases linearly, making the compensation for the fluctuation of the driving current of the pixel circuit 1 more uniform and further improving the display effect of the display panel.

[0088] Optionally, based on the above embodiments, see also... Figure 4 In the first method, the brightness holding stage t2 of the display panel provided in this embodiment of the invention includes N sub-light emission periods L1 to Ln; the second gate and / or the fourth gate are configured such that the voltage of the second bias control signal input in each sub-light emission period gradually decreases, and the voltage amplitude of the second bias control signal input in the (i+1)th sub-light emission period is less than the voltage amplitude of the second bias control signal transmitted in the ith sub-light emission period; wherein, N is a positive integer greater than or equal to 1, and i is a positive integer less than N.

[0089] Specifically, each sub-emission stage can be one frame, and the brightness holding stage t2 is divided into N sub-emission periods. It can be set that in each sub-emission period, the voltage of the second bias control signal input to the second gate and / or the fourth gate gradually decreases, so that the increase in the amplitude of the threshold voltage of the driving transistor M1 of the pixel circuit 1 can be compensated in each sub-emission period. This ensures that the threshold voltage of the driving transistor M1 remains constant in each sub-emission period, resulting in a more uniform driving current in each sub-emission period and improving the display effect of the display panel.

[0090] Because the threshold voltage of the driving transistor M1 in pixel circuit 1 becomes negatively biased during the brightness holding phase t2, as the sub-emission phase continues, the amplitude of the threshold voltage of the driving transistor M1 gradually increases. The longer the brightness holding time, the larger the amplitude of the threshold voltage of the driving transistor M1. By setting the voltage amplitude of the second bias control signal input to the second gate and / or the fourth gate in the (i+1)th sub-emission period to be smaller than the voltage amplitude of the second bias control signal input in the ith sub-emission period, a second bias control signal with a smaller voltage amplitude is transmitted in the (i+1)th sub-emission period when the threshold voltage amplitude of the driving transistor M1 is larger. This further improves the stability of the threshold voltage of the driving transistor M1 during the brightness holding phase t2, and further improves the display effect of the display panel.

[0091] Optionally, based on the above embodiments, see also... Figure 4 In the second method, the brightness holding stage t2 of the display panel provided in this embodiment of the invention includes N sub-light emission periods; the second gate and / or the fourth gate are configured such that the voltage amplitude of the second bias control signal input in the (j+1)th sub-light emission period is greater than the voltage amplitude of the second bias control signal input in the jth sub-light emission period, and equal to the voltage amplitude of the second bias control signal transmitted in the (j-1)th sub-light emission period; wherein, N is a positive integer greater than or equal to 1, and j is a positive integer less than N.

[0092] Specifically, this setting ensures that the voltage amplitude of the second bias control signal transmitted during the (j+1)th sub-light-emitting period is greater than the voltage amplitude of the second bias control signal transmitted during the jth sub-light-emitting period, and equal to the voltage amplitude of the second bias control signal transmitted during the (j-1)th sub-light-emitting period. This not only improves the stability of the threshold voltage of the driving transistor M1 during the brightness holding phase t2, further improving the display effect of the display panel, but also facilitates the generation of the second bias control signal by the driving chip 300.

[0093] This invention provides a display panel. (Continue reading...) Figure 1The display panel 100 provided in this embodiment of the invention includes the pixel circuit 1 proposed in any of the above embodiments, and has the beneficial effects of the pixel circuit 1 proposed in any of the above embodiments, which will not be described again here. The display panel 100 provided in this embodiment of the invention can be applied to terminals such as mobile phones, tablet computers, and wearable devices.

[0094] Optional, Figure 8 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 9 This is a schematic diagram of the pixel circuit structure of another display panel provided in an embodiment of the present invention. Based on the above embodiments, see... Figure 8 The display panel provided in this embodiment may further include: at least one first bias line Vini, which extends along a first direction Y and is used to connect the second gate of the pixel circuit 1; at least one switch module 7, which is connected between the first bias line Vini and the second gate of the pixel circuit 1; along the first direction Y, the second gates of the pixel circuit 1 located in the same column are connected to the same first bias line Vini; along the second direction X, the control signals input to the control terminals of the switch modules 7 located in adjacent rows are different; wherein, the second direction X intersects the first direction Y.

[0095] Specifically, each column is equipped with a first bias line (Vini) for transmitting a first bias control signal and a second bias control signal to the second gate of pixel circuit 1. See also Figure 8 The example illustrates that, along the first direction Y, each column of pixels corresponds to a first bias line Vini-1, a first bias line Vini-2, and a first bias line Vini-3, respectively. Along the second direction X, each row is arranged with a corresponding switch module 7, which may include a switching transistor. The control terminals of switch modules 7 located in the same row receive the same scan signal, while the control terminals of switch modules 7 located in adjacent rows receive different scan signals. The switch module scans row by row according to the scan signal received at its control terminal. When a scan signal arrives, the switch module 7 in that row is turned on, controlling the first bias line Vini to transmit a bias control signal to the second gate of the pixel circuit 1. See also... Figure 9 The second gate and the first power supply VDD form a capacitor C2, which is responsible for storing the bias control signal of the second gate of the driving transistor M1 of each pixel circuit 1 within 1 second.

[0096] In the initial stage t1, i.e., the write frame, the first bias control signal transmitted by the first bias line Vini is the first power supply signal VDD. In the brightness holding stage t2, i.e., the brightness holding frame, the second bias control signal transmitted by the first bias line Vini is as follows: Figure 4The voltage signal shown keeps the potential of the second gate constant, which in turn keeps the current of the driving transistor M1 constant, and this cycle repeats. This setting better compensates for the characteristic difference of the drive transistor M1 between the write frame and the hold frame, improves the transient characteristic changes of the drive transistor M1, and thus improves low-frequency or frequency-switching flicker.

[0097] Optionally, the display panel 100 may further include a second bias line Vini2, which may extend along a first direction Y and is used to connect to the fourth gate of the pixel circuit 1; at least one switch module 7 connected between the second bias line Vini2 and the fourth gate of the pixel circuit 1; along the first direction Y, the fourth gates of the pixel circuits 1 located in the same column are connected to the same second bias line Vini2; along the second direction X, the control signals input to the control terminals of the switch modules 7 located in adjacent rows are different. This configuration allows the second bias control signal to compensate for fluctuations in the drive current of the display panel as much as possible, further improving the display effect of the display panel.

[0098] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0099] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A pixel circuit, characterized by comprising: include: The light-emitting module is connected between the first power supply and the second power supply. A driving transistor is connected between the first power supply and the light-emitting module, and the driving transistor includes a first gate and a second gate. An initialization module is connected between an initialization line and the first gate; the second gate is used to input a first bias control signal in the initial stage and a second bias control signal in the brightness holding stage; wherein at least a portion of the amplitude of the second bias control signal is smaller than the amplitude of the first bias control signal; The initial stage includes an initialization stage, a data writing stage, and a subthreshold swing compensation stage; the brightness maintenance stage includes a light emission stage. The initialization module includes a first initialization module, the first terminal of which is connected to the first gate of the driving transistor, and the second terminal of which is connected to the second terminal of the driving transistor. The first initialization module includes a third gate and a fourth gate; the third gate is used to input a first light emission control signal. The fourth gate is used to input a first light emission control signal; or, the fourth gate is used to input a first bias control signal in the initial stage and a second bias control signal in the brightness maintenance stage.

2. The pixel circuit according to claim 1, characterized in that, When displaying an image in the first frequency range, the second gate and / or the fourth gate are configured to input a first bias control signal in the initial phase and a second bias control signal in the brightness holding phase.

3. The pixel circuit of claim 2, wherein, The first frequency range includes frequencies less than 60 Hz.

4. The pixel circuit of claim 2, wherein, The voltage of the first bias control signal is constant; The second bias control signal has at least one of the following: constant voltage, gradually decreasing voltage, or pulsed voltage.

5. The pixel circuit according to claim 1, characterized in that, The voltage of the second bias control signal, configured as an input to the second gate and / or the fourth gate, decreases linearly; or, The duty cycles of the second bias control signal, which is configured to be input to the second gate and / or the fourth gate, are equal or gradually decrease.

6. The pixel circuit of claim 1, wherein, The brightness maintenance phase includes N sub-emission periods; The second gate and / or the fourth gate are configured such that the voltage of the second bias control signal input in each of the sub-light emission periods gradually decreases, and the voltage amplitude of the second bias control signal input in the (i+1)th sub-light emission period is less than the voltage amplitude of the second bias control signal transmitted in the ith sub-light emission period. Where N is a positive integer greater than or equal to 1, and i is a positive integer less than N.

7. The pixel circuit according to claim 1, characterized in that, The brightness maintenance phase includes N sub-emission periods; The second gate and / or the fourth gate are configured such that the voltage amplitude of the second bias control signal input in the (j+1)th sub-light emission period is greater than the voltage amplitude of the second bias control signal input in the jth sub-light emission period, and equal to the voltage amplitude of the second bias control signal transmitted in the (j-1)th sub-light emission period. Where N is a positive integer greater than or equal to 1, and j is a positive integer less than N.

8. The pixel circuit according to claim 1, characterized in that, The initialization module further includes: Second initialization module; The first electrode of the second initialization module is connected to the anode of the light-emitting module, and the second electrode of the second initialization module is connected to the initialization line; The second initialization module includes a fifth gate and a sixth gate; The fifth gate is used to input the second light emission control signal, and the sixth gate is used to input the first light emission control signal.

9. A display panel, characterized in that, include: The pixel circuit according to any one of claims 1-8.

10. The display panel according to claim 9, characterized in that, The display panel further includes: At least one first bias line extends along a first direction and is used to connect to the second gate of the pixel circuit. At least one switching module is connected between the first bias line and the second gate of the pixel circuit; Along the first direction, the second gates of the pixel circuits located in the same column are connected to the same first bias line; Along the second direction, the control signals input to the control terminals of the switch modules located in adjacent rows are different; wherein, the second direction intersects with the first direction.

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