A method for processing a silicon wafer, a silicon wafer, and a chip comprising the silicon wafer

Abstract

The application relates to a silicon wafer processing method, a silicon wafer and a chip containing the silicon wafer, relates to the field of microelectronic chip manufacturing, and solves the problem of the influence of the existing bidirectional thyristor surface corrosion pits on the reliability of a chip.S1, a SIPOS protective film is grown on the surface of the silicon wafer by using a CVD technology;S2, glass is grown in a glass groove of the silicon wafer by using a passivation technology;S3, a thin oxide layer is grown on the surface of the silicon wafer by using a CVD technology;S4, after the photoresist is photosensitive and chemical reaction occurs, the pattern on the photoetching plate is transferred to the corroded silicon wafer;S5, the silicon wafer is put into SIPOS+polycrystalline etching liquid to perform one-step etching, the SIPOS+polycrystalline etching liquid is prepared from nitric acid, hydrofluoric acid and glacial acetic acid;S6, after etching, the photoresist is removed and cleaned, and the silicon wafer with the required pattern on the surface is obtained.

Description

Technical Field

[0001] This invention relates to the field of microelectronic chip manufacturing, and more specifically to a silicon wafer processing method, a silicon wafer, and a chip containing the silicon wafer. Background Technology

[0002] Bidirectional thyristors are a typical example of thyristor products. Structurally, they consist of two traditional unidirectional thyristors connected in reverse parallel and integrated onto a single semiconductor chip. Compared to unidirectional thyristors, they offer advantages such as single-controller triggering, bidirectional conduction, and high reliability. With the booming development of my country's industrial manufacturing and processing industries, the demand for bidirectional thyristor devices is increasingly strong in products such as automotive electronics, motor control, lighting control, and home appliances.

[0003] Currently, existing bidirectional thyristors typically employ a process of growing multiple dielectric layers sequentially, glass passivation, and step-by-step etching. However, on the one hand, incomplete wiping before glass passivation can lead to glass powder settling on the silicon wafer surface, forming glass dots after passivation and sintering. The original step-by-step etching process, which first uses ammonium fluoride and hydrogen peroxide to etch the polycrystalline film and then the SIPOS protective layer, results in a long etching time. The glass dots generate significant heat during etching, which cannot be dissipated, leading to numerous pits on the silicon wafer surface, severely impacting product quality and reliability. On the other hand, the excessively long etching time weakens the photoresist's corrosion resistance, making it prone to detachment and reducing the thickness of the multiple dielectric layers on the chip surface, thus affecting the product's breakdown voltage. Summary of the Invention

[0004] To address the issue of surface corrosion pits affecting chip reliability in existing bidirectional thyristor wafers, this invention proposes a silicon wafer processing method, a silicon wafer, and a chip containing the silicon wafer.

[0005] The technical solution of the present invention is as follows:

[0006] A silicon wafer processing method includes the following steps:

[0007] S1. A SIPOS protective film is grown on the surface of a silicon wafer using CVD technology;

[0008] S2. Glass is grown in the glass bath of a silicon wafer using passivation technology;

[0009] S3. A thin oxide layer is grown on the surface of a silicon wafer using CVD technology;

[0010] S4. The pattern on the photoresist is transferred to the etched silicon wafer by a chemical reaction after being exposed to light.

[0011] S5. The silicon wafer is placed in SIPOS+ polycrystalline etching solution for one-step etching. The SIPOS+ polycrystalline etching solution is prepared from nitric acid, hydrofluoric acid and glacial acetic acid.

[0012] S6. After etching, the photoresist is removed and the wafer is cleaned to obtain a silicon wafer with the desired pattern on its surface.

[0013] Preferably, the thickness of the SIPOS protective film is 5400 angstroms to 6600 angstroms.

[0014] Preferably, the thickness of the oxide layer is 4000 angstroms to 6000 angstroms.

[0015] Preferably, the mass concentration of nitric acid in the SIPOS+ polycrystalline etching solution is 50%–60%, the mass concentration of hydrofluoric acid is 2.5%–3.5%, and the mass concentration of glacial acetic acid is 6%–8%.

[0016] Preferably, the corrosion time in step S5 is 60s to 120s.

[0017] Preferably, step S4 specifically includes the following steps:

[0018] S41. Place the chip in an oven to bake and remove surface moisture;

[0019] S42. Place the chip on a spin coater for dust removal, glue dispensing, spin coating, spin coating and back cleaning to form a layer of photoresist on the chip surface;

[0020] S43. Place the chip on the lithography machine stage for alignment and exposure;

[0021] S44. Remove the chip and place it on the developing machine. As the developing machine sprays out developing solution from the nozzle, the photoresist on the chip that has been exposed gradually dissolves, revealing the pattern on the photomask.

[0022] Preferably, the baking temperature in step S41 is 150°C and the baking time is 2 hours.

[0023] Preferably, the thickness of the photoresist in step S42 is 63,000 angstroms to 67,000 angstroms.

[0024] A silicon wafer, manufactured using the processing method described above.

[0025] A chip comprising a silicon wafer as described above.

[0026] Compared with existing technologies, this invention solves the problem of silicon surface etching pits affecting chip reliability, and the specific beneficial effects are as follows:

[0027] This invention improves the surface electric field and increases the surface breakdown voltage by growing a SIPOS protective film (containing polycrystalline silicon) of a certain thickness on the silicon surface. The oxide layer formed by CVD technology acts as a dielectric layer. The pattern on the photomask is transferred to the photoresist, facilitating the etching of the etched areas. Using a specially formulated etching solution, effective etching can be achieved in a single step, effectively improving the problem of etching pits on the silicon wafer surface during step etching, ensuring stable product reliability, thereby greatly improving chip quality, saving production cycle time and reducing production costs. It also solves the problem of photoresist peeling due to excessive etching time and improves the product breakdown voltage. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a cross-section after the SIPOS film has been grown on the surface of a silicon wafer.

[0029] Figure 2 A schematic diagram of the cross-section after glass has been grown inside a silicon wafer glass bath;

[0030] Figure 3 This is a schematic diagram of a cross-section after an oxide layer has been grown on the surface of a silicon wafer.

[0031] Figure 4 This is a schematic diagram of the cross-section of a silicon wafer after photolithography.

[0032] Figure 5 This is a schematic diagram of the cross-section of a silicon wafer after etching. Detailed Implementation

[0033] To make the technical solutions of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be noted that the following embodiments are only used to better understand the technical solutions of the present invention and should not be construed as limiting the present invention.

[0034] Example 1.

[0035] This embodiment provides a silicon wafer processing method, including the following steps:

[0036] S1. A SIPOS protective film is grown on the surface of a silicon wafer using CVD technology. (See...) Figure 1 As shown;

[0037] S2. Glass is grown within a glass bath on a silicon wafer using passivation technology, see... Figure 2 ;

[0038] S3. A thin oxide layer is grown on the surface of the silicon wafer using CVD technology, see... Figure 3 ;

[0039] S4. A chemical reaction occurs after the photoresist is exposed to light, transferring the pattern on the photomask to the etched silicon wafer, such as... Figure 4 As shown;

[0040] S5. The silicon wafer is placed in SIPOS+ polycrystalline etching solution for one-step etching. The SIPOS+ polycrystalline etching solution is prepared from nitric acid, hydrofluoric acid and glacial acetic acid.

[0041] S6. After etching, the photoresist is removed and the wafer is cleaned to obtain a silicon wafer with the desired surface pattern, such as... Figure 5 As shown.

[0042] This embodiment grows a SIPOS protective film (including polycrystalline silicon) of a certain thickness on the silicon surface. The SIPOS protective film can improve the surface electric field and increase the surface breakdown voltage. The oxide layer formed by CVD technology acts as a dielectric layer. The pattern on the photomask is transferred to the photoresist, which facilitates the etching of the etched area. A newly prepared etching solution is used for one-step etching, which effectively improves the problem of etching pits on the silicon wafer surface during step etching, improves chip quality, ensures product reliability and stability, saves production cycle and reduces production cost, solves the problem of photoresist peeling due to excessive etching time, and improves product breakdown voltage.

[0043] Example 2.

[0044] This embodiment is a further example of Embodiment 1, wherein the thickness of the SIPOS protective film is 5400 angstroms to 6600 angstroms.

[0045] Example 3.

[0046] This embodiment is a further example of Embodiment 1, wherein the thickness of the oxide layer is 4000 angstroms to 6000 angstroms.

[0047] Example 4.

[0048] This embodiment is a further example of Embodiment 1. In the SIPOS+ polycrystalline etching solution, the mass concentration of nitric acid is 50% to 60%, the mass concentration of hydrofluoric acid is 2.5% to 3.5%, and the mass concentration of glacial acetic acid is 6% to 8%.

[0049] The etching solution with specific components and formulation provided in this embodiment can achieve effective etching in just one step, effectively improving the problem of etching pits on the silicon wafer surface during step etching, ensuring stable product reliability, thereby greatly improving chip quality, saving production cycle and reducing production costs, solving the problem of photoresist peeling due to excessive etching time, and improving product breakdown voltage.

[0050] Example 5.

[0051] This embodiment is a further example of Embodiment 1, and the corrosion time in step S5 is 60s to 120s.

[0052] Example 6.

[0053] This embodiment is a further illustrative example of embodiment 1. Step S4 specifically includes the following steps:

[0054] S41. Baking the chip in an oven removes surface moisture and improves the adhesion between the photoresist and the chip.

[0055] S42. Place the chip on a spin coater for dust removal, glue dispensing, spin coating, spin coating and back cleaning to form a layer of photoresist on the chip surface;

[0056] S43. Place the chip on the lithography machine stage for alignment and exposure;

[0057] S44. Remove the chip and place it on the developing machine. As the developing machine sprays out developing solution from the nozzle, the photoresist on the chip that has been exposed gradually dissolves, revealing the pattern on the photomask.

[0058] Example 7.

[0059] This embodiment is a further example of embodiment 6. The baking temperature in step S41 is 150°C and the baking time is 2 hours.

[0060] Example 8.

[0061] This embodiment is a further example of embodiment 6, and the thickness of the photoresist in step S42 is 63,000 angstroms to 67,000 angstroms.

[0062] Example 9.

[0063] This embodiment provides a silicon wafer, which is processed using the processing method described in any one of Embodiments 1-8.

[0064] Example 10.

[0065] This embodiment provides a chip comprising a silicon wafer as described in Embodiment 9.

[0066] It should be understood that the application and design concept of this invention are not limited to the examples above. Any non-substantial modifications made to this invention using this concept shall be considered as infringing upon the protection scope of this invention. Any equivalent changes and modifications made to the above embodiments based on the technical essence of this invention, without departing from the scope of the technical solution of this invention, shall still fall within the protection scope of this invention.

Claims

1. A method of processing a silicon wafer, characterized by, Includes the following steps: S1. A SIPOS protective film is grown on the surface of a silicon wafer using CVD technology; S2. Glass is grown in the glass bath of a silicon wafer using passivation technology; S3. A thin oxide layer is grown on the surface of a silicon wafer using CVD technology; S4. The pattern on the photoresist is transferred to the etched silicon wafer by a chemical reaction after being exposed to light. S5. The silicon wafer is placed in SIPOS+ polycrystalline etching solution for one-step etching. The SIPOS+ polycrystalline etching solution is prepared from nitric acid, hydrofluoric acid and glacial acetic acid. S6. After etching, the photoresist is removed and the wafer is cleaned to obtain a silicon wafer with the desired pattern on the surface. The SIPOS+ polycrystalline etching solution contains 50% to 60% nitric acid, 2.5% to 3.5% hydrofluoric acid, and 6% to 8% glacial acetic acid.

2. The method of processing a silicon wafer of claim 1 wherein, The thickness of the SIPOS protective film is 5400 angstroms to 6600 angstroms.

3. The method of claim 1, wherein the step of forming the plurality of trenches is performed by a dry etching process. The thickness of the oxide layer is 4000 angstroms to 6000 angstroms.

4. The method of processing a silicon wafer of claim 1 wherein, The corrosion time in step S5 is 60s~120s.

5. The method of claim 1, wherein Step S4 specifically includes the following steps: S41. Place the chip in an oven to bake and remove surface moisture; S42. Place the chip on a spin coater for dust removal, glue dispensing, spin coating, spin coating and back cleaning to form a layer of photoresist on the chip surface; S43. Place the chip on the lithography machine stage for alignment and exposure; S44. Remove the chip and place it on the developing machine. As the developing machine sprays out developing solution from the nozzle, the photoresist on the chip that has been exposed gradually dissolves, revealing the pattern on the photomask.

6. The silicon wafer processing method according to claim 5, characterized in that, In step S41, the baking temperature is 150℃ and the baking time is 2 hours.

7. The method of processing a silicon wafer of claim 5 wherein, The thickness of the photoresist in step S42 is 63,000 angstroms to 67,000 angstroms.

8. A silicon wafer, characterized by It is processed using the processing method described in any one of claims 1-7.

9. A chip, characterized in that, It includes the silicon wafer as described in claim 8.

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