heat dissipating device

Abstract

Embodiments of this disclosure relate to a heat dissipation device. The heat dissipation device includes a substrate with a network having thermally conductive vias and a thermally conductive layer. The substrate has a first surface and a second surface opposite to the first surface. A heat dissipation interface layer includes a stack of a first layer made of a first thermally conductive material and a second layer made of a second thermally conductive material. The first material is different from the second material. The surface of the first layer is coplanar with the first surface of the substrate. At least one thermally conductive via of the network supports and contacts the first layer. At least one opening completely extends through the stack of the first and second layers. The material of the substrate fills the opening in the first layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to French patent application No. 2112736, filed on November 30, 2021, the entire contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to electronic systems and apparatuses, and more specifically, to apparatuses for dissipating heat generated by such electronic systems and apparatuses. Background Technology

[0004] Many techniques for cooling and dissipating heat generated by electronic systems and devices are known. For example, the use of substrates particularly suitable for dissipating heat generated by components and circuits of electronic devices or systems is known.

[0005] The goal is to at least partially improve the heat dissipation system of electronic devices.

[0006] More efficient heat dissipation devices are needed for electronic devices. Summary of the Invention

[0007] The embodiments described herein overcome all or some of the disadvantages of known heat dissipation devices.

[0008] One embodiment provides a heat dissipation device comprising: a substrate including a network of thermally conductive vias and a thermally conductive layer extending between a first surface of the substrate and a second surface of the substrate opposite to the first surface; and a heat dissipation interface layer comprising a stack of a first layer made of a first thermally conductive material and a second layer made of a second thermally conductive material, the first material being different from the second material. The surface of the first layer is coplanar with the first surface of the substrate. At least one of the thermally conductive vias of the network contacts the first layer. The stack includes at least one opening completely through the first and second layers. A material of the substrate fills at least one opening in the first layer.

[0009] According to one embodiment, the first thermally conductive material is copper or an alloy containing copper.

[0010] According to one implementation scheme, the second thermally conductive material is selected from: nickel-gold (NiAu), nickel-palladium-gold (NiPdAu), nickel-containing alloys, gold-containing alloys, palladium-tin-containing alloys, tin-containing alloys, alloys for welding such as alloys containing tin, silver and copper, ENIG (electro-free nickel-plated gold) type alloys, ENEPIG (electro-free nickel-palladium-plated gold) type alloys, and OSP (organic surface protection) type organic materials.

[0011] According to one embodiment, the opening has a cylindrical shape.

[0012] According to one embodiment, the opening has a cylindrical shape, which has a polygonal, rectangular, square, oblong, elliptical, or circular base.

[0013] According to one embodiment, the at least one opening includes at least two openings that extend completely through the stack.

[0014] According to one embodiment, the at least two openings have the same size.

[0015] According to one embodiment, the at least two openings have different sizes.

[0016] According to one embodiment, the at least one opening includes a plurality of openings that completely span the stack and are arranged in an array.

[0017] According to one embodiment, the device further includes a lower thermally conductive layer disposed on a second surface of the substrate.

[0018] Another embodiment provides an electronic device including the aforementioned heat dissipation device, and an electronic chip assembled on the heat dissipation device.

[0019] According to one embodiment, the electronic chip includes a fourth surface bonded to a fifth surface of the heat dissipation interface layer opposite to the substrate.

[0020] According to one embodiment, the fourth surface is bonded to the fifth surface by an adhesive layer. Attached Figure Description

[0021] The foregoing features and advantages, as well as other features and advantages, will be set forth in the following detailed description of embodiments by way of illustration rather than limitation, with reference to the accompanying drawings, in which:

[0022] Figure 1 A simplified cross-sectional view of an embodiment of the electronic device is shown;

[0023] Figure 2 It shows Figure 1 A more detailed top view of a part of the device; and

[0024] Figure 3 It shows Figure 1 A more detailed cross-sectional view of a part of the device. Detailed Implementation

[0025] In the various figures, the same features are indicated by the same reference numerals. In particular, common structural and / or functional features in the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0026] For clarity, only the steps and elements useful for understanding the embodiments described herein are shown and described in detail.

[0027] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements connected together, it means that the two elements can be connected or they can be coupled through one or more other elements.

[0028] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or when referring to relative position qualifiers, such as the terms "up", "down", "above", "below", etc., or when referring to orientation qualifiers, such as "horizontal", "vertical", etc., the orientation shown in the figure is used.

[0029] Unless otherwise stated, the expressions “about,” “approximately,” “basically,” and “in the order of” indicate within 10%, preferably within 5%.

[0030] Figure 1 This is a cross-sectional view of an embodiment of an electronic device 100 including an electronic integrated circuit chip 102 assembled on a heat dissipation device 104.

[0031] Chip 102 in Figure 1 The image is schematically represented by a rectangular block. Chip 102 includes various electronic circuits and components that may generate heat during its operation. More specifically, chip 102 may generate heat in different hot spots, at least one of which is located on one of its surfaces 106, which is the surface to which chip 102 is attached to heat dissipation device 104. Here, a hot spot refers to a portion of the surface of chip 102 that emits heat during operation of chip 102. Chip 102 may include other hot spots located on surfaces other than surface 106.

[0032] Chip 102 may also include one or more (typically multiple) contacts 108 formed on surface 110 opposite surface 106. For example, contacts 108 are used for coupling to other contacts of other electronic devices, for example, via solder wires. Figure 1 The image shows two contacts 108, and only two portions of the solder wires bonded to these contacts 108 are shown. According to one example, the solder wires are bonded using a wire bonding method.

[0033] The heat dissipation device 104 includes a substrate 114 made of an electrically insulating material. According to one example, the electrically insulating material may be selected from the group consisting of electrically insulating resins, mixtures of electrically insulating resins, glass fibers, mixtures of glass fibers, and mixtures of resins and glass fibers. The substrate 114 may also be a printed circuit board or a laminated substrate comprising stacks of different materials. The substrate 114 includes an upper surface 116 and a lower surface 118 opposite to the upper surface 116. The upper surface 116 is covered with an adhesive layer 120, and the lower surface 118 is covered with a protective layer.

[0034] According to one embodiment, device 104 further includes a heat dissipation interface layer 124. Figure 1 (as shown in the shaded area), the heat dissipation interface layer 124 is formed from the surface 116 of the substrate 114 and within a cavity formed in the adhesive layer 120. Figure 2 and 3 The interface layer 124 is described in more detail.

[0035] Device 104 also includes a lower heat-dissipating layer 126 extending at the level of surface 118 of substrate 114 and within a cavity formed in protective layer 122. Layer 126 is preferably located below layer 124 and may have, for example, a larger surface area than layer 124. Layer 126 is made of, for example, a metallic material, such as an alloy comprising nickel and / or gold, or another thermally conductive metal alloy. Layer 126 may be placed on thermally conductive balls 128, such as metal balls, like solder balls.

[0036] Device 104 also includes an array of thermally conductive vias 130 and thermally conductive traces 132 for thermally coupling layers 124 and 126. More specifically, at least one via 130 or one conductive track 132 of the network contacts layer 124, and at least one via 130 or one conductive track 132 contacts layer 126. The vias 130 and tracks 132 are, for example, further conductive. The vias 130 and tracks 132 are made of, for example, a metallic material, such as a metal like copper, or a metal alloy such as an alloy comprising copper. The vias 130 and / or metal tracks 132 contact the interface layer 124, while another via and / or another metal track 132 contacts the underlying layer 128. According to another embodiment, the network of vias 130 and tracks 132 can be replaced by a single conductive via.

[0037] The chip 102 is assembled onto the device 104 by bonding the surface 106 of the chip 102 to the upper surface 133 of the heat dissipation interface layer 124, i.e., to the free surface of the interface layer 124 opposite the substrate 114. For this purpose, the chip 102 is bonded to the interface layer 124, for example, via an adhesive layer 134. The adhesive layer 134 is adapted to conduct heat dissipated by hot spots of the chip 102.

[0038] When chip 102 is in operation and its hot spots generate heat, the heat is conducted sequentially through the interface layer 124, the network of vias 130 and tracks 132, the lower layer 126, and finally the ball 128, and is dissipated at the level of the “back side” of substrate 114, that is, on one side of its surface 118.

[0039] Figure 2 and 3 They are Figure 1 The layer 200 of the type 114 type substrate 204 at the surface 202 and therein formed about Figure 1 The description includes a top view and a cross-sectional view of a layer 200, which includes a topmost layer 132 and a heat dissipation interface layer 124. Figure 3 yes Figure 2 Cross-sectional view along axis AA.

[0040] Layer 200 is formed by stacking a first layer 206 made of a first thermally conductive material and a second layer 208 made of a second thermally conductive material. The first layer 206 extends from the surface 202 of the substrate 204. The first layer 206 corresponds to... Figure 1 The top layer is 132. The second layer 208 is located on top of the first layer. The second layer 208 corresponds to... Figure 1 Layer 124. According to one example, the first layer 206 has a thickness ranging from 8 μm to 35 μm, for example on the order of 17 μm. According to one example, the second layer 208 has a thickness ranging from 4 μm to 12 μm, for example on the order of 8 μm.

[0041] According to one embodiment, layers 206 and 208 are metal layers. According to one embodiment, the first thermally conductive material is copper or a copper-containing alloy. According to one embodiment, the second conductive material is selected from the group consisting of: nickel-gold (NiAu), nickel-palladium-gold (NiPdAu), nickel-containing alloys, gold-containing alloys, palladium-tin alloys, tin-containing alloys, alloys for soldering such as alloys containing tin, silver, and copper, ENIG (electro-free nickel-plated gold) type alloys, ENEPIG (electro-free nickel-palladium-plated gold) type alloys, and OSP (organic surface protectant) type organic materials.

[0042] According to one embodiment, layers 206 and 208 include at least one opening 210 that completely passes through layers 206 and 208. This opening 210 may have, for example, a cylindrical shape with a rectangular or square base, but according to alternative embodiments, it may have a rectangular, elliptical, circular, or polygonal base. Figure 3As shown, at the level of opening 210, the substrate 204 fills the opening in layer 206 (so that the substrate 204 is not recessed relative to layer 206). Several rules can be considered for the placement of opening 210. A first rule is that opening 210 is not located where it might contact vias or thermal tracks of the substrate 204's network. A second alternative rule is that opening 210 is not located where it might contact hot spots of the electronic chip.

[0043] According to an embodiment, the stack includes a plurality of openings 210 distributed on the surface of layer 200. Different openings 210 may have different shapes and sizes and may be arranged to conform to previously defined positioning rules. Figure 2 In the diagram, the circle represents the via 103 of the network in substrate 200 located directly below layer 206. Figure 1 The position in the top layer (132).

[0044] Layer 200, having layers 206 and 208, may include all the space, i.e., the space without opening 210 at the hot spot level of the chip, and the space at the location where minimal heat is generated. The solid portion of layer 200 has approximately 20 mm. 2 The maximum surface area.

[0045] according to Figure 2 In the preferred embodiment shown, the stack includes a plurality of rectangular or square openings 210 arranged in an array. The openings 210 can be arranged with a pitch ranging from 305 to 585 μm relative to each other and have a width ranging from 120 to 400 μm. The openings 210 can be spaced approximately 185 μm apart. By using this type of dimensioning, the surface of layer 200 can cover 50–85% of the chip surface area assigned to it.

[0046] The advantage of using a layer 200 having one or more openings 210 is that such a layer 200 has better bonding to the substrate 204 (see reference). Figure 1 (114), that is, better adhesion to the substrate 204 (as opposed to the metal that only bonds to layer 208).

[0047] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to them. Adjusting the size and shape of the opening 210 to optimize the bonding of layer 200 on substrate 204 and the heat dissipation of the electronic chip will be within the capabilities of those skilled in the art.

[0048] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

Claims

1. A heat dissipation device, comprising: An insulating substrate having a first surface and a second surface and including a network of thermally conductive vias; A heat dissipation interface comprises a stack of a first layer made of a first thermally conductive material and a second layer made of a second thermally conductive material, wherein the first thermally conductive material is different from the second thermally conductive material; The first layer, made of the first thermally conductive material, is located in the first surface of the insulating substrate and has an upper surface that is coplanar with the first surface of the insulating substrate, and also has a lower surface that is in contact with the network of the thermally conductive vias; The stack includes at least one opening that completely penetrates both the first layer and the second layer; and The at least one opening in the first layer is filled with the material of the insulating substrate.

2. The apparatus of claim 1, wherein the first thermally conductive material is copper or an alloy containing copper.

3. The apparatus of claim 1, wherein the second thermally conductive material is selected from the group consisting of: nickel-gold, nickel-palladium-gold, nickel-containing alloys, gold-containing alloys, palladium-tin-containing alloys, tin-containing alloys, soldering alloys such as those containing tin, silver, and copper, electroless nickel-plated gold (ENIG) type alloys, electroless nickel-palladium-plated gold (ENEPIG) type alloys, and organic surface protection (OSP) type organic materials.

4. The apparatus of claim 1, wherein the at least one opening has a cylindrical shape.

5. The apparatus of claim 4, wherein the cylindrical shape has a polygonal, rectangular, square, oblong, elliptical, or circular base.

6. The apparatus of claim 1, wherein the at least one opening comprises at least two openings that completely penetrate the first and second layers of the stack.

7. The apparatus of claim 6, wherein the at least two openings have the same size.

8. The apparatus of claim 6, wherein the at least two openings have different sizes.

9. The apparatus of claim 1, wherein the at least one opening comprises a plurality of openings arranged in an array.

10. The apparatus of claim 1, further comprising a lower thermally conductive layer disposed in the second surface of the substrate and having a lower surface coplanar with the second surface of the substrate, wherein the lower thermally conductive layer is thermally coupled to the network of thermally conductive vias.

11. An electronic device comprising: Heat dissipation device, including: An insulating substrate having a first surface and a second surface and including a network of thermally conductive vias; A heat dissipation interface comprises a stack of a first layer made of a first thermally conductive material and a second layer made of a second thermally conductive material, wherein the first thermally conductive material is different from the second thermally conductive material; The first layer, made of the first thermally conductive material, is located in the first surface of the insulating substrate and has an upper surface that is coplanar with the first surface of the insulating substrate, and also has a lower surface that is in contact with the network of the thermally conductive vias; The stacking includes at least one opening that extends completely through both the first layer and the second layer; and The at least one opening in the first layer is filled with the material of the insulating substrate; and An electronic chip is mounted to the heat dissipation device by means of an adhesive material that fills at least one opening in the second layer to contact the material of the insulating substrate that fills at least one opening in the first layer.

12. The apparatus of claim 11, wherein the electronic chip is bonded to the surface of the second layer of the heat dissipation interface layer.

13. The apparatus of claim 11, wherein the adhesive material is an adhesive layer.

14. The apparatus according to claim 11: Wherein the first thermally conductive material is copper or an alloy containing copper; and The second thermally conductive material is selected from the group consisting of: nickel-gold, nickel-palladium-gold, alloys containing nickel, alloys containing gold, alloys containing palladium and tin, alloys containing tin, alloys for welding such as alloys containing tin, silver and copper, electroless nickel-plated gold (ENIG) type alloys, electroless nickel-palladium-plated gold (ENEPIG) type alloys, and organic surface protection (OSP) type organic materials.

15. The apparatus of claim 11, further comprising a lower thermally conductive layer disposed in the second surface of the substrate and having a lower surface coplanar with the second surface of the substrate, wherein the lower thermally conductive layer is thermally coupled to the network of thermally conductive vias.

16. The apparatus of claim 15, further comprising: A protective layer is located on the second surface of the substrate; The protective layer includes a cavity at the lower thermally conductive layer; as well as The lower heat dissipation layer is located inside the cavity and in contact with the lower heat-conducting layer.

17. The apparatus of claim 11, further comprising: A protective layer is provided at the first surface of the substrate; as well as The protective layer includes a cavity in the first layer made of the first thermally conductive material; The second layer, made of a second thermally conductive material, and the electronic chip are located inside the cavity.

Images