A method for forming alignment marks in a semiconductor device and the semiconductor device.

Abstract

This invention provides a method for forming alignment marks in a semiconductor device, comprising: etching a semiconductor substrate to form a plurality of first trenches; laterally etching to interconnect the bottoms of the plurality of first trenches to form a second trench, the second trench being wider than the first trenches; and forming a first epitaxial layer through at least one epitaxial process to close the tops of the first trenches, forming a cavity in the second trench to form an alignment mark. The method of this invention makes it easy to close the tops of the trenches through epitaxial processes, forming a mid-space gap, and also expands the scale of the interface between the epitaxial layer and the air, thereby improving signal detection intensity, enhancing the detection effect of the alignment mark, and making it more suitable for practical applications.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming alignment marks in a semiconductor device and a semiconductor device thereof. Background Technology

[0002] A CMOS image sensor (CIS) is a semiconductor device that converts optical images into electrical signals. A CIS consists of a photodiode (PD) for sensing light and logic circuitry for processing the sensed light into electrical signals.

[0003] In existing semiconductor processes, alignment marks for photolithography are typically formed on the substrate surface first (e.g., individual alignment marks, or alignment mark patterns within the active region mask) as a starting step before other steps are performed. However, CIS (Content Injection System) is for processes like CIS that require epitaxy before the formation of the active region. After epitaxy is completed, the shallow alignment marks are affected by the planarization process, leading to attenuation or disappearance of the alignment signal.

[0004] Furthermore, in a common method, the trench can be sealed using an epitaxial process, leaving a hollow gap within the trench. The boundary of the hollow cavity serves as the alignment interface, which requires a relatively fine linewidth in the trench. However, with a fine linewidth, detecting the interface information is quite difficult. On the other hand, if the linewidth is increased, it becomes difficult to form a hollow gap within the trench. Therefore, the alignment marks formed by this method are not ideal. Summary of the Invention

[0005] The purpose of this invention is to provide a method for forming alignment marks in a semiconductor device, specifically, the method includes: Etching the semiconductor substrate forms multiple first trenches; By lateral etching, the bottoms of several first trenches are interconnected to form a second trench, the second trench being wider than the first trench. The first epitaxial layer is formed by at least one epitaxial process, the top of the first trench is closed, a cavity is formed in the second trench, and an alignment mark is formed.

[0006] Further, the step of forming a first epitaxial layer through at least one epitaxial process to seal the top of the first trench and form a cavity in the second trench includes: A dielectric layer is formed on the surface of the second trench to seal the top of the first trench and form a cavity in the second trench; The top of the dielectric layer is etched to open the dielectric layer at the top of the first trench; At least one epitaxial process is performed on the surface of the first trench to close the top of the first trench and form a cavity in the second trench. Furthermore, after sealing the top of the first trench and forming a cavity in the second trench, the method further includes: After thinning the back side of the semiconductor substrate, the interface between the first epitaxial layer and the cavity is used as the alignment mark for the back side process.

[0007] Furthermore, the etching of the semiconductor substrate to form a plurality of first trenches includes: According to the preset photolithography pattern, the semiconductor substrate is etched to form a plurality of third trenches; An oxide film is formed on the surface of the third trench to protect the sidewalls of the third trench; Continue etching the bottom of the third trench to deepen it, forming the first trench that is not interconnected.

[0008] Furthermore, when etching the semiconductor substrate to form multiple third trenches, a negative angle etching is used so that the opening linewidth of the third trench is smaller than the bottom linewidth.

[0009] Furthermore, the multiple first trenches have the same line width and length and are arranged in a rectangular array.

[0010] Further, the first epitaxial layer includes a first sub-epitaxy layer and a second sub-epitaxy layer, and the formation of the first epitaxial layer through at least one epitaxial process includes: Intrinsic semiconductors are epitaxially grown on the surfaces of the first trench and the second trench to form the first sub-epitaxy layer; A second sub-epitaxial layer is formed by epitaxially bonding semiconductor material on the surface of the first sub-epitaxial layer.

[0011] Furthermore, the doping type of the second sub-epipolar layer is opposite to that of the semiconductor substrate.

[0012] Furthermore, after forming the alignment mark, the process also includes: The surface of the semiconductor substrate is planarized. A device layer is epitaxially formed on the surface of the semiconductor substrate.

[0013] Furthermore, during the formation of the first trench and the second trench, the semiconductor substrate is simultaneously etched to form an array of semiconductor island structures, and each of the semiconductor island structures is interconnected at least at its upper part through at least one connection structure to reduce defects generated by subsequent epitaxial processes.

[0014] The present invention also provides a semiconductor device in which alignment marks are formed using the aforementioned semiconductor device alignment mark formation method.

[0015] Furthermore, the semiconductor device is an image sensor.

[0016] The present invention proposes a method for forming alignment marks in semiconductor devices through the above-mentioned scheme. By first etching finer trenches and then extending and connecting the trenches at the bottom, it is easy to close the top of the trenches through epitaxial processes to form a hollow gap, and the linewidth of the hollow cavity of the alignment pattern is increased, thereby improving the signal detection intensity, enhancing the detection effect of the alignment marks, and making it more conducive to practical applications. Attached Figure Description

[0017] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings.

[0018] Figure 1 This is a schematic diagram of the alignment mark formation process in the semiconductor device of the present invention; Figure 2 , Figure 3 This is a schematic diagram of the first trench arrangement shape in this invention; Figures 4-7 This is a schematic diagram of the alignment mark formation process in the semiconductor device of the present invention; Figure 8 This is a schematic diagram of the semiconductor island structure in this invention.

[0019] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Implementation

[0020] The present invention aims to provide a method for forming alignment marks in a semiconductor device. Specifically, the method includes the following steps: Step S1: As Figure 1 As shown, the semiconductor substrate 100 is etched to form a plurality of first trenches 110; In an optional embodiment, the plurality of first grooves 110 have the same line width and length and are arranged in a rectangular array; the specific arrangement is not limited in this invention. Figure 2 , Figure 3 The diagram shows the possible arrangements of multiple first grooves 110 in different embodiments of the present invention.

[0021] Preferably, such as Figure 1As shown, the semiconductor substrate 100 has a hard mask layer 101 on its surface. A first trench 110 can be formed by etching the hard mask layer 101 and the semiconductor substrate 100 using a preset photolithography pattern. The hard mask layer 101 may include one or more of oxides, nitrides, and oxide oxynitrides, and the present invention is not limited thereto.

[0022] Preferably, in step S1, a plurality of first trenches 110 can be formed by the following steps: Step S11: As Figure 4 As shown, according to the preset photolithography pattern, the semiconductor substrate 100 is etched to form a plurality of third trenches 130; Step S12: An oxide film 131 is formed on the surface of the third trench. The oxide film 131 can protect the sidewall of the third trench 130 and ensure that the trench linewidth is not too large during further etching. Step S13: Continue etching the bottom of the third trench 130 to deepen the third trench 130, forming the non-interconnected first trench 110, as shown. Figure 1 As shown.

[0023] Preferably, when etching the semiconductor substrate 100 to form a plurality of third trenches 130, negative angle etching can be used so that the opening linewidth of the third trench 130 is smaller than the bottom linewidth.

[0024] Step S2: As Figure 5 As shown, by lateral etching, the bottoms of several first trenches 110 are interconnected to form a second trench 120, the second trench 120 being wider than the first trenches 110. Step S3: As Figure 6 As shown, the first epitaxial layer 130 is formed by at least one epitaxial process, which closes the top of the first trench 110 and forms a cavity 121 in the second trench 120 to form an alignment mark.

[0025] Through the above steps, the present invention forms an alignment mark structure with a small upper opening linewidth and multiple "cantilever beams" connecting the bottoms of the two semiconductor substrates. This alignment mark can be etched into a small opening using existing masks with small linewidths, and because the bottom trench is relatively wide, the signal strength is sufficient, making it suitable for marking.

[0026] Preferably, in one embodiment, forming a cavity 121 in the second trench 120 in step S3 can be further achieved through the following steps: Step S31: A dielectric layer 122 is formed on the surface of the second trench 120 to close the top of the first trench 110 and form a cavity 121 in the second trench 120; Step S32: Etch the top of the dielectric layer 122 to open the dielectric layer 122 at the top of the first trench 110; Step S33: Perform at least one epitaxial process on the surface of the first trench 110 to form a first epitaxial layer 111, thereby closing the top of the first trench 110 and re-forming a cavity 121 in the second trench 120.

[0027] Furthermore, in one embodiment, after forming the cavity 121 in the second trench 120 in step S3, the back side of the semiconductor substrate 100 can be thinned. At this time, the interface between the first epitaxial layer 111 and the cavity 121 can be used as an alignment mark for the back side process.

[0028] In one embodiment, the first epitaxial layer 111 includes a first sub-epitaxy layer 112 and a second sub-epitaxy layer 113. In step S33, the first epitaxial layer 111 can be formed in the following manner: Step S331: Epitaxial intrinsic semiconductors are formed on the surfaces of the first trench 110 and the second trench 120 to form the first sub-epitaxy layer 112; Step S332: Epitaxially grow semiconductor material on the surface of the first sub-epitaxial layer 112 to form the second sub-epitaxial layer 113. Preferably, the doping type of the second sub-epitaxial layer 113 is opposite to that of the semiconductor substrate 100. If the semiconductor substrate 100 is P-type doped, the second sub-epitaxial layer 113 is N-type doped; if the semiconductor substrate 100 is N-type doped, the second sub-epitaxial layer 113 is P-type doped.

[0029] Furthermore, after forming the alignment mark in step S3, the following steps can also be performed: Step S41: The surface of the semiconductor substrate 100 is planarized; Step S42: As Figure 7 As shown, a device layer 200 is epitaxially formed on the surface of the semiconductor substrate 100.

[0030] Furthermore, in the semiconductor device of the present invention, an island-like structure can be formed in the semiconductor substrate 100 simultaneously with the formation of alignment marks. Specifically, as shown... Figure 8 As shown, in one embodiment, while forming the first trench 110 and the second trench 120, the semiconductor substrate 100 is simultaneously etched to form an array of semiconductor island structures 140, and each of the semiconductor island structures 140 is interconnected at least at its upper part by at least one connection structure 141. This structure can reduce defects generated by subsequent epitaxial processes. As shown, the connection structure can be suspended.

[0031] Based on this, one embodiment of the present invention provides a semiconductor device in which alignment marks are formed using the alignment mark formation method described above in the semiconductor device formation process. Further, the semiconductor device can be an image sensor. If semiconductor island structures are formed simultaneously with the formation of the alignment marks, these island structures can be used as the photosensitive areas of the pixel units of the image sensor.

[0032] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plural. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.

Claims

1. A method for forming alignment marks in a semiconductor device, characterized in that, include: Etching the semiconductor substrate forms multiple first trenches; By lateral etching, the bottoms of several first trenches are interconnected to form a second trench, the second trench being wider than the first trench. The first epitaxial layer is formed by at least one epitaxial process, the top of the first trench is closed, and a cavity is formed in the second trench to form an alignment mark; The step of forming a first epitaxial layer through at least one epitaxial process to seal the top of the first trench and form a cavity in the second trench includes: A dielectric layer is formed on the surface of the second trench to seal the top of the first trench and form a cavity in the second trench; The top of the dielectric layer is etched to open the dielectric layer at the top of the first trench; At least one epitaxial process is performed on the surface of the first trench to close the top of the first trench and form a cavity in the second trench.

2. The method for forming alignment marks in a semiconductor device as described in claim 1, characterized in that, After sealing the top of the first trench and forming a cavity in the second trench, the method further includes: After thinning the back side of the semiconductor substrate, the interface between the first epitaxial layer and the cavity is used as the alignment mark for the back side process.

3. The method for forming alignment marks in a semiconductor device as described in claim 1, characterized in that, The etching of the semiconductor substrate forms a plurality of first trenches, including: According to the preset photolithography pattern, the semiconductor substrate is etched to form a plurality of third trenches; An oxide film is formed on the surface of the third trench to protect the sidewalls of the third trench; Continue etching the bottom of the third trench to deepen it, forming the first trench.

4. The method for forming alignment marks in a semiconductor device as described in claim 3, characterized in that, When etching the semiconductor substrate to form multiple third trenches, a negative angle etching is used so that the opening linewidth of the third trench is smaller than the bottom linewidth.

5. The method for forming alignment marks in a semiconductor device as described in claim 1, characterized in that, The multiple first trenches have the same line width and length and are arranged in a rectangular array.

6. The method for forming alignment marks in a semiconductor device as described in claim 1, characterized in that, The first epitaxial layer includes a first sub-epitaxy layer and a second sub-epitaxy layer, wherein forming the first epitaxial layer through at least one epitaxial process includes: Intrinsic semiconductors are epitaxially grown on the surfaces of the first trench and the second trench to form the first sub-epitaxy layer; A second sub-epitaxial layer is formed by epitaxially bonding semiconductor material on the surface of the first sub-epitaxial layer.

7. The method for forming alignment marks in a semiconductor device as described in claim 6, characterized in that, The doping type of the second sub-epipolar layer is opposite to that of the semiconductor substrate.

8. The method for forming alignment marks in a semiconductor device as described in claim 1, characterized in that, After forming the alignment mark, the method further includes: The surface of the semiconductor substrate is planarized. A device layer is epitaxially formed on the surface of the semiconductor substrate.

9. The method for forming alignment marks in a semiconductor device as described in claim 1, characterized in that, During the formation of the first trench and the second trench, the semiconductor substrate is simultaneously etched to form an array of semiconductor island structures, and each of the semiconductor island structures is interconnected at least at its upper part through at least one connection structure to reduce defects generated by subsequent epitaxial processes.

10. A semiconductor device, characterized in that, Alignment marks are formed in the semiconductor device using the alignment mark formation method described in claims 1 to 9.

11. The semiconductor device as claimed in claim 10, characterized in that, The semiconductor device is an image sensor.

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