Semiconductor package

Abstract

A semiconductor package includes a first substrate, a first electronic component disposed on the first substrate, a second substrate disposed on the first substrate and provided with a cavity disposed in one surface of the second substrate, a first connection member connecting the first substrate and the second substrate to each other, a heat dissipation structure disposed on the second substrate and spaced apart from the first connection member, a second connection member disposed on the second substrate, and a via disposed on the second substrate, spaced apart from the heat dissipation structure, and connected to the first connection member. The second substrate includes a first area in which the cavity is disposed and a second area connected to the first substrate, and the heat dissipation structure is disposed in each of the first area and the second area of the second substrate.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2021-0168597, filed with the Korean Intellectual Property Office on November 30, 2021, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0002] This disclosure relates to a semiconductor package. Background Technology

[0003] In response to the recent trend of lightweighting and miniaturization of mobile devices, there is an increasing demand for achieving lightweight, thin, and compactness in semiconductor packages installed in mobile devices.

[0004] On the other hand, as mobile devices become lighter, thinner, and smaller, in response to these technological demands, there is a need for technologies that allow electronic components (such as integrated circuits (ICs), active or passive devices) to be embedded into boards in order to shorten the connection paths between electronic components and reduce noise. Research into technologies for embedding components into substrates in various ways has been ongoing in recent years.

[0005] In detail, as the thickness of semiconductor packages decreases, methods for effectively dissipating the heat generated by semiconductor chips are continuously discussed. Summary of the Invention

[0006] This summary is provided to introduce the selected concept in a simplified form, and the concept is further described below in detail in the specific embodiments. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to help determine the scope of the claimed subject matter.

[0007] One aspect of this disclosure is to provide a semiconductor package including microcircuits and / or microvias.

[0008] One aspect of this disclosure is to provide a semiconductor package that can effectively dissipate heat generated by a semiconductor chip.

[0009] According to one aspect of this disclosure, a semiconductor package includes: a first substrate on which a first electronic component is disposed on a surface; a second substrate disposed on the first substrate and having a cavity disposed in a surface of the second substrate; and a via penetrating the second substrate. The second substrate includes a first region in which the cavity is disposed and a second region connected to the first substrate. The via is disposed in each of the first and second regions of the second substrate.

[0010] According to another aspect of this disclosure, a semiconductor package includes: a first substrate on which a first electronic component is disposed; a second substrate disposed on the first substrate; and a heat dissipation structure disposed on the second substrate, wherein a step is disposed on one surface of the second substrate, and the heat dissipation structure includes a plurality of metal layers in the region where the step is disposed. Attached Figure Description

[0011] The above and other aspects, features and advantages of the present invention will be more clearly understood by taking into account the accompanying drawings and the following detailed description, in which:

[0012] Figure 1 This is a schematic block diagram illustrating an example of an electronic device system;

[0013] Figure 2 This is a schematic perspective view showing an example of an electronic device;

[0014] Figure 3 This is a schematic diagram illustrating an example of a semiconductor package according to an embodiment;

[0015] Figure 4A and Figure 4B This is a schematic diagram illustrating an example of a semiconductor package according to an embodiment; Figure 5 The diagram schematically illustrates an example of a semiconductor package according to an embodiment; and

[0016] Figure 6A and Figure 6B This is a schematic diagram illustrating an example of a semiconductor package according to an embodiment. Detailed Implementation

[0017] The following detailed embodiments are provided to aid the reader in gaining a comprehensive understanding of the methods, apparatus, and / or systems described herein. However, various modifications, variations, and equivalents of the methods, apparatus, and / or systems described herein will be readily understood by those skilled in the art. The order of operations described herein is merely illustrative and is not limited to the order set forth herein; changes that will be readily understood by those skilled in the art may be made, except for operations that must occur in a specific order. Furthermore, for clarity and brevity, descriptions of functions and constructions well-known to those skilled in the art may be omitted.

[0018] The features described herein may be implemented in various forms and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0019] It should be noted here that the use of the term "may" in relation to an embodiment or example (e.g., what an embodiment or example may include or implement) means that there exists at least one embodiment or example that includes or implements such a feature, and is not limited to all embodiments or examples including or implementing such a feature.

[0020] Throughout the specification, when an element (such as a layer, region, or substrate) is described as being "on" another element, "connected" to another element, or "bonded" to another element, the element may be directly "on" said other element, directly "connected" to said other element, or directly "bonded" to said other element, or there may be one or more other elements in between. In contrast, when an element is described as being "directly on" another element, "directly connected" to another element, or "directly bonded" to another element, there are no other elements in between.

[0021] As used herein, the term “and / or” includes any one of the relevant listed items or any combination of any two or more items.

[0022] Although terms such as “first,” “second,” and “third” may be used herein to describe various components, assemblies, regions, layers, or parts, these components, assemblies, regions, layers, or parts are not limited by these terms. Rather, these terms are used only to distinguish one component, assembly, region, layer, or part from another. Therefore, without departing from the teaching of the examples described herein, the first component, first assembly, first region, first layer, or first part mentioned in the examples may also be referred to as the second component, second assembly, second region, second layer, or second part.

[0023] For ease of description, spatial relative terms such as “above,” “above,” “below,” and “under” are used herein to describe the relationship between one element and another as shown in the accompanying drawings. Such spatial relative terms are intended to include not only the orientation depicted in the drawings but also the different orientations of the device during use or operation. For example, if the device in the drawings is flipped, an element described as being “above” or “above” relative to another element will then be “below” or “under” relative to that other element. Therefore, the term “above” includes both “above” and “below” orientations depending on the spatial orientation of the device. The device may also be positioned in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative terms used herein will be interpreted accordingly.

[0024] The terminology used herein is for the purpose of describing various examples only and is not intended to limit this disclosure. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well. The terms “comprising,” “including,” and “having” enumerate the presence of the stated features, quantities, operations, components, elements, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof.

[0025] The shapes shown in the accompanying drawings may change due to manufacturing techniques and / or tolerances. Therefore, the examples described herein are not limited to the specific shapes shown in the accompanying drawings, but may include changes in shape that occur during manufacturing.

[0026] The features of the examples described herein can be combined in a variety of ways that will be readily understood after gaining an understanding of the disclosure of this application. Furthermore, although the examples described herein have various configurations, other configurations that will be readily understood after gaining an understanding of the disclosure of this application are possible.

[0027] The accompanying drawings may not be drawn to scale, and for clarity, illustration and convenience, the relative sizes, scales and depictions of the elements in the drawings may be exaggerated.

[0028] Electronic devices

[0029] Figure 1 This is a schematic block diagram illustrating an example of an electronic device system.

[0030] Reference Figure 1 The electronic device 1000 can house the motherboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 can be physically and / or electrically connected to the motherboard 1010. These components can be connected to other electronic components described below via various signal lines 1090.

[0031] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processing units (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, chip-related components 1020 are not limited to these, but may also include other types of chip-related components. Furthermore, chip-related components 1020 can be combined with each other. Chip-related components 1020 may be in the form of a package including the chips described above.

[0032] Network-related components 1030 may include components that are compatible with or communicate using protocols such as: Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE, Ev-DO (evolution-data only, an evolution of CDMA 2000 1x), HSPA+, HSDPA+, HSUPA+, EDGE+, GSM, GPS, GPRS, CDMA, TDMA, DECT, WLAN, Bluetooth, 3G, 4G, and 5G protocols, as well as any other wireless and wired protocols specified after the protocols listed above. However, the network-related component 1030 is not limited to this, but may also include components that are compatible with or communicate using various other wireless or wired standards or protocols. Furthermore, the network-related component 1030 may be combined with the chip-related component 1020 described above.

[0033] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these, and may also include passive components for various other purposes. Furthermore, other components 1040 may be combined with each other in conjunction with the chip-related components 1020 or network-related components 1030 described above.

[0034] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the motherboard 1010 or not physically and / or electrically connected to the motherboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc., but are not limited thereto. For example, other electronic components may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage units (e.g., hard disk drives), optical disc (CD) drives, digital versatile optical disc (DVD) drives, etc. Furthermore, other electronic components may include other electronic components used for various purposes depending on the type of electronic device 1000.

[0035] Electronic device 1000 can be a smartphone, personal digital assistant (PDA), digital video camera, digital camera, network system, computer, monitor, tablet PC, laptop PC, netbook PC, television, video game console, smartwatch, automotive component, etc. However, electronic device 1000 is not limited to these and can be any other electronic device used for processing data.

[0036] Figure 2 This is a schematic perspective view showing an example of an electronic device.

[0037] Reference Figure 2 The electronic device can be, for example, a smartphone 1100. A motherboard 1110 is housed in the smartphone 1100, and various electronic components 1120 are physically and / or electrically connected to the motherboard 1110. Furthermore, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected, or not physically and / or electrically connected, to the motherboard 1110 may be housed in the electronic device. Some of the electronic components in the electronic components 1120 may be chip-related components as described above (e.g., an antenna module 1121), but are not limited thereto. The antenna module 1121 may be in the form of an electronic component surface-mounted on a semiconductor package, but this disclosure is not limited thereto. On the other hand, the electronic device is not necessarily limited to the smartphone 1100, and can also be other electronic devices as described above.

[0038] Semiconductor packages

[0039] Figure 3 This is a schematic diagram illustrating an example of a semiconductor package 10A according to an embodiment.

[0040] Reference Figure 3 The semiconductor package 10A according to an embodiment may include: a first substrate 100, on which a first electronic component D1 is disposed; a second substrate IS, disposed on the first substrate 100, and in which a cavity C is formed; and a heat dissipation structure 500 extending through the second substrate IS. At least a portion of the heat dissipation structure 500 may be disposed in the second substrate IS. In this case, the first substrate 100 and the second substrate IS may be connected to each other by a first connecting member 410 including metal (such as solder), the first connecting member 410 being spaced apart from the heat dissipation structure 500. Furthermore, the semiconductor package 10A according to an embodiment may also include: a second connecting member 420 including metal (such as solder), disposed on the second substrate IS; and a via V disposed in the second substrate IS, spaced apart from the heat dissipation structure 500 and connected to the first connecting member 410.

[0041] Furthermore, the second substrate IS may include a first region R1 in which a cavity C is formed and a second region R2 connected to the first substrate 100, and a heat dissipation structure 500 may be disposed in each of the first region R1 and the second region R2 of the second substrate IS. For example, the heat dissipation structure 500 extending through the second substrate IS may include the region in which the cavity C is formed and may be formed to extend to its outer periphery. In addition, a via V may be disposed in the second region R2 and may extend through the opening of the heat dissipation structure 500 in the second region R2. In this case, it can be seen that the heat dissipation structure 500 and the via V disposed in the second substrate IS are insulated from each other, such that the heat dissipation structure 500 has a structure and function different from that of the via V connecting the signal pattern.

[0042] The heat dissipation structure 500, which penetrates or extends through the second substrate IS, can be used as a heat dissipation via to dissipate heat generated by the electronic components, and the heat dissipation effect can be further improved by widening the area around the first electronic component D1 where the heat dissipation structure 500 is formed (as described above). In one example, when viewed in the stacking direction of the first substrate 100 and the second substrate IS, the heat dissipation structure 500 may be disposed above or stacked with the first electronic component D1.

[0043] At least a portion of the first electronic component D1 in the semiconductor package 10A according to the embodiment may be disposed in the cavity C of the second substrate IS, and the first electronic component D1 may be a passive electronic component, an active electronic component, a semiconductor die, a chip electronic component, etc., but is not limited thereto. For example, the first electronic component D1 may represent a known component, as long as it is an electronic component of the type that can be mounted on a printed circuit board.

[0044] Furthermore, the semiconductor package 10A according to the embodiment may also include: a molding material 300 disposed inside the cavity C of the second substrate IS, and sealing or embedding the first electronic component D1; and a third substrate 200 connected to the second substrate IS. In this case, the second electronic component D2 may be disposed on one surface of the third substrate 200.

[0045] The second electronic component D2 can be a passive electronic component, an active electronic component, a semiconductor die, a chip electronic component, etc., but is not limited to these. For example, the second electronic component D2 can represent a known component, as long as it is an electronic component that can be mounted on a printed circuit board.

[0046] According to an embodiment, the first substrate 100, the second substrate 15, and the third substrate 200 of the semiconductor package 10A may each include at least one insulating layer, a circuit layer, and a via. In this case, the insulating layer may include known insulating materials, but its material is not limited thereto. More specifically, thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimides), or materials prepared by impregnating inorganic fillers together with a core material (such as glass fiber (glass cloth, glass fabric)) in a thermosetting or thermoplastic resin (e.g., prepreg, Ajinomoto Build-up Film (ABF), FR-4, or bismaleimide triazine (BT)) can be used as the insulating layer material.

[0047] Furthermore, conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), palladium (Pd), or alloys thereof can be used as the material for each of the circuit layer, the heat dissipation structure 500, and the via V, but are not limited thereto. In this case, the via V may correspond to a via penetrating at least a portion of the insulating layer of each of the first substrate 100, the second substrate 11, and the third substrate 200.

[0048] Furthermore, the circuit layer, heat dissipation structure 500, and via V of the semiconductor package 10A according to the embodiment can be formed by a plating process, and in this case, an electroless plating layer and an electrolytic plating layer may be included. The electroless plating layer can be used as a seed layer for the electrolytic plating layer, but this disclosure is not limited thereto.

[0049] In this case, the electroless and electrolytic plating layers of the filling circuit layer, heat dissipation structure 500 and via V may also include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), palladium (Pd) or alloys thereof.

[0050] In the semiconductor package 10A according to an embodiment, a circuit layer is formed on one surface of an insulating layer disposed on its outermost layer. At least a portion of the circuit layer may include a surface treatment layer, and the surface treatment layer may include a component different from the component of each circuit layer. For example, each circuit layer may include copper (Cu), and the surface treatment layer may include nickel (Ni) or tin (Sn), but the construction is not limited thereto.

[0051] Furthermore, in the semiconductor package 10A according to the embodiment, a solder resist layer may also be provided to cover at least a portion of the circuit layer (including the surface treatment layer) formed on the outermost layer. In this case, the solder resist layer may be formed using a photosensitive material. Furthermore, the solder resist layer may have thermosetting and / or photocurable properties, but this disclosure is not limited thereto.

[0052] Furthermore, the first connecting member 410 connecting the first substrate 100 and the second substrate IS of the semiconductor package 10A according to the embodiment may correspond to a known solder bump. For example, the first connecting member 410 may include, but is not limited to, copper (Cu), nickel (Ni), gold (Au), indium (In), bismuth (Bi), or other non-reactive metals.

[0053] The first electronic component D1 disposed on the first substrate 100 and the second electronic component D2 disposed on the third substrate 200 may be embedded in the molding material 300. In this case, the molding material 300 may include known materials, for example, epoxy molding compound (EMC), but this disclosure is not limited thereto.

[0054] Figure 4A and Figure 4B This is a schematic diagram illustrating examples of semiconductor packages 10B and 10C according to embodiments.

[0055] Reference Figure 4A and Figure 4B In the semiconductor package 10B according to an embodiment, at least a portion of the heat dissipation structure 500 disposed in the second region R2 through the second substrate IS is exposed to the sidewall of the cavity C of the second substrate IS (to clearly show the variation of the heat dissipation structure, in Figure 4A and Figure 4B (Through-hole V is not shown). For example, the heat dissipation structure 500 disposed in the second region R2 of the second substrate IS may be disposed on the sidewall of the cavity C of the second substrate IS, but the construction is not limited thereto. In addition, the circuit layer extends in the lateral direction on the lower surface of the heat dissipation structure 500 and can be used as a heat transfer path, thereby improving the heat dissipation function.

[0056] As described above, since the heat dissipation structure 500 with heat dissipation function is exposed through the sidewall of cavity C, the heat generated by the first electronic component D1 is transferred outward more effectively, thereby improving the heat dissipation function of semiconductor package 10B.

[0057] In addition, refer to Figure 4BIn the semiconductor package 10C according to an embodiment, at least a portion of the heat dissipation structure 500 disposed in the second region R2 through the second substrate IS is exposed through the sidewall of the cavity C of the second substrate IS. In this case, the heat dissipation structure 500 disposed on the sidewall of the cavity C may have a shape that tapers gradually in the direction toward the third substrate 200 (described later). For example, the cross-section or size of the heat dissipation structure 500 exposed through the sidewall of the cavity C may be largest in the region closest to the first substrate 100. This corresponds to the structure obtained by performing processes such as laser drilling, CNC drilling, or sandblasting in the process of forming the cavity C in the second substrate IS, so that the sidewall penetrates the heat dissipation structure 500. Optionally, the cavity C may also be formed by plating and etching methods, but the formation method is not limited to these.

[0058] In addition, the circuit layer extends laterally on the lower surface of the heat dissipation structure 500 to serve as a heat transfer path, thereby improving heat dissipation.

[0059] As described above, since the heat dissipation structure 500 with heat dissipation function is exposed through the sidewall of cavity C, the heat generated by the first electronic component D1 is transferred outward more effectively, thereby improving the heat dissipation function of semiconductor package 10B.

[0060] The descriptions of the other components are largely the same as those mentioned above, and their detailed descriptions will be omitted.

[0061] Figure 5 This is a schematic diagram illustrating an example of a semiconductor package 10D according to an embodiment.

[0062] Reference Figure 5 In the semiconductor package 10D according to the embodiment, a molding material 300 may be included, wherein the first electronic component D1 is embedded in the molding material 300, and in this case, the heat dissipation structure 500 disposed on the second substrate IS may include a metal portion M that penetrates a portion of the molding material 300 and is spaced apart from the first electronic component D1.

[0063] For example, the heat dissipation structure 500 that penetrates the upper and lower surfaces of the second substrate IS may include a metal portion M protruding from the bottom surface of the cavity C, and the distance between the first electronic component D1 and the heat dissipation structure 500 with heat dissipation function may be reduced due to the metal portion M, so that heat can be dissipated more effectively.

[0064] However, the first electronic component D1 does not contact the metal part M, and a space of about 20 μm to 30 μm can be formed between them, but the structure is not limited to this.

[0065] The descriptions of the other components are largely the same as those mentioned above, and their detailed descriptions will be omitted.

[0066] Figure 6A and Figure 6B This is a schematic diagram illustrating examples of semiconductor packages 10E and 10F according to embodiments. For simplicity, in Figure 6A and Figure 6B The via V is not shown in the diagram.

[0067] Reference Figure 6A and Figure 6B According to an embodiment, the semiconductor package 10E may include: a first substrate 100 on which a first electronic component D1 is disposed; a second substrate IS disposed on the first substrate 100; and a heat dissipation structure 500 extending through the upper and lower surfaces of the second substrate IS. In this case, the semiconductor package 10E according to the embodiment may further include a first connecting member 410 connecting the first substrate 100 and the second substrate IS. In this case, a step may be formed on one surface of the second substrate IS, and the heat dissipation structure 500 may be configured with multiple metal layers in the region where the step is formed.

[0068] In detail, the semiconductor package 10E according to the embodiment may further include: a third substrate 200, a second electronic component D2 disposed on one surface of the third substrate 200; and a second connecting member 420 connecting the third substrate 200 and the second substrate IS. In this case, the second connecting member 420 may be spaced apart from the region where the step of the second substrate IS is formed. For example, the second substrate IS may include a region in which the second connecting member 420, which is connected to the third substrate 200, is disposed and a region in which the step is formed. In this case, the height of the region in which the step is formed may be higher than the height of the region in which the second connecting member 420 is disposed. For example, an insulating layer and a circuit layer may be disposed in the region in which the step is formed of the second substrate IS, such that the region in which the step is formed of the second substrate IS may be closer to the third substrate 200 than an external region (e.g., the region in which the second connecting member 420 is disposed).

[0069] The heat dissipation structure 500 can be disposed in multiple layers in a region formed above the outer periphery. The heat dissipation structure 500 extending through the second substrate IS can be used to dissipate heat generated by the electronic components, and as described above, the portion of the heat dissipation structure 500 adjacent to the region in which the first electronic component D1 is disposed can be extended to further improve the heat dissipation effect.

[0070] The first electronic component D1 of the semiconductor package 10E according to the embodiment may be a passive electronic component, an active electronic component, a semiconductor die, a chip electronic component, etc., but is not limited thereto. For example, the first electronic component D1 may represent a known component, as long as it is an electronic component that can be mounted on a printed circuit board.

[0071] Furthermore, in the semiconductor package 10E according to the embodiment, the second electronic component D2 may be disposed on one surface of the third substrate 200. The second electronic component D2 may be a passive electronic component, an active electronic component, a semiconductor die, a chip electronic component, etc., but is not limited thereto. For example, the second electronic component D2 may represent a known component, as long as it is an electronic component of the type that can be mounted on a printed circuit board.

[0072] According to an embodiment, the first substrate 100, the second substrate 15, and the third substrate 200 of the semiconductor package 10E may each include at least one insulating layer, a circuit layer, and a via. In this case, the insulating layer may include known insulating materials, but the material is not limited thereto. Specifically, thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or materials prepared by impregnating inorganic fillers together with a core material (such as glass fiber (glass cloth, glass fabric)) in a thermosetting or thermoplastic resin (e.g., prepreg, Ajinomoto Build-up Film (ABF), FR-4, or bismaleimide triazine (BT)) can be used as the insulating layer material.

[0073] Furthermore, conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), palladium (Pd), or alloys thereof can be used as the material for each of the circuit layer, the heat dissipation structure 500, and the via V, but are not limited thereto. In this case, the via V may correspond to a via penetrating at least a portion of the insulating layer of each of the first substrate 100, the second substrate 11, and the third substrate 200.

[0074] Furthermore, each of the circuit layer, heat dissipation structure 500, and via V of the semiconductor package 10E according to the embodiment can be formed by a plating process, and in this case, an electroless plating layer and an electrolytic plating layer may be included. The electroless plating layer can be used as a seed layer for the electrolytic plating layer, but the construction is not limited thereto.

[0075] In this case, the electroless and electrolytic plating layers of the filling circuit layer, heat dissipation structure 500 and via V may also include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), palladium (Pd) or alloys thereof.

[0076] In the semiconductor package 10E according to an embodiment, a circuit layer is formed on one surface of an insulating layer disposed on its outermost layer. At least a portion of the circuit layer may include a surface treatment layer, and the surface treatment layer may include a component different from the component of each circuit layer. For example, each circuit layer may include copper (Cu), and the surface treatment layer may include nickel (Ni) or tin (Sn), but this disclosure is not limited thereto.

[0077] Furthermore, in the semiconductor package 10E according to the embodiment, a solder resist layer may also be provided, which covers at least a portion of the circuit layer (including the surface treatment layer) formed on the outermost layer. In this case, the solder resist layer may be formed using a photosensitive material. Furthermore, the solder resist layer may have thermosetting and / or photocurable properties, but this disclosure is not limited thereto.

[0078] Furthermore, the first connecting member 410 connecting the first substrate 100 and the second substrate IS of the semiconductor package 10E according to the embodiment may correspond to a known solder bump, and may include, for example, copper (Cu), nickel (Ni), gold (Au), indium (In), bismuth (Bi) or other non-reactive metals.

[0079] The first electronic component D1 disposed on the first substrate 100 and the second electronic component D2 disposed on the third substrate 200 may be embedded in the molding material 300. In this case, the molding material 300 may include known materials, for example, epoxy molding compound (EMC), but this disclosure is not limited thereto.

[0080] In addition, refer to Figure 6B In the semiconductor package 10F according to an embodiment, a cavity C may be formed in a second substrate IS. In this case, the cavity C may be formed by known methods and may correspond, for example, to a structure obtained by performing processes such as laser drilling, CNC drilling, or sandblasting. Optionally, the cavity C may also be formed by plating and etching methods, but the formation methods are not limited thereto.

[0081] According to the embodiment, the first electronic component D1 of the semiconductor package 10F can be disposed in the cavity C of the second substrate IS, and the first electronic component D1 can represent a known component, as long as it is an electronic component of the type that can be mounted on a printed circuit board.

[0082] Furthermore, the semiconductor package 10F according to the embodiment may also include: a molding material 300 disposed inside the cavity C of the second substrate IS, and sealing or embedding the first electronic component D1; and a third substrate 200 connected to the second substrate IS. In this case, the second electronic component D2 may be disposed on one surface of the third substrate 200.

[0083] The descriptions of the other components are largely the same as those mentioned above, and their detailed descriptions will be omitted.

[0084] The insulating layer of the semiconductor package 10F according to an embodiment may include known components of stacked insulating layers. Specifically, thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimides), or materials prepared by impregnating inorganic fillers together with a core material (such as glass fiber (glass cloth, glass fabric)) in a thermosetting or thermoplastic resin (e.g., prepreg, Ajinomoto Build-up Film (ABF), FR-4, or bismaleimide triazine (BT)) can be used as the insulating layer material.

[0085] The descriptions of the other components are largely the same as those mentioned above, and their detailed descriptions will be omitted.

[0086] As described above, according to embodiments, semiconductor packages including microcircuits and / or microvias can be provided.

[0087] According to an embodiment, a semiconductor package that can effectively dissipate heat generated by a semiconductor chip can be provided.

[0088] While this disclosure includes specific examples, it will be readily understood by those skilled in the art that various changes in form and detail may be made to these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered merely for descriptive purposes and not for limiting purposes. The description of features or aspects in each example is to be considered applicable to similar features or aspects in other examples. Suitable results may be obtained if the described techniques are performed in a different order, and / or if components in the described system, architecture, apparatus, or circuit are combined in a different manner and / or if components in the described system, architecture, apparatus, or circuit are replaced or supplemented with other components or their equivalents. Therefore, the scope of this disclosure is not limited by the specific embodiments but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents shall be construed as included in this disclosure.

Claims

1. A semiconductor package, comprising: First substrate; A first electronic component is disposed on the first substrate; A second substrate is disposed on the first substrate and has a cavity, the cavity being disposed in one surface of the second substrate; A first connecting member connects the first substrate and the second substrate to each other; A heat dissipation structure is disposed on the second substrate and spaced apart from the first connecting member; A second connecting member is disposed on the second substrate; as well as A via is disposed on the second substrate, spaced apart from the heat dissipation structure, and connected to the first connecting member. The second substrate includes a first region in which the cavity is disposed and a second region connected to the first substrate. The heat dissipation structure is disposed in each of the first region and the second region of the second substrate. The via is disposed in the second region and penetrates the opening of the heat dissipation structure in the second region.

2. The semiconductor package according to claim 1, wherein, At least a portion of the first electronic component is disposed in the cavity of the second substrate.

3. The semiconductor package according to claim 1, wherein, In the heat dissipation structure, the heat dissipation structure disposed in the second region of the second substrate is disposed on the side wall of the cavity of the second substrate.

4. The semiconductor package according to claim 3, wherein, The heat dissipation structure disposed on the sidewall of the cavity of the second substrate has the largest cross-section in the region adjacent to the first substrate.

5. The semiconductor package of claim 1, further comprising a molding material disposed inside the cavity of the second substrate and sealing the first electronic component.

6. The semiconductor package according to claim 5, wherein, The heat dissipation structure disposed in the first region of the second substrate includes a metal portion that penetrates a portion of the molding material and is spaced apart from the first electronic component.

7. The semiconductor package according to claim 1, further comprising: The third substrate is connected to the second connecting member; And a second electronic component, disposed on one surface of the third substrate.

8. The semiconductor package according to claim 1, wherein, Each of the first connecting member and the second connecting member includes solder.

9. The semiconductor package according to claim 1, wherein, The heat dissipation structure is insulated from the via and the first connecting member.

10. The semiconductor package according to claim 1, wherein, The heat dissipation structure is insulated from the via and the first connecting member in the second region.

11. The semiconductor package according to claim 1, wherein, The second substrate has a step on the other surface opposite to the first surface, and The heat dissipation structure includes multiple metal layers in the area where the steps are set.

12. A semiconductor package, comprising: A first substrate, on one surface of which a first electronic component is disposed; The second substrate is disposed on the first substrate and has a cavity; as well as A heat dissipation structure is disposed on the second substrate. Wherein, a step is provided on one surface of the second substrate, and The heat dissipation structure includes multiple metal layers in the area where the steps are formed. The semiconductor package further includes: A first connecting member connects the first substrate and the second substrate to each other; and A via is disposed on the second substrate, spaced apart from the heat dissipation structure, and connected to the first connecting member. The second substrate includes a first region in which the cavity is disposed and a second region connected to the first substrate, and, The heat dissipation structure is disposed in each of the first region and the second region of the second substrate. The via is disposed in the second region and penetrates the opening of the heat dissipation structure in the second region.

13. The semiconductor package according to claim 12, wherein, The heat dissipation structure is insulated from the via and the first connecting member in the second region.

14. The semiconductor package of claim 13, wherein, The first connecting component includes solder.

15. The semiconductor package of claim 12, further comprising a molding material for sealing the first electronic component.

16. The semiconductor package of claim 12, further comprising a third substrate having a second electronic component disposed on a surface of the third substrate.

17. The semiconductor package of claim 16, further comprising a second connecting member connecting the second substrate and the third substrate. in, The second connecting member is spaced apart from the area in which the step is disposed.

18. The semiconductor package of claim 17, wherein, The second connecting component includes solder.

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