半导体器件及其制作方法

By forming an opening in the gate structure of the LDMOS transistor, the electric field concentration of the depletion electric field is alleviated, the breakdown voltage is increased, and the device performance is improved.

CN116207149BActive Publication Date: 2026-07-17WUHAN XINXIN SEMICON MFG CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
WUHAN XINXIN SEMICON MFG CO LTD
Filing Date
2021-11-30
Publication Date
2026-07-17

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Abstract

本申请提供一种半导体器件及其制作方法，该半导体器件包括：衬底，该衬底包括主体区和漂移区，该漂移区包括间隔区；位于该衬底上的栅介质层，该栅介质层从该主体区延伸至该漂移区，且与该间隔区边缘邻接；位于该栅介质层上且延伸至该间隔区上方的栅极结构，该栅极结构中形成有至少一个开口，该开口的位置与该间隔区的邻接边缘对应，且沿该栅极结构的厚度方向贯穿该栅极结构，从而能较好地缓解漂移区内邻接边缘处耗尽电场的负电荷集中现象，有效解决了耗尽电场中局部电压过大的问题，有利于提高击穿电压。
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