Thin-film transistors, display panels, and methods for fabricating thin-film transistors.

Abstract

This application discloses a thin-film transistor, a display panel, and a method for fabricating a thin-film transistor, relating to the field of display technology. The thin-film transistor includes a substrate, a gate, a gate insulating layer, an active layer, an ohmic contact layer, a source, and a drain. The gate is formed on the substrate, the gate insulating layer is formed on the gate, the active layer is formed on the gate insulating layer, the ohmic contact layer is formed on the active layer, and both the source and drain are formed on the ohmic contact layer. It also includes a first insulating layer formed between the ohmic contact layer and the active layer, wherein the thickness of the first insulating layer is 30-50 Å. Through the above design, this application increases the band barrier of the active layer, blocks holes, and reduces the TFT off-state current.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a thin-film transistor, a display panel, and a method for manufacturing a thin-film transistor. Background Technology

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) is a technology that combines microelectronics and liquid crystal display technology. In TFTs, the TFTs act as switches for pixels, controlling the rotation of the liquid crystal to display different colors. The deposition of each thin film layer is a crucial step in the TFT fabrication process, mainly including the gate electrode, gate insulating layer, active layer, ohmic contact layer, source / drain electrode, passivation layer, and pixel electrode.

[0003] The ohmic contact layer is conventionally prepared using amorphous silicon doped with other elements. The ohmic contact layer is placed between the active layer and the source / drain electrodes, which makes good ohmic contact between the active layer and the source / drain electrodes and reduces the contact resistance between the active layer and the source / drain electrodes. However, it also leads to a significant increase in leakage current in the TFT cutoff state. Summary of the Invention

[0004] The purpose of this application is to provide a thin-film transistor, a display panel, and a method for fabricating a thin-film transistor that increases the band barrier of the active layer, blocks holes, and reduces the off-state current of the TFT.

[0005] This application discloses a thin-film transistor, including a substrate, a gate, a gate insulating layer, an active layer, an ohmic contact layer, a source, and a drain. The gate is formed on the substrate, the gate insulating layer is formed on the gate, the active layer is formed on the gate insulating layer, the ohmic contact layer is formed on the active layer, and the source and drain are both formed on the ohmic contact layer. The transistor also includes a first insulating layer formed between the ohmic contact layer and the active layer, wherein the thickness of the first insulating layer is 30-50 Å.

[0006] Optionally, the ohmic contact layer is a highly doped N-type conductive layer.

[0007] Optionally, the ohmic contact layer includes a first doped layer, a second doped layer, and a first amorphous silicon layer located between the first doped layer and the second doped layer, wherein the first insulating layer is formed on the second doped layer; wherein the first amorphous silicon layer is an undoped amorphous silicon layer; and the doping concentration of the first doped layer is less than the doping concentration of the second doped layer.

[0008] Optionally, the ohmic contact layer further includes a third doped layer and a second amorphous silicon layer, wherein the second amorphous silicon layer is formed on the second doped layer and the third doped layer is formed on the second amorphous silicon layer; wherein the doping concentration of the first doped layer is less than the doping concentration of the second doped layer and the doping concentration of the second doped layer is less than the doping concentration of the third doped layer.

[0009] Optionally, the ohmic contact layer further includes a second amorphous silicon layer, a third doped layer, a fourth doped layer, a fifth doped layer, a fifth amorphous silicon layer, and a sixth doped layer. The second amorphous silicon layer, the third doped layer, the third amorphous silicon layer, the fourth doped layer, the fifth doped layer, the fifth amorphous silicon layer, and the sixth doped layer are stacked sequentially on the second doped layer. The second amorphous silicon layer is located between the second doped layer and the third doped layer. The third amorphous silicon layer is located between the third doped layer and the fourth doped layer. The fourth amorphous silicon layer is located between the fourth doped layer and the fifth doped layer. The fifth amorphous silicon layer is located between the fifth doped layer and the sixth doped layer.

[0010] Optionally, the doping concentration of the first doped layer is less than the doping concentration of the second doped layer, the doping concentration of the second doped layer is less than the doping concentration of the third doped layer, the doping concentration of the third doped layer is less than the doping concentration of the fourth doped layer, the doping concentration of the fourth doped layer is less than the doping concentration of the fifth doped layer, and the doping concentration of the fifth doped layer is less than the doping concentration of the sixth doped layer.

[0011] Optionally, the thicknesses of the first doped layer, the second doped layer, the third doped layer, the fourth doped layer, the fifth doped layer, and the sixth doped layer are all equal, ranging from 50 Å to 75 Å; the thicknesses of the first amorphous silicon layer, the second amorphous silicon layer, the third amorphous silicon layer, and the fourth amorphous silicon layer are all equal, ranging from 50 Å to 60 Å.

[0012] This application also discloses a display panel including thin-film transistors as described above.

[0013] This application also discloses a method for fabricating a thin-film transistor, including the following steps:

[0014] Provide a substrate;

[0015] A gate is formed on the substrate.

[0016] A gate insulating layer is formed on the gate;

[0017] An active layer is formed on the gate insulating layer;

[0018] A first insulating layer is formed on the active layer;

[0019] An ohmic contact layer is formed on the first insulating layer; and

[0020] A source and a drain are formed on the first insulating layer;

[0021] The thickness of the first insulating layer is 30-50 Å.

[0022] Optionally, the step of forming an ohmic contact layer on the active layer includes:

[0023] A first doped layer is formed on the first insulating layer;

[0024] A first amorphous silicon layer is formed on the first doped layer;

[0025] A second doped layer is formed on the first amorphous silicon layer.

[0026] Optionally, in the step of forming the first doped layer on the active layer, the gas flow rate of PH3 is 11000ML / S*25%, the gas flow rate of SiH4 is 6700ML / S, and the coating time is 4S; in the step of forming the second doped layer on the active layer, the gas flow rate of PH3 is 11000ML / S*50%, the gas flow rate of SiH4 is 6700ML / S, and the coating time is 4S.

[0027] Compared to the existing technology that uses an ohmic contact layer between the active layer and the source / drain, this application also provides a first insulating layer between the ohmic contact layer and the active layer, with a film thickness of 30-50 Å. This increases the height of the active layer's band barrier, causing the active layer's band to bend. When electrons are transported, electrons have a smaller mass than holes, while holes have a higher mass and slower electron mobility, making it more difficult for them to pass through the active layer's band barrier, thus preventing holes from passing through. At the same time, the characteristics of the first insulating layer allow electrons to be transported, thereby reducing the leakage current in the TFT's off state. Attached Figure Description

[0028] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0029] Figure 1 This is a block diagram of a display panel provided in an embodiment of this application;

[0030] Figure 2 This is a schematic diagram of the structure of the thin-film transistor provided in the embodiments of this application;

[0031] Figure 3 This is a schematic diagram of the energy band and charge of the first insulating layer combined with the highly doped ohmic contact layer provided in the embodiments of this application;

[0032] Figure 4 This is a schematic diagram of the structure of the ohmic contact layer provided in the embodiments of this application;

[0033] Figure 5 This is a schematic diagram of the six-layer ohmic contact layer provided in the embodiments of this application;

[0034] Figure 6 This is a schematic diagram comparing the TFT IV of the ohmic contact layer of this application with that of existing ohmic contact layers;

[0035] Figure 7 yes Figure 6 A diagram illustrating the numerical comparison;

[0036] Figure 8 A schematic flowchart of the method for fabricating a thin-film transistor provided in this application embodiment;

[0037] Figure 9 yes Figure 8 A further flowchart of step S5.

[0038] Among them, 10 is a display panel; 20 is a thin-film transistor; 100 is a substrate; 110 is a gate; 120 is a gate insulating layer; 130 is an active layer; 140 is an ohmic contact layer; 141 is a first doped layer; 142 is a first amorphous silicon layer; 143 is a second doped layer; 144 is a second amorphous silicon layer; 145 is a third doped layer; 146 is a third amorphous silicon layer; 147 is a fourth doped layer; 148 is a fourth amorphous silicon layer; 149 is a fifth doped layer; 150 is a fifth amorphous silicon layer; 151 is a sixth doped layer; 160 is a source; 170 is a drain; and 180 is a first insulating layer. Detailed Implementation

[0039] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0040] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0041] In addition, terms such as “center,” “horizontal,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer” that indicate orientation or positional relationship are based on the orientation or relative positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0042] Furthermore, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0043] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0044] Example:

[0045] Figure 1 This is a block diagram of a display panel provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a thin-film transistor according to an embodiment of this application. Figure 3 This is a schematic diagram of the energy bands and charges of the first insulating layer combined with a highly doped ohmic contact layer provided in the embodiments of this application, combined with... Figures 1-2As shown, this application discloses a display panel 10, including a thin-film transistor 20. The thin-film transistor 20 includes a substrate 100, a gate 110, a gate insulating layer 120, an active layer 130, a first insulating layer 180, an ohmic contact layer 140, a source 160, and a drain 170. The gate 110 is formed on the substrate 100, the gate insulating layer 120 is formed on the gate 110, the active layer 130 is formed on the gate insulating layer 120, the ohmic contact layer 140 is formed on the active layer 130, the source 160 and the drain 170 are both formed on the ohmic contact layer 140, and the first insulating layer 180 is formed between the ohmic contact layer 140 and the active layer 130. The thickness of the first insulating layer 180 is 30-50 Å.

[0046] Compared to the existing technology that uses an ohmic contact layer between the active layer and the source / drain, this application also provides a first insulating layer between the ohmic contact layer and the active layer, with a film thickness of 30-50 Å. This increases the height of the active layer's band barrier, causing the active layer's band to bend. When electrons are transported, electrons have a smaller mass than holes, while holes have a higher mass and slower electron mobility. Electrons need to overcome a higher barrier to jump over, making it more difficult for them to pass through the active layer's band barrier, thus preventing holes from passing through. At the same time, the characteristics of the first insulating layer allow electrons to be transported, thereby reducing the TFT off-state current.

[0047] The off-state current Ioff of a TFT is the current between the source and drain when the TFT is off, while the on-state current Ion is the current between the source and drain when the TFT is on. Ioff is a crucial factor affecting the pixel's voltage retention characteristics; an excessively large Ioff can lead to pixel voltage leakage and display defects. Conversely, as Ioff decreases, Ion also decreases. The ratio Ion / Ioff is the on / off ratio; a higher on / off ratio indicates better TFT performance, while a lower ratio indicates relatively poorer TFT performance.

[0048] The first insulating layer 180 is a silicon dioxide insulating layer, which has good properties and can save energy. Of course, other suitable insulating layers can also be used.

[0049] The ohmic contact layer 140 is a highly doped N-type conductive layer. For example... Figure 3 As shown, at this time, compared with the N-type conductive layer with low concentration doping, the high concentration doped conductive layer cooperates with the first insulating layer 180 to reduce the contact resistance between the high concentration conductive layer and the source / drain metal electrodes, the potential barrier of the active layer 130 increases, the holes are directly blocked, and the EVs carrying the active layer 130 can bend, so that the charge carriers that originally needed to jump can tunnel directly, thereby improving the electron mobility.

[0050] Figure 4 This is a schematic diagram of the ohmic contact layer provided in an embodiment of this application, as shown below. Figure 4 As shown, the ohmic contact layer 140 includes a first doped layer 141, a second doped layer 143, and a first amorphous silicon layer 142 located between the first doped layer 141 and the second doped layer 143. The first insulating layer 180 is formed on the second doped layer 143. The first amorphous silicon layer 142 is an undoped amorphous silicon layer. The doping concentration of the first doped layer 141 is lower than that of the second doped layer 143. This formation of ohmic contact layers 140 with different doping concentrations improves electron mobility and reduces leakage current in the TFT cutoff state. Both the first and second doped layers are N+α-Si:H doped layers, and the second doped layer has a high doping concentration, which reduces the TFT turn-on voltage and makes the TFT easier to turn on.

[0051] Therefore, in order to further improve electron mobility and reduce leakage current, the ohmic contact layer 140 employs multiple doped layers, formed in a gradient doping manner. Specifically, Figure 5 This is a schematic diagram of the six-layer ohmic contact layer provided in the embodiments of this application, as shown below. Figure 5 As shown, the ohmic contact layer 140 further includes a second amorphous silicon layer 144, a third doped layer 145, a third amorphous silicon layer 146, a fourth doped layer 147, a fourth amorphous silicon layer 148, a fifth doped layer 149, a fifth amorphous silicon layer 150, and a sixth doped layer 151. 51 are stacked sequentially on the second doped layer 143, the second amorphous silicon layer 144 is located between the second doped layer 143 and the third doped layer 145, the third amorphous silicon layer 146 is located between the third doped layer 145 and the fourth doped layer 147, the fourth amorphous silicon layer 148 is located between the fourth doped layer 147 and the fifth doped layer 149, and the fifth amorphous silicon layer 150 is located between the fifth doped layer 149 and the sixth doped layer 151.

[0052] The doping concentration of the first doped layer 141 is lower than that of the second doped layer 143, the doping concentration of the second doped layer 143 is lower than that of the third doped layer 145, the doping concentration of the third doped layer 145 is lower than that of the fourth doped layer 147, the doping concentration of the fourth doped layer 147 is lower than that of the fifth doped layer 149, and the doping concentration of the fifth doped layer 149 is lower than that of the sixth doped layer 151. The doping concentration of the first doped layer 141 is close to that of hydrogenated amorphous silicon, which improves the contact interface between the first doped layer 141 and the active layer 130, resulting in good interlayer contact. The doping concentrations from the second doped layer 143 to the fifth doped layer 149 transition gradually, avoiding a sharp increase in doping concentration. The final layer, the sixth doped layer 151, has the highest doping concentration, reducing the contact resistance between the sixth doped layer 151 and the source / drain metal electrodes, thereby forming a good ohmic contact and improving electron mobility. Between every two doped layers, an undoped amorphous silicon layer is added. Compared to the N+α-Si:H doped layer, the conductivity of the amorphous silicon layer is somewhat worse, which improves the insulation. Therefore, it can increase the resistance of electron transition and block holes. Compared to the metal Fermi level EF, it lowers the position of the 140 valence band EV of the ohmic contact layer.

[0053] The thicknesses of the first doped layer 141, the second doped layer 143, the third doped layer 145, the fourth doped layer 147, the fifth doped layer 149, and the sixth doped layer 151 are all equal, ranging from 50 Å to 75 Å. This ensures the uniformity of the film layers and maintains a consistent electron migration rate for each doped layer. The thicknesses of the first amorphous silicon layer 142, the second amorphous silicon layer 144, the third amorphous silicon layer 146, and the fourth amorphous silicon layer 148 are also equal. Since the undoped amorphous silicon layers in between need to conduct electricity, the thickness of each amorphous silicon layer can be relatively smaller than the thickness of the doped layers. The thicknesses of the doped layers 141, 143, 145, 147, 149, and 151 are all 75 Å, while the thicknesses of the amorphous silicon layers 142, 144, 146, and 148 are 50 Å. This combination effectively improves electron mobility, enhances electron transition, blocks holes, and reduces leakage current in the TFT cutoff state. Furthermore, using an even number of layers ensures symmetry between the upper and lower layers of the ohmic contact layer 140, resulting in better ohmic contact. Of course, the ohmic contact layer 140 can also be a combination of four doped layers and three amorphous silicon layers.

[0054] When the ohmic contact layer 140 employs three doped layers plus two amorphous silicon layers, specifically a third doped layer 145 and a second amorphous silicon layer 144, with the second amorphous silicon layer 144 formed on the second doped layer 143 and the third doped layer 145 formed on the second amorphous silicon layer 144, the doping concentration of the first doped layer 141 is less than that of the second doped layer 143, and the doping concentration of the second doped layer 143 is less than that of the third doped layer 145. This improves electron transition, blocks holes, reduces leakage current in the TFT cutoff state, and also reduces the manufacturing process.

[0055] Figure 6 This is a schematic diagram comparing the ohmic contact layer of this application with the TFTs of existing ohmic contact layers. Figure 7 yes Figure 6 The numerical comparison diagram shows that line A is the IV curve of the TFT with a conventional ohmic contact layer 140, and line B is the IV curve of the TFT with the novel ohmic contact layer 140 of this application. Figure 4-5 It can be seen from the experiment that when the ohmic contact layer 140 adopts a novel 6-layer doped structure, the back channel leakage current is 3.79E-14, while Ion is 2.39E-6. At this time, the on / off ratio of the ohmic contact layer 140 is: Ion / Ioff = 2.39E-6 / 3.79E-14 = 6.31E7. When the ohmic contact layer 140 has a normal structure, the back channel leakage current is 9.72E-14, while Ion is 2.46E-6. At this time, the on / off ratio of the ohmic contact layer 140 is: Ion / Ioff = 2.46E-6 / 9.72E-14 = 2.53E7. Therefore, the on / off ratio of the ohmic contact layer 140 with the novel structure is improved by [(6.31E7-2.53E7) / 2.53E7]*% = 149.41% compared with the normal structure. This reduces leakage current, lowers the risk of image retention and other problems, and improves the quality of the LCD panel.

[0056] Figure 8 This is a schematic diagram of the steps in the fabrication method of a thin-film transistor provided in the embodiments of this application, as shown below. Figure 8 As shown, this application also discloses a method for fabricating a thin-film transistor, including the following steps:

[0057] S1: Provide a substrate;

[0058] S2: A gate is formed on the substrate;

[0059] S3: A gate insulating layer is formed on the gate;

[0060] S4: An active layer is formed on the gate insulating layer;

[0061] S5: A first insulating layer is formed on the active layer;

[0062] S6: An ohmic contact layer is formed on the first insulating layer; and

[0063] S7: A source and a drain are formed on the ohmic contact layer;

[0064] The thickness of the first insulating layer is 30-50 Å. The thickness of a normal gate insulating layer is about 4000 Å, while the thickness of a passivation layer is about 2000 Å. Making the first insulating layer relatively thin increases the height of the active layer's band barrier, causing the active layer's band to bend. When electrons are transported, electrons have a smaller mass than holes, while holes have a higher mass and slower electron mobility. Electrons need to overcome a higher barrier to jump over, making it more difficult for them to pass through the active layer's band barrier, thus preventing holes from passing through. At the same time, the characteristics of the first insulating layer allow electrons to be transported, thereby reducing the TFT off-state current.

[0065] In addition, since the first insulating layer is relatively thin, there are certain requirements for the coating when preparing the first insulating layer. Chemical vapor deposition is adopted. In the chemical vapor deposition method, the deposition RF power is 100W to 200W, the deposition temperature is 220℃ to 250℃, the pressure in the reaction chamber is 50Pa to 90Pa, the gas flow ratio of N2O to SiH4 is 30 to 35, and the deposition rate is 0.5nm / s to 0.8nm / s. This can ensure the accuracy of the process while ensuring the required film thickness, and further ensure the contact characteristics between the first insulating layer, the active layer, and the ohmic contact layer.

[0066] Furthermore, Figure 9 yes Figure 8 A further flowchart of step S5 is shown below. Figure 9 As shown, step S5, which involves forming an ohmic contact layer on the active layer, includes:

[0067] S51: A first doped layer is formed on the first insulating layer;

[0068] S52: A first amorphous silicon layer is formed on the first doped layer;

[0069] S53: A second doped layer is formed on the first amorphous silicon layer.

[0070] In the doping layer fabrication process, the SiH4 gas flow rate is 6000-7000 mL / s, while the PH3 gas flow rate is based on 11000 mL / s. Specifically, the PH3 gas flow rate is 11000 mL / s * 25%, and the SiH4 gas flow rate is 6700 mL / s, with a coating time of 4 seconds to form the first doped layer. To form the second doped layer, the PH3 gas flow rate is adjusted to 11000 mL / s * 50%, while the coating time and SiH4 gas flow rate remain consistent with those used for the first doped layer.

[0071] When the ohmic contact layer uses six doped layers, the flow rate of PH3 gas in the fabrication process of the other doped layers follows the same pattern: the third doped layer uses a PH3 gas flow rate of 11000 mL / s*(1-25%), the fourth doped layer uses 11000 mL / s*(1+25%), the fifth doped layer uses 11000 mL / s*(1+50%), and the sixth doped layer uses 11000 mL / s*(1+25%+50%). An amorphous silicon layer is then added between each doped layer to form a gradient-doped ohmic contact layer. During the doping process, H2 is also required, and the H2 gas flow rate is adjusted appropriately based on the PH3 gas flow rate. Throughout the entire doping process, the overall gas flow rate of each doped layer remains at approximately 42000 mL / s.

[0072] It should be noted that the limitations on each step involved in this solution are not considered as limiting the order of steps, provided that they do not affect the implementation of the specific solution. The steps listed first can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the scope of protection of this application.

[0073] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0074] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A thin-film transistor, comprising: Substrate; A gate is formed on the substrate; A gate insulating layer is formed on the gate; An active layer is formed on the gate insulating layer; An ohmic contact layer is formed on the active layer; Source and drain, both of which are formed on the ohmic contact layer; The feature is that it further includes a first insulating layer, the first insulating layer being formed between the ohmic contact layer and the active layer, wherein... The thickness of the first insulating layer is 30 Å-50 Å; the first insulating layer is a silicon dioxide insulating layer; The ohmic contact layer is a highly doped N-type conductive layer; the ohmic contact layer includes a first doped layer, a second doped layer, and a first amorphous silicon layer located between the first doped layer and the second doped layer; the first doped layer is disposed on the first insulating layer; wherein, the first amorphous silicon layer is an undoped amorphous silicon layer, and the doping concentration of the first doped layer is less than the doping concentration of the second doped layer.

2. The thin-film transistor according to claim 1, characterized in that, The ohmic contact layer further includes a third doped layer and a second amorphous silicon layer, wherein the second amorphous silicon layer is formed on the second doped layer and the third doped layer is formed on the second amorphous silicon layer; Wherein, the doping concentration of the first doped layer is less than that of the second doped layer, and the doping concentration of the second doped layer is less than that of the third doped layer.

3. The thin-film transistor according to claim 1, characterized in that, The ohmic contact layer further includes a second amorphous silicon layer, a third doped layer, a fourth doped layer, a fifth doped layer, a fifth amorphous silicon layer, and a sixth doped layer. The second amorphous silicon layer, the third doped layer, the third amorphous silicon layer, the fourth doped layer, the fifth doped layer, the fifth amorphous silicon layer, and the sixth doped layer are stacked sequentially on the second doped layer. The second amorphous silicon layer is located between the second doped layer and the third doped layer. The third amorphous silicon layer is located between the third doped layer and the fourth doped layer. The fourth amorphous silicon layer is located between the fourth doped layer and the fifth doped layer. The fifth amorphous silicon layer is located between the fifth doped layer and the sixth doped layer.

4. The thin-film transistor according to claim 3, characterized in that, The doping concentration of the first doped layer is less than that of the second doped layer, the doping concentration of the second doped layer is less than that of the third doped layer, the doping concentration of the third doped layer is less than that of the fourth doped layer, the doping concentration of the fourth doped layer is less than that of the fifth doped layer, and the doping concentration of the fifth doped layer is less than that of the sixth doped layer.

5. The thin-film transistor according to claim 4, characterized in that, The on / off ratio of the ohmic contact layer is: Ion / Ioff = 2.39E-6 / 3.79E-14 = 6.31E7; the on / off ratio is increased by 149.41%.

6. The thin-film transistor according to claim 3, characterized in that, The thicknesses of the first doped layer, the second doped layer, the third doped layer, the fourth doped layer, the fifth doped layer, and the sixth doped layer are all equal, ranging from 50 Å to 75 Å; the thicknesses of the first amorphous silicon layer, the second amorphous silicon layer, the third amorphous silicon layer, and the fourth amorphous silicon layer are all equal, ranging from 50 Å to 60 Å.

7. The thin-film transistor according to claim 6, characterized in that, The thickness of the first doped layer, the second doped layer, the third doped layer, the fourth doped layer, the fifth doped layer, and the sixth doped layer is 75 Å, and the thickness of the first amorphous silicon layer, the second amorphous silicon layer, the third amorphous silicon layer, and the fourth amorphous silicon layer is 50 Å.

8. A display panel, characterized in that, Including the thin-film transistor as claimed in any one of claims 1-7.

9. A method for fabricating a thin-film transistor, characterized in that, Including the following steps: Provide a substrate; A gate is formed on the substrate. A gate insulating layer is formed on the gate; An active layer is formed on the gate insulating layer; A first insulating layer is formed on the active layer; An ohmic contact layer is formed on the first insulating layer; as well as The source and drain are formed on the ohmic contact layer; Wherein, the thickness of the first insulating layer is 30Å-50Å, and the first insulating layer is a silicon dioxide insulating layer; The ohmic contact layer is a highly doped N-type conductive layer; the ohmic contact layer includes a first doped layer, a second doped layer, and a first amorphous silicon layer located between the first doped layer and the second doped layer; wherein, the first amorphous silicon layer is an undoped amorphous silicon layer, and the doping concentration of the first doped layer is less than the doping concentration of the second doped layer; The step of forming an ohmic contact layer on the first insulating layer includes: A first doped layer is formed on the first insulating layer; A first amorphous silicon layer is formed on the first doped layer; A second doped layer is formed on the first amorphous silicon layer.

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