Switched power amplifier and method of suppressing harmonics thereof

Abstract

A switching power amplifier with harmonic rejection includes a multiphase converter and a power amplifier stage. The multiphase converter converts an input signal modulated in frequency or phase into a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal centered at the 50% duty cycle rail-to-rail signal when high, and a negative 25% duty cycle rail-to-rail signal centered at the 50% duty cycle rail-to-rail signal when low. The power amplifier stage includes first and second branches coupled between an upper node and a lower node, each including a series coupled P-channel transistor and a series coupled N-channel transistor forming an intermediate input node. The transistors of the first branch are controlled by the 50% duty cycle signal, and the transistors of the second branch are controlled by the positive and negative 25% duty cycle signals. The first and second branches produce output currents that are superimposed on each other to reject the third and fifth harmonics.

Description

Technical Field

[0001] This invention relates to a switching power amplifier, and more particularly to a switching power amplifier for output harmonic suppression that meets spectrum shielding requirements. Background Technology

[0002] Nonlinear switching power amplifiers (PAs) including Class D output stages and similar types operate with amplitude-limited signals and achieve good efficiency; however, they also generate high electromagnetic radiation at carrier frequency harmonics. Generally, such amplifiers require harmonic mitigation techniques to meet the stringent out-of-band emission requirements set by various regulatory agencies, such as the U.S. Federal Communications Commission. Common methods for reducing such emissions include high-order matching networks that reduce conducted harmonic power. However, such high-order matching networks result in increased component count and do not effectively handle electromagnetic radiation caused by harmonic currents in the lead wires connecting the chip to the package lead frame and in the radiating loops near the printed circuit board (PCB).

[0003] On-chip harmonic suppressors (such as, for example, series inductors and capacitors (LC) modulated to provide low-impedance AC shunts to ground voltage for specific harmonics) have been used to reduce the energy of radiated harmonics. However, such solutions typically require on-chip passive components, which consume considerable valuable circuit space. Furthermore, such implementations offer limited on-chip quality factor (Q) and component diversity for the limited passive components, setting a limit on the maximum suppressable harmonics. Controlling instantaneous metrics (such as the rise and fall times of the pre-driver output to produce a gradual change in the switching resistance between the power amplifier's on and off states) reduces harmonic content but simultaneously leads to a significant performance drop due to a substantial reduction in input power at the fundamental frequency. Summary of the Invention

[0004] A switching power amplifier with harmonic suppression according to one embodiment of this disclosure includes a multiphase converter and a power amplifier stage. The multiphase converter converts input signals whose frequency or phase is modulated as rail-to-rail signals, each of which shifts between a first rail and a second rail, including a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is high for 25% of the time and at the center of the 50% duty cycle rail-to-rail signal while high, and a negative 25% duty cycle rail-to-rail signal that is low for 25% of the time and at the center of the 50% duty cycle rail-to-rail signal while low. The power amplifier stage includes a first branch and a second branch coupled between an upper node and a lower node, each comprising a series-coupled P-channel transistor and an N-channel transistor coupled together at an intermediate output node. The transistor in the first branch has a control terminal for receiving the 50% duty cycle rail-to-rail signal. The P-channel transistor in the second branch has a control terminal for receiving the negative 25% duty cycle rail-to-rail signal. The second branch's N-channel transistor has a control terminal that receives a rail-to-rail signal during a positive 25% duty cycle.

[0005] In this manner, when applied to a broadband load, the first branch generates a first output current with approximately 50% duty cycle, and the second branch generates a second output current superimposed on the first output current with approximately 25% duty cycle. The converged overlapping current performs harmonic cancellation, including, for example, suppressing the third and fifth harmonics of the output to meet the spectral shielding requirements for power transmission.

[0006] The multiphase converter can be configured to transfer a negative 25% duty cycle rail-to-rail signal to activate the second P-channel transistor in the second branch for approximately 25% of each cycle, and can also be configured to transfer a positive 25% duty cycle rail-to-rail signal to activate the second N-channel transistor in the second branch for approximately 25% of each cycle.

[0007] A multiphase converter may include a multiphase filter, a limiting amplifier circuit, and a combinational circuit. The multiphase filter converts the sinusoidal input signal into a positive 45-degree phase-shifted sinusoidal signal, a non-shifted amplitude-adjusted sinusoidal signal, and a negative 45-degree phase-shifted sinusoidal signal. The limiting amplifier circuit converts the positive 45-degree phase-shifted sinusoidal signal, the non-shifted amplitude-adjusted sinusoidal signal, and the negative 45-degree phase-shifted sinusoidal signal into a positive 45-degree phase-shifted rail-to-rail signal, a non-shifted rail-to-rail signal, and a negative 45-degree phase-shifted rail-to-rail signal, respectively. The combinational circuit logically combines the positive 45-degree phase-shifted rail-to-rail signal and the negative 45-degree phase-shifted rail-to-rail signal into a positive 25% duty cycle rail-to-rail signal and a negative 25% duty cycle rail-to-rail signal, respectively. The combinational circuit may further include a delay-matching buffer for delaying the shiftless rail-to-rail signal to provide a signal delay that matches the 50% duty cycle rail-to-rail signal with the positive 25% duty cycle rail-to-rail signal and the negative 25% duty cycle rail-to-rail signal.

[0008] The multiphase filter may include a high-pass capacitor-resistor filter, a capacitive attenuation matching circuit, and a low-pass resistor-capacitor filter. In one embodiment, each of the high-pass capacitor-resistor filter, the capacitive attenuation matching circuit, and the low-pass resistor-capacitor filter may be tuned based on a predetermined transmission frequency. The limiting amplifier circuit may include an amplitude limiting buffer. The combinational circuit may be configured with Boolean logic gates or the like to provide a positive 25% duty cycle rail-to-rail signal and a negative 25% duty cycle rail-to-rail signal.

[0009] A multiphase converter may include a delay-locked loop (DLL) and combinational circuitry. The DLL may include a delay line with a series-coupled inverter for providing phase-shifted and unshifted rail-to-rail signals. A phase-locked loop circuit can provide a frequency- or phase-modulated input signal as the rail-to-rail signal supplied to the DLL. An amplitude-limiting buffer can convert a frequency- or phase-modulated sinusoidal input signal into the corresponding rail-to-rail signal supplied to the DLL.

[0010] The switching power amplifier may include non-overlapping generation circuitry that generates non-overlapping P-type drive rail-to-rail signals and non-overlapping N-type drive rail-to-rail signals for driving P-channel transistors and N-channel transistors when harmonic suppression is disabled.

[0011] A method for suppressing harmonics in a switching power amplifier according to one embodiment of the present disclosure includes a rail-to-rail signal whose switching frequency or phase is modulated. Each of the rail-to-rail signals is shifted between a first rail and a second rail, including a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is high for 25% of the time and is centered on the 50% duty cycle rail-to-rail signal while being high, and a negative 25% duty cycle rail-to-rail signal that is low for 25% of the time and is centered on the 50% duty cycle rail-to-rail signal while being low. The negative 25% duty cycle rail-to-rail signal is used to drive an upper P-channel transistor of a second branch coupled in parallel with a power amplifier circuit of a first branch, and the positive 25% duty cycle rail-to-rail signal is used to drive a lower N-channel transistor of a power amplifier circuit of the second branch.

[0012] The method may include shifting the phase of a sinusoidal input signal forward by 45 degrees to provide a positive 45-degree phase-shifted sinusoidal signal, shifting the phase of a sinusoidal input signal backward by 45 degrees to provide a negative 45-degree phase-shifted sinusoidal input signal, adjusting the amplitude of the sinusoidal input signal to provide a non-shifted amplitude-adjusted sinusoidal signal, and converting the positive 45-degree phase-shifted sinusoidal signal, the non-shifted amplitude-adjusted sinusoidal signal, and the negative 45-degree phase-shifted sinusoidal signal to respectively provide a positive 45-degree phase-shifted rail-to-rail signal. The rail-to-rail signal without shift and the rail-to-rail signal with a negative 45-degree phase shift are logically combined to provide a rail-to-rail signal with a positive 25% duty cycle and a rail-to-rail signal with a negative 25% duty cycle, and the rail-to-rail signal without shift is delayed to provide a rail-to-rail signal with a 50% duty cycle that has the same time delay as the rail-to-rail signal with a positive 25% duty cycle and a rail-to-rail signal with a negative 25% duty cycle.

[0013] The method may include a high-pass filtered sinusoidal input signal to provide a positive 45-degree phase-shifted sinusoidal signal, a low-pass filtered sinusoidal input signal to provide a negative 45-degree phase-shifted sinusoidal input signal, and a capacitively attenuated sinusoidal input signal to provide a shiftless amplitude-adjusted sinusoidal signal.

[0014] The method may include transmitting a positive 45-degree phase-shifted sinusoidal signal, a non-shifted amplitude-adjusted sinusoidal signal, and a negative 45-degree phase-shifted sinusoidal signal through first, second, and third amplitude-limiting buffers, respectively, to provide a positive 45-degree phase-shifted rail-to-rail signal, a non-shifted rail-to-rail signal, and a negative 45-degree phase-shifted rail-to-rail signal, respectively.

[0015] The method may include performing a logical "OR" operation on a positive 45-degree phase-shifted rail-to-rail signal and a negative 45-degree phase-shifted rail-to-rail signal to provide a negative 25% duty cycle rail-to-rail signal, and performing a logical "AND" operation on a positive 45-degree phase-shifted rail-to-rail signal and a negative 45-degree phase-shifted rail-to-rail signal to provide a positive 25% duty cycle rail-to-rail signal.

[0016] The method may include providing a rail-to-rail input signal to a multiphase delay line having selectable outputs configured to provide a positive 45-degree phase-shifted rail-to-rail signal, a no-shifted rail-to-rail signal, and a negative 45-degree phase-shifted rail-to-rail signal; logically combining the positive 45-degree phase-shifted rail-to-rail signal and the negative 45-degree phase-shifted rail-to-rail signal to provide a positive 25% duty cycle rail-to-rail signal and a negative 25% duty cycle rail-to-rail signal; and delaying the no-shifted rail-to-rail signal to provide a 50% duty cycle rail-to-rail signal with the same time delay as the positive 25% duty cycle rail-to-rail signal and the negative 25% duty cycle rail-to-rail signal.

[0017] The method may include generating a P-type drive rail-to-rail signal by performing a logical OR operation on a 50% duty cycle rail-to-rail signal and an N-type drive rail-to-rail signal, generating an N-type drive rail-to-rail signal by performing a logical AND operation on the 50% duty cycle rail-to-rail signal and the P-type drive rail-to-rail signal, wherein the P-type drive rail-to-rail signal and the N-type drive rail-to-rail signal are non-overlapping, and disabling harmonic suppression by driving P-channel transistors of a first branch and a second branch of a power amplifier circuit with the P-type drive rail-to-rail signal and driving the lower N-channel transistors of the first branch and the second branch of the power amplifier circuit with the N-type drive rail-to-rail signal. Attached Figure Description

[0018] The invention is illustrated by way of example and is not limited to the drawings, wherein like references represent similar elements. Elements shown in the drawings are for simplicity and clarity and are not drawn to scale.

[0019] Figure 1 A simplified block diagram of a power amplifier (PA) output stage implemented according to one embodiment of the present invention is shown.

[0020] Figure 2 For illustration Figure 1 A schematic diagram of a multiphase converter, including an implementation according to an embodiment of the present disclosure. Figure 1 Multiphase filters, limiting amplifier circuits, and combinational circuits.

[0021] Figure 3 To illustrate an embodiment implemented according to this disclosure Figure 1 A simplified block diagram of the non-overlapping generation circuit, the suppression selection circuit, and the pre-drive circuit.

[0022] Figure 4 The power amplifier output chip illustrated according to one embodiment of this disclosure can be used to implement... Figure 1 At least a portion of the output stage of the power amplifier.

[0023] Figure 5A timing diagram depicting the approximate signal values ​​of MP50DC, MN50DC, MN25DC, and MP25DC relative to time and the power amplifier output current relative to time is provided to illustrate the state of harmonic suppression enabled according to one embodiment of this disclosure.

[0024] Figure 6 The illustration shows an embodiment of the present disclosure for generating P-type drive rail-to-rail signals and N-type drive rail-to-rail signals. Figure 3 A schematic diagram of a non-overlapping generation circuit.

[0025] Figure 7 This is a timing diagram illustrating a 50% duty cycle signal and the corresponding non-overlapping P-type drive rail-to-rail signal and N-type drive rail-to-rail signal, as well as a delayed 50% duty cycle reference signal, according to an embodiment of this disclosure.

[0026] Figure 8 The simplified schematic and block diagram of a delay-locked loop (DLL) according to another embodiment of this disclosure can be used as an alternative to generating a combination of a 50% duty cycle signal and a 25% duty cycle signal. Figure 1 The multiphase filter and limiting amplifier circuit of the multiphase converter.

[0027] Figure 9 The diagram illustrates a method for directly receiving rail-to-rail input signals TXIN according to another embodiment of this disclosure. R-R Simplified block diagrams of alternative embodiments of LP45, L0, and LN45 signals are provided.

[0028] [Explanation of Labels in the Attached Images]

[0029] TXIN,TXINB,P+45,P-0,P-45,LP45,L0,LN45,

[0030] LP45+45,DL0,MP25DC,MP50DC,MN50DC,MN25DC,TXO,SLEN, LP45&45: Signal

[0031] 100: Power Amplifier Output Stage

[0032] 102: Buffer

[0033] 104: Polyphase Filter

[0034] 106: Limiting Amplifier Circuit

[0035] 108: Combinational Circuits

[0036] 110: Non-overlapping generation, suppression selection, and pre-drive circuitry

[0037] 112: Power Amplifier Output Stage

[0038] 116: Pound wire inductor

[0039] 118: Matching Network

[0040] 120: Antenna

[0041] 122: Multiphase converter

[0042] 203, 205, 207: Nodes

[0043] 210: First limiting amplifier

[0044] 212: Second limiting amplifier

[0045] 214: Third Limiting Amplifier

[0046] 216: 2-Boolean logic "OR" gate

[0047] 217: Delay Match Buffer

[0048] 218: 2-Boolean logic AND gate

[0049] 220: Timing Diagram

[0050] R L :load

[0051] L BW :inductance

[0052] LSER: Series Inductor

[0053] CSH1, CSH2: Branch capacitors

[0054] GND: Ground voltage

[0055] PD: P-type drive signal

[0056] ND: N-type drive signal

[0057] 304: Suppression Selection Circuit

[0058] 306: Pre-drive circuit

[0059] B1, B2, B3, B4: Buffers

[0060] HS: Input

[0061] M1, M2, M3, M4: 2-input multiplexers

[0062] PA, P1, P2: P-channel transistors

[0063] NA, N1, N2: N-channel transistors

[0064] 401: Upper Node

[0065] 402: Power Amplifier Output Chip

[0066] 403: Output node

[0067] 405: Lower Node

[0068] I1, I2: Current

[0069] Ipa: Output current

[0070] 604: 2-Output Boolean logic AND gate

[0071] 800: Delayed Lock-in Loop

[0072] 801: Limiting Amplifier

[0073] 802: Phase Detector

[0074] 806: Filter

[0075] VDD: Power supply

[0076] 808: Current Source

[0077] INV1-INVN: Reverse buffer

[0078] 902: Phase-locked loop Detailed Implementation

[0079] The switched power amplifier and its harmonic suppression method described herein use a multiphase signal to drive parallel branches in the power amplifier output stage to achieve harmonic cancellation. This multiphase signal is generated using a first-order resistor-capacitor (RC) circuit. Harmonic cancellation is achieved by superimposing the resulting output current, thereby meeting the power supply's spectral shielding requirements. The switched power amplifier therefore does not require any additional external components or on-chip inductors for filtering to achieve harmonic suppression in the frequency band and reduce out-of-band emissions. However, it should be noted that such harmonic suppressors and external filters can still be added, if necessary, to further reduce harmonic signal components.

[0080] Both the third and fifth harmonics are reduced using current cancellation principles. Unlike traditional harmonic suppression topologies, the switching power amplifier described herein uses a combination of 50% and 25% duty cycle signals to minimize the impact on efficiency. In this paper, the duty cycle represents the portion of the full cycle during which the driven device is in the on-state (low resistance) due to a given drive. Harmonic cancellation current flows out of the power amplifier and also reduces the radiated component of the spectral emission through the pawl connecting the power amplifier to the leadframe, which overall is no more effective than through complex off-chip matching. In applications requiring relaxed harmonic suppression, the systems and methods described herein can be used to reduce the complexity of off-chip or external matching networks or reconfigured to deliver higher maximum power to conventional Class D. The harmonic suppression implementation described herein can also significantly accelerate silicon verification time by reducing the number of iterations on the matching network side. Reducing reliance on matching networks to attenuate the third and fifth harmonics should also make design deployments more robust to different PCB layouts.

[0081] Figure 1 This is a simplified block diagram of a power amplifier (PA) output stage 100 implemented according to one embodiment of the present disclosure. A rise-converted input transmission signal TXIN is provided to the input of a buffer 102, which provides a buffered TX signal TXIN. B The input and output of the multiphase filter 104. The TXIN signal is therefore also TXIN. B The signals are collectively converted to the central carrier frequency (f) for transmission. TX A sinusoidal signal, such as at 900 MHz or other low-frequency sub-gigahertz (GHz) levels, or other high-frequency levels, such as, for example, 2.4 GHz, 5 GHz, 10 GHz, etc. TXIN signal and therefore TXIN B The signal is either a frequency-modulated signal or a phase-modulated signal. In the illustrated embodiment, the power amplifier output stage 100 is configured as a switched power amplifier based on a Class D operating principle that applies phase or frequency modulation. Typical standards using these modulation methods include Bluetooth, Bluetooth Low Energy, ZigBee, and others that utilize different modulation formats, such as Gaussian Frequency Shift Keying (GFSK), Quadrature Phase Shift Keying (QPSK), Offset Quadrature Phase Shift Keying (O-QPSK), and so on.

[0082] TXIN BThe inputs to a multiphase filter 104 are provided, which, as described herein, performs phase shifting and outputs three corresponding sinusoidal signals, including two phase-shifted signals P+45 and P-45 (each shifted 45 degrees in opposite directions or polarities) and a non-shifted amplitude adjustment signal P-0. The P+45, P-0, and P-45 sinusoidal signals are provided to the respective inputs to a limiting amplifier circuit 106, which converts the sinusoidal signals into corresponding rail-to-rail signals LP45, L0, and LN45, respectively. The LP45, L0, and LN45 rail-to-rail signals are provided to the respective inputs to a combinational circuit (COMBO) 108, which logically combines LP45 and LN45 into two synchronous rail-to-rail signals LP45+LP45 and LP45&LN45, with their delay L0 matched by an amount to provide a delayed signal DL0 that is matched to the channel delay of LP45+LN45 and LP45&LN45. As used herein, a "rail-to-rail" signal typically includes a signal that transfers between applicable supply voltages or rails, including a first rail such as a supply reference level, such as ground (GND), and a second rail such as a supply voltage level VDD relative to ground (GND).

[0083] The LP45+LP45, DL0, and LP45%LP45 rail-to-rail signals are provided to the inputs of the non-overlap generation, suppression selection, and pre-drive circuit 110, respectively. The non-overlap generation, suppression selection, and pre-drive circuit 110 receives the LP45+LP45, DL0, and LP45%LP45 signals and provides four signals, MP25DC, MP50DC, MN50DC, and MN25DC, to their corresponding inputs to the power amplifier output stage 112. The actual configuration of each of the MP25DC, MP50DC, MN50DC, and MN25DC signals is determined by a harmonic suppression enable (HS_EN) signal provided to the control or selection input of the non-overlap generation, suppression selection, and pre-drive circuit 110. When the harmonic suppression enable signal is enabled to enable harmonic suppression, the MP25DC, MP50DC, MN50DC, and MN25DC signals drive the power amplifier output stage 112 by substantially suppressing or reducing the third and fifth harmonic frequencies of the transmission frequency. When the harmonic suppression enable signal is set to an inactive state to disable harmonic suppression, the MP25DC, MP50DC, MN50DC, and MN25DC signals drive the power amplifier output stage 112 to operate with minimal impact on efficiency, as further described herein, without harmonic suppression. The harmonic suppression enable signal can be disabled, for example, for applications that intentionally operate in the relaxed suppression specification region. The power amplifier output stage 112 receives the MP25DC, MP50DC, MN50DC, and MN25DC signals and generates a transmission output (TXO) signal at the output.

[0084] The TXO signal is coupled in series between the power amplifier output stage 112 and the input of the external matching network 118 via an AC coupling capacitor 114 and a line inductor 116 (with inductance L). BW A matching network 118 is provided. Matching network 118 has an output coupled to antenna 120 for wireless transmission. In one embodiment, matching network 118 may be configured as a three-element PI matching circuit comprising a series inductor LSER and a pair of shunt capacitors CSH1 and CSH2. As shown, for example, the series inductor LSER has a first end coupled to inductor 116 and a second end coupled to antenna 120, shunt capacitor CSH1 is coupled between the first end of the series inductor LSER and a reference node, such as ground GND, and shunt capacitor CSH2 is coupled between the second end of the series inductor LSER and ground GND. Alternative matching networks may be used. The output current I of power amplifier output stage 112 is... pa Inflow load R L The load of capacitor 114 is shown in the diagram.

[0085] It should be noted that the polyphase filter 104, the limiting amplifier circuit 106, and the combination circuit 108 collectively form a polyphase converter 122, which can be used to convert the buffered input transmission signal TXIN. B The signals are: 50% duty cycle signal L0, positive 25% duty cycle signal LP45+LP45, and negative 25% duty cycle signal LP45&LP45.

[0086] Figure 2 A multiphase converter 122 is schematically illustrated, comprising a multiphase filter 104, a limiting amplifier circuit 106, and a combination circuit 108, each of which is implemented according to one embodiment of this disclosure. Signal TXIN B The signal is supplied to node 201, which is further coupled to one end of capacitor C1 in the first branch, one end of another capacitor C2 in the second branch, and one end of resistor R2 in the third branch. In the first branch, the other end of capacitor C1 is coupled to node 203, which is further coupled to one end of resistor R1, the other end of which is coupled to GND. The capacitance of capacitor C1 and the resistance of resistor R1 are selected to transmit the signal TXIN. B The phase is shifted forward by +45 degrees (°) to develop the P+45 signal at node 203. In the second branch, the other end of capacitor C2 is coupled to node 205, which is further coupled to one end of another capacitor C3, which has the other end coupled to GND. The capacitances of capacitors C2 and C3 are selected to attenuate the signal TXIN. BThe same amount as in the first and second branches, with a 0° shift (or no shift), is used to develop the P-0 signal at node 205. In the third branch, the other end of resistor R2 is coupled to node 207, which is further coupled to one end of another capacitor C4, the other end of which is coupled to GND. The resistance of resistor R2 and the capacitance of capacitor C4 are selected to transmit the TXIN signal. B The phase is shifted backward by 45 degrees to develop the P-45 signal on node 203.

[0087] Capacitor C1 and resistor R1 form a first high-pass filter (HPF-CR) path; capacitors C2 and C3 form a second capacitive attenuation path for matching the amplitudes across the first, second, and third branches; and resistor R1 and capacitor C4 form a third low-pass filter (LPF-RC) path. The RC cutoff frequencies of the high-pass and low-pass filters are calibrated to be at the transmission frequency f. TX This causes the path to have a phase shift of ±45° relative to capacitive attenuation at this frequency.

[0088] Limiting amplifier circuit 106 includes a first limiting amplifier 210, a second limiting amplifier 212, and a third limiting amplifier 214. A P+45 signal is provided to the input of limiting amplifier 210, which has an output providing signal LP45. A P-0 ​​signal is provided to the input of limiting amplifier 212, which has an output providing signal L0. A P-45 signal is provided to the input of limiting amplifier 214, which has an output providing signal LN45. Each of limiting amplifiers 210, 212, and 214 operates as an amplitude limiting buffer (essentially similar to a comparator with a rail-to-rail output) to convert the sinusoidal signals P+45, P-0, and P-45 to the corresponding rail-to-rail signals LP45, L0, and LN45, respectively. It is understood that although amplitude information is not ideally preserved, phase and frequency information can be preserved according to Class D operation. It should be noted that the P+45 rail-to-rail signal, the P-0 rail-to-rail signal, and the P-45 rail-to-rail signal are essentially 50% DC signals that remain within 50% of the duty cycle, even during periods when the phase and / or frequency of the transmitted signal is modulated.

[0089] The combinational circuit 108 includes a 2-input Boolean OR gate 216, a delay matching buffer 217, and a 2-input Boolean AND gate 218. Signals LP45 and LN45 are provided to the respective inputs of the OR gate 216, which provides an output of LP45+LN45, where the "+" in the signal names indicates a logical OR operation rather than a mathematical addition operation. Signals LP45 and LN45 are also provided to the respective inputs of the AND gate 218, which provides an output of LP45%LN45, where the "&" in the signal names indicates a logical AND operation rather than a mathematical multiplication operation. The L0 signal is provided to the input of buffer 217, which provides an output of a delayed signal DL0 that is maintained at 50% duty cycle. Buffer 217 has a substantial matching gate 216 and a delay gate 218 to maintain delay matching between signals LP45+LN45, signals LP45&LN45 and signal DL0.

[0090] As illustrated in timing diagram 220, as a result of the logic combination, signals LP45+LN45 and LP45&LN45 are both 25% duty cycle signals. Signal LP45+LN45 maintains a high level (VDD) on the second rail for approximately 75% of the time, while simultaneously moving down to the first rail (GND) for approximately 25% of the time. Conversely, signals LP45&LN45 maintain a low level on the first rail (GND) for approximately 75% of the time, while moving up to the second rail (VDD) for approximately 25% of the time. Furthermore, signals LP45+45 and LN45+45 are jointly delayed-matched and centered at signal DL0, as further illustrated in timing diagram 220. As further explained and illustrated in this document, when signal LP45+LN45 is low on the first rail (GND), it is set to signal DL0 when the first rail is low, and when LP45%LN45 is high on the second rail (VDD), it is set to signal DL0 when the second rail is also high.

[0091] Figure 3 This disclosure describes a non-overlapping generation, suppression selection, and pre-driving circuit 110 implemented according to one embodiment. The non-overlapping generation, suppression selection, and pre-driving circuit 110 includes a non-overlapping generation circuit 302, a suppression selection circuit 304, and a pre-driving circuit 306. Timing diagram 220 repeatedly illustrates signals LP45+LN45, DL0, and LP45&LN45, which are respectively provided as inputs. DL0 is represented as an input provided to the non-overlapping generation circuit 302, which has a first output providing a P-type drive signal PD and a second output providing an N-type drive signal ND. The operation of the non-overlapping generation circuit 110 for converting signal DL0 into PD and ND signals is further described below.

[0092] Selection circuit 304 includes four 2-input multiplexers (MUX) M1, M2, M3, and M4, and pre-drive circuit 306 includes buffer circuits, each represented as a corresponding buffer B1, B2, B3, and B4. Signal LP45+LP45 is provided to the "HS" input of multiplexer M1 (where "HS" represents harmonic suppression selection), multiplexer M1 receives signal PD at its other inputs and has outputs coupled to the inputs of buffer B1. DL0 is provided to the HS input of multiplexer M2, multiplexer M2 receives signal PD at its other inputs and has outputs coupled to the inputs of buffer B2. DL0 is also provided to the HS input of multiplexer M3, multiplexer M3 receives signal ND at its other inputs and has outputs coupled to the inputs of buffer B3. LP45 & LN45 are provided to the HS input of multiplexer M4, which receives signal ND at its other inputs and has outputs coupled to the input of buffer B4. The outputs of buffers B1, B2, B3, and B4 provide signals MP25DC, MP50DC, MN25DC, and MN50DC, respectively.

[0093] Each of multiplexers M1 to M4 has a selection input for receiving the HS_EN signal. When HS_EN is enabled to enable harmonic suppression, each of multiplexers M1 to M4 selects its HS input to provide its output signal. Otherwise, when the signal HS_EN is disabled to disable harmonic suppression, each of multiplexers M1 to M4 selects another or non-HS input as its output. In this mode, when HS is enabled to enable harmonic suppression, signals LP45+LN45 are used to generate signals MP25DC, DL0 is used to generate both signals MP50DC and MN50DC, and LP45&LN45 are used to generate signal MN25DC. When the signal HS_EN is disabled to disable harmonic suppression, signal PD is used to provide both signals MP25DC and MP50DC, and signal ND is used to provide both signals MN50DC and MN25DC.

[0094] Each of the buffers 306 is configured to drive a large capacitive load of the power amplifier output stage 112. Although not specifically stated, each of the buffers B1 to B4 may be configured as a series tapered buffer suitable for driving the capacitive load of the power amplifier output stage 112.

[0095] It should be noted that for embodiments where harmonic suppression is required and remains enabled, the non-shift generation and suppression selection portion of circuit 110 can be omitted. Instead, signal LP45+LN45 can be buffered as signal MP25DC through buffer B1, signal DL0 can be buffered as signal MP50DC and signal MN50DC through buffers B2 and B3 respectively, and signal LP45&LN45 can be buffered as MN25DC signal through buffer B4.

[0096] Figure 4 This is a schematic diagram of a power amplifier output chip 402 that can be used to implement at least a portion of a power amplifier output stage 112 according to an embodiment of this disclosure. The power amplifier output chip 402 is representative of the entire power amplifier output stage 112, in which multiple chips are coupled in parallel and selectively activated based on a desired power level. The power amplifier input chip 402 includes P-channel transistors PA, P1, and P2, and N-channel transistors NA, N1, and N2. The P-channel and N-channel transistors are represented as metal-oxide-semiconductor row transistors (e.g., PMOS, NMOS), and it should be understood that alternative types of transistors may be used. The power amplifier output chip 402 is enabled by a chip enable signal SLEN and an inverse enable signal. Enable, the aforementioned two are each other's two's complement. The power amplifier output chip 402 receives signals MP25DC, MP50DC, MN50DC and MN25DC and outputs signal TXO.

[0097] A P-channel transistor PA has a source terminal coupled to VDD and a receiver terminal. The P-channel transistor P1 has a source terminal coupled to node 401, a gate terminal for receiving signal MP50DC, and a drain terminal coupled to output node 403 for developing signal TXO. The N-channel transistor N1 has a drain terminal coupled to output node 403, a gate terminal for receiving signal MN50DC, and a source terminal coupled to lower node 405. The N-channel transistor NA has a drain terminal coupled to node 405, a gate terminal for receiving SLEN, and a source terminal coupled to GND. The P-channel transistor P2 has a source terminal coupled to output node 401, a gate terminal for receiving signal MP25DC, and a drain terminal coupled to output node 403. The N-channel transistor N2 has a drain terminal coupled to output node 403, a gate terminal for receiving signal MN25DC, and a source terminal coupled to node 405.

[0098] It should be noted that the "MP" signals MP50DC and MP25DC are rail-to-rail signals used to drive P-channel or P-type transistors P1 and P2, respectively, while the "MN" signals MN50DC and MN25DC are rail-to-rail signals used to drive N-channel or N-type transistors N1 and N2, respectively. The numerical values ​​in the signal names, 25 and 50, represent the percentage of time the corresponding transistor is turned on or activated in each cycle. Therefore, P1 is turned on by signal MP50DC for 50% of the time (or per cycle), N1 is turned on by signal MN50DC for approximately 50% of the time (or per cycle), P2 is turned on by signal M25DC for approximately 25% of the time, and N2 is turned on by MN25DC for approximately 5% of the time. It should be further noted that the MP25DC signal can be designated as a "negative" 25% duty cycle rail-to-rail signal, nominally on the second rail (like VDD) and with 25% of the time (or per cycle) shifted to the first rail (like GND). Conversely, the MN25DC signal can be designated as a "positive" 25% duty cycle rail-to-rail signal, nominally on the first rail (like GND) and with 25% of the time (or per cycle) shifted to the second rail (like VDD).

[0099] Figure 5 To illustrate the signals MP50DC, MN50DC, MN25DC, and MP25DC with the power amplifier output current i in a case where harmonic suppression is enabled according to one embodiment of this disclosure. PA In the power amplifier output stage 112 (and assuming a wideband load R), L The approximate value of the signal is plotted against the time. Harmonic suppression is enabled as described above by setting the signal HS_EN to active. Since the signal is represented in an ideal state with no phase or frequency changes, it is plotted as an approximation.

[0100] Signals MP50DC and MN50DC are shown together as essentially the same signal. However, refer back to... Figure 4It should be noted that because signal MP50DC is applied to transistor P1 and signal MN50DC is applied to transistor N1, these two transistors are driven in an interleaved manner using the same signal. Signal MN25DC rises to the second rail only about 25% of the time (approximately 25% of the time for turning on transistor N2), occurring after MP50DC / MN50DC rises and falling back to a low potential during each cycle. Furthermore, each high pulse of signal MN25DC is substantially centered within half a cycle of signal MP50DC / MN50DC, coinciding with the second rail or the voltage rail above VDD. Similarly, signal MP25DC falls to the first rail only about 25% of the time (approximately 25% of the time for turning on transistor P2), occurring after MP50DC / MN50DC falls and returning to a high potential during each cycle before MP50DC / MN50DC rises. Furthermore, each low pulse of MP25DC is substantially centered in half a cycle of signal MP50DC / MN50DC simultaneously with the first rail or the low supply voltage rail GND.

[0101] The startup of two parallel switching stages driven by the quadrature group of gate drive signals MP50DC and MN50DC (50% duty cycle) and MP25DC and MN25DC (25% duty cycle), wherein the 25% duty cycle signal is set symmetrical to the 50% duty cycle signal, resulting in overlapping currents I1 and I2 forming a total current I. PA I1 is the current generated by the first parallel branch consisting of transistors P1 and N1 driven by a 50% duty cycle signal, and I2 is the current generated by the second parallel branch consisting of transistors P2 and N2 driven by a 25% duty cycle signal.

[0102] For each half-cycle when the signal TXO output is connected to the power supply VDD or GND via a supposedly symmetrical pull-up and pull-down switch, the circuit in resistor R... on_50DC and R on_50DC ||R on_25DC It has a two-range operating characteristic, where "||" represents a parallel configuration, R ON_50DCThe resistors are for the output chip 402 of the power amplifier driven by signals MP50DC and MN50DC, and RON_25DC is the resistor for the output chip 402 of the power amplifier driven by signals MP25DC and MN25DC. By appropriately selecting the above resistor ratios, suppression of the output current in the third (H3) and fifth (H5) harmonics for a given resistive load termination can be achieved. In the case of reactive harmonic termination, the load presented in the harmonics is not necessarily real, as it is usually the fundamental frequency. To obtain the highest efficiency, the suppression amplitude is lower, but nominally the H3-H5 reference design is still met.

[0103] The output current I of the power amplifier output stage 112 PA It is formed by the superposition of currents I1 and I2 caused by the aforementioned 50DC and 25DC voltage excitations, and can be expressed as a Fourier expansion with the following procedure (1):

[0104]

[0105] Where ω TX =2πf TX , where f TX For the transmission frequency, the equation can be expressed as follows: For the current I2 = √2I1, the third and fifth harmonics are invalidated. For the load R... L (like Figure 1 As shown in the figure, looking from capacitor 114 toward the load, the maximum amplitude of current I1 can be obtained according to the following formula (2):

[0106]

[0107] Furthermore, the maximum amplitude of current I2 can be obtained according to the following formula (3):

[0108]

[0109] Figure 6 A non-overlapping generation circuit 302 is used according to one embodiment of this disclosure to generate signals PD and ND. The non-overlapping generation circuit 302 includes a 2-input Boolean logic "OR" gate 602 and a 2-output Boolean logic "AND" gate 604 coupled to each other. A signal DL0 is provided to one input of each of the "OR" gate 602 and the "AND" gate 604. The output of the "OR" gate 602 provides the signal PD, which is further fed back to the other input of the "AND" gate 604, and the output of the "AND" gate 604 provides the signal ND, which is further fed back to the other input of the "OR" gate 602.

[0110] As before Figure 3As with the related instructions, when no additional harmonic suppression is required, signals PD and ND are selected when the signal HS_EN is set to invalid to disable harmonic suppression. Non-overlapping signals PD and ND are used in the latter mode to suppress potentially high current spikes during gate signal transitions to pull-up or pull-down devices.

[0111] Figure 7 This disclosure describes a signal DL0 and its corresponding non-overlapping signals PD and ND, along with a reference signal delayed by 50% of the duty cycle, according to one embodiment. Typically, the rising and falling edges of signals PD and ND are delayed by -T. AND (Delay associated with gate 604) or T OR The delay associated with the OR gate 602 is skewed relative to each other to ensure that the signals driving the complementary (P-type and N-type) transistors of the power amplifier output chip 402 do not overlap. This non-overlapping signal avoids high current spikes that would otherwise occur if VDD were temporarily coupled to GND through simultaneously turned-on series-coupled transistors. With harmonic suppression enabled, the switch is configured in a high-impedance state at the crossover point of the 50DC signal, and thus the current spike is minimized. Furthermore, if the 50DC signal is reduced during the duty cycle to ensure non-overlap (e.g., reducing the efficiency of 48DC based on the amount of non-overlap, e.g., by 2DC), harmonic cancellation will not be as effective.

[0112] Figure 8 This is a simplified block diagram of a delay-locked loop (DLL) 800, which can be used as an alternative to generating a combination of a 50% duty cycle signal and a 25% duty cycle signal according to another embodiment of this disclosure, replacing the multiphase filter 104 and the limiting amplifier circuit 106 of the multiphase converter 122. The buffered input signal TXIN B Provided by limiting amplifier 801, limiting amplifier 801 converts the sinusoidal input signal into a rail-to-rail input signal TXIN. R-R Rail-to-rail input signal TXIN R-RAn input to the phase detector 802 and an input to the delay line 804 are provided to the delay-locked loop 800. The delay line 804 can be implemented using N inverting buffers coupled together in series, the N inverting buffers being individually denoted as INV1, INV2, ..., INVN. In one embodiment, N = 8, although any multiple of 8 of the number of inverting buffers may be included. The output of the output line 804 at the output of the last inverting buffer INVN is fed back to another input of the phase detector 802. The phase detector 802 has an output coupled to the input of the loop filter 806, which has an output coupled to the control input of the current source 808. The current source 808 is referenced to VDD (or other reference voltage) and has an output that is supplied above the power supply input to each of the inverting buffers INV1-INVN of the delay line 804. Unless otherwise stated, each of the inverting buffers INV1-INVN has a low power supply input that references GND.

[0113] The outputs of each of the inverting buffers INV1-INVN of delay line 804 form a polyphase delay line output, wherein the selected outputs can be used as signals LP45, L0, and LN45. In one embodiment, the limiting amplifier circuit 106 can be omitted because the outputs of the selected inverters are limited as rail-to-rail signals. In an alternative embodiment, the limiting amplifier circuit 106 may still be included for buffering. In an embodiment where N=8, three of the eight possible output phases having a phase angle of k x 45° can be used to generate the associated LN45, LN, and LP45 signals, where k corresponds to any three consecutive elements of the array {0,1,2,3,4,5,6,7}.

[0114] Figure 9 According to another embodiment of this disclosure, this is for directly receiving rail-to-rail input signal TXIN. R-R Simplified block diagrams of alternative embodiments of signals LP45, L0, and LN45 are provided. A phase-locked loop (PLL) circuit 902 generates and provides a phase- or frequency-modulated signal TXIN. R-R The inputs to DLL800 are provided. The selected outputs of DLL800 provide signals LP45, L0, and LN45 as previously described.

[0115] This invention is disclosed to enable those skilled in the art to create and use the invention provided for specific applications and corresponding needs. However, this invention is not intended to be limited to the specific embodiments described and represented herein, but rather to be carried out within the maximum scope equivalent to the principles and novel features disclosed herein. Many other versions and variations are possible and included. Those skilled in the art will understand that they can readily use the disclosed concepts and specific embodiments as the basis for other structures of designs or modifications to provide the same purpose as the invention without departing from its spirit and scope.

Claims

1. A switching power amplifier, characterized in that, include: A multiphase converter is configured to modulate an input signal, either in frequency or phase, into multiple rail-to-rail signals, each of which is shifted between a first rail and a second rail, including a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is high for 25% of the time and is centered on the 50% duty cycle rail-to-rail signal while being high, and a negative 25% duty cycle rail-to-rail signal that is low for 25% of the time and is centered on the 50% duty cycle rail-to-rail signal while being low; and A power amplifier stage, comprising: A first branch includes a first P-channel transistor and a first N-channel transistor, wherein the first P-channel transistor has multiple current terminals coupled between an upper node and an intermediate output node and a control terminal for receiving the 50% duty cycle rail-to-rail signal; the first N-channel transistor has multiple current terminals coupled between the intermediate output node and a lower node and a control terminal for receiving the 50% duty cycle rail-to-rail signal; and A second branch includes a second P-channel transistor and a second N-channel transistor, wherein the second P-channel transistor has a plurality of current terminals coupled between the upper node and the intermediate output node and a control terminal for receiving the negative 25% duty cycle rail-to-rail signal, and the second N-channel transistor has a plurality of current terminals coupled between the intermediate output node and the lower node and a control terminal for receiving the positive 25% duty cycle rail-to-rail signal.

2. The switching power amplifier as described in claim 1, characterized in that, The multiphase converter is configured to shift the negative 25% duty cycle rail-to-rail signal to activate the second P-channel transistor for approximately 25% of each cycle, and wherein the multiphase converter is configured to shift the positive 25% duty cycle to activate the second N-channel transistor for approximately 25% of each cycle.

3. The switching power amplifier as described in claim 1, characterized in that, This multiphase converter includes: A multiphase filter is configured to convert an input signal containing a sinusoidal input signal into a positive 45-degree phase-shifted sinusoidal signal, a non-shifted amplitude-adjusted sinusoidal signal, and a negative 45-degree phase-shifted sinusoidal signal. A limiting amplifier circuit is configured to convert the positive 45-degree phase-shifted sinusoidal signal, the unshifted amplitude-adjusted sinusoidal signal, and the negative 45-degree phase-shifted sinusoidal signal into a positive 45-degree phase-shifted rail-to-rail signal, an unshifted rail-to-rail signal, and a negative 45-degree phase-shifted rail-to-rail signal, respectively; and A combinational circuit is configured to logically combine the positive 45-degree phase-shifted rail-to-rail signal and the negative 45-degree phase-shifted rail-to-rail signal into the positive 25% duty cycle rail-to-rail signal and the negative 25% duty cycle rail-to-rail signal, and the combinational circuit includes a delay matching buffer configured to delay the no-shifted rail-to-rail signal to provide a delay that matches the 50% duty cycle rail-to-rail signal with the positive 25% duty cycle rail-to-rail signal and the negative 25% duty cycle rail-to-rail signal.

4. The switching power amplifier as described in claim 3, characterized in that, This multiphase filter includes: A high-pass capacitor-resistance filter has an input coupled to an input node for receiving the sinusoidal input signal and an output that provides the positive 45-degree phase-shifted sinusoidal signal. A capacitive attenuation matching circuit has an input coupled to the input node and an output that provides the shiftless amplitude adjustment sine signal; as well as A low-pass resistor-capacitor filter has an input coupled to the input node and an output that provides the negative 45-degree phase-shifted sine signal.

5. The switching power amplifier as described in claim 4, characterized in that, The high-pass capacitor-resistor filter, the capacitive attenuation matching circuit, and the low-pass resistor-capacitor filter are each tuned based on a preset transmission frequency.

6. The switching power amplifier as described in claim 3, characterized in that, This limiting amplifier circuit contains multiple amplitude limiting buffers.

7. The switching power amplifier as described in claim 3, characterized in that, This combinational circuit includes: A Boolean logic OR gate having multiple inputs that receive the positive 45-degree phase shift rail-to-rail signal and the negative 45-degree phase shift rail-to-rail signal, and an output that provides the negative 25% duty cycle rail-to-rail signal. as well as A Boolean logic AND gate has multiple inputs that receive the positive 45-degree phase shift rail-to-rail signal and the negative 45-degree phase shift rail-to-rail signal, and an output that provides the positive 25% duty cycle rail-to-rail signal.

8. The switching power amplifier as described in claim 1, characterized in that, This multiphase converter includes: A delayed locking loop is configured to convert the input signal, which includes a rail-to-rail input signal, into a positive 45-degree phase-shifted rail-to-rail signal, a non-shifted rail-to-rail signal, and a negative 45-degree phase-shifted rail-to-rail signal; and A combinational circuit is configured to logically combine the positive 45-degree phase-shifted rail-to-rail signal and the negative 45-degree phase-shifted rail-to-rail signal into the positive 25% duty cycle rail-to-rail signal and the negative 25% duty cycle rail-to-rail signal, and the combinational circuit includes a delay matching buffer configured to delay the no-shifted rail-to-rail signal to provide a delay matching the positive 25% duty cycle rail-to-rail signal and the negative 25% duty cycle rail-to-rail signal to the 50% duty cycle rail-to-rail signal.

9. The switching power amplifier as described in claim 8, characterized in that, This delayed locking loop includes: A phase detector having a first input for receiving a rail-to-rail input signal, a second input, and an output; A delay line comprising a plurality of series-coupled inverters, the plurality of series-coupled inverters including a first inverter having an input for receiving the rail-to-rail signal and a final inverter having an output having a second input coupled to the phase detector; A cyclic filter having an input coupled to the output of the phase detector and having an output; and A controlled current source has a control input coupled to the output of the cyclic filter and an output having a supply input coupled to each of the plurality of series-coupled inverters of the delay line; The selected outputs of the plurality of series-coupled inverters are used to generate the 50% duty cycle rail-to-rail signal, the positive 25% duty cycle rail-to-rail signal, and the negative 25% duty cycle rail-to-rail signal.

10. The switching power amplifier as described in claim 8, characterized in that, It also includes an amplitude limiting buffer that converts a sine input signal into a rail-to-rail input signal.

11. The switching power amplifier as described in claim 8, characterized in that, It also includes a phase-locked loop that provides the input signal whose frequency or phase is modulated.

12. The switching power amplifier as described in claim 1, characterized in that, The first branch is configured to generate a first output current having approximately 50% duty cycle, and the second branch is configured to generate a second output current having approximately 25% duty cycle and superimposed on the first output current.

13. The switching power amplifier as described in claim 1, characterized in that, It also includes: A non-overlapping generation circuit has an input for receiving the 50% duty cycle rail-to-rail signal, a first output for providing a P-type drive rail-to-rail signal, and a second output for providing an N-type drive rail-to-rail signal, wherein the P-type drive rail-to-rail signal and the N-type drive rail-to-rail signal have offset transfer to prevent them from overlapping each other. as well as A selection circuit is configured to transmit the 50% duty cycle rail-to-rail signal and the positive and negative 25% duty cycle rail-to-rail signals to the power amplifier stage when harmonic suppression is enabled, and to transmit the P-type drive rail-to-rail signal to a plurality of control terminals of the first P-channel transistor and the second P-channel transistor, and to transmit the N-type drive rail-to-rail signal to the plurality of control terminals of the first N-channel transistor and the second N-channel transistor when harmonic suppression is disabled.

14. A method for suppressing harmonics in a switching power amplifier, characterized in that, Include: An input signal whose conversion frequency or phase is modulated is a plurality of rail-to-rail signals, each of which shifts between a first rail and a second rail, including a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is high for 25% of the time and is located at the center of the 50% duty cycle rail-to-rail signal while being high, and a negative 25% duty cycle rail-to-rail signal that is low for 25% of the time and is located at the center of the 50% duty cycle rail-to-rail signal while being low; The rail-to-rail signal during the 50% duty cycle drives an upper P-channel transistor and a lower N-channel transistor in a first branch of a power amplifier circuit. The negative 25% duty cycle rail-to-rail signal drives an upper P-channel transistor of a second branch, wherein the second branch is coupled in parallel to the first branch of the power amplifier circuit; as well as The N-channel transistor in the second branch of the power amplifier circuit is driven by the rail-to-rail signal with a positive 25% duty cycle.

15. The method for suppressing harmonics in a switching power amplifier as described in claim 14, characterized in that, The input signal whose conversion frequency or phase is modulated includes: Shift the phase of a sinusoidal input signal forward by 45 degrees to provide a positive 45-degree phase-shifted sinusoidal signal; The phase of the sinusoidal input signal is shifted backward by 45 degrees to provide a negative 45-degree phase-shifted sinusoidal signal; Adjust the amplitude of the sinusoidal input signal to provide a shift-free amplitude-adjustable sinusoidal signal; The amplitudes of the positive 45-degree phase-shifted sine wave signal, the amplitude of the non-shifted amplitude-adjusted sine wave signal, and the amplitude of the negative 45-degree phase-shifted sine wave signal are converted to provide a positive 45-degree phase-shifted rail-to-rail signal, a non-shifted rail-to-rail signal, and a negative 45-degree phase-shifted rail-to-rail signal, respectively. The positive 45-degree phase shift rail-to-rail signal and the negative 45-degree phase shift rail-to-rail signal are logically combined to provide a positive 25% duty cycle rail-to-rail signal and a negative 25% duty cycle rail-to-rail signal. as well as The non-displacement rail-to-rail signal is delayed to provide a 50% duty cycle rail-to-rail signal with the same time delay as the positive 25% duty cycle rail-to-rail signal and the negative 25% duty cycle rail-to-rail signal.

16. The method for suppressing harmonics in a switching power amplifier as described in claim 15. Its characteristics are: The step of shifting the phase of the sinusoidal input signal forward by 45 degrees includes high-pass filtering of the sinusoidal input signal to provide the positive 45-degree phase-shifted sinusoidal signal; The aforementioned shifting the phase of the sinusoidal input signal backward by 45 degrees includes low-pass filtering the sinusoidal input signal to provide the negative 45-degree phase-shifted sinusoidal signal; and The adjustment of the amplitude of the sinusoidal input signal includes capacitively attenuating the sinusoidal input signal to provide the shiftless amplitude-adjustable sinusoidal signal.

17. The method for suppressing harmonics in a switching power amplifier as described in claim 15, characterized in that, The conversion of the amplitude of the positive 45-degree phase-shifted sine signal, the amplitude of the non-shifted amplitude-adjusted sine signal, and the amplitude of the negative 45-degree phase-shifted sine signal includes transmitting the positive 45-degree phase-shifted sine signal, the non-shifted amplitude-adjusted sine signal, and the negative 45-degree phase-shifted sine signal respectively through a first amplitude limiting buffer, a second amplitude limiting buffer, and a third amplitude limiting buffer.

18. The method for suppressing harmonics in a switching power amplifier as described in claim 15, characterized in that, The logical combination includes performing a logical "OR" operation on the positive 45-degree phase shift rail-to-rail signal and the negative 45-degree phase shift rail-to-rail signal to provide the negative 25% duty cycle rail-to-rail signal, and performing a logical "AND" operation on the positive 45-degree phase shift rail-to-rail signal and the negative 45-degree phase shift rail-to-rail signal to provide the positive 25% duty cycle rail-to-rail signal.

19. The method for suppressing harmonics in a switching power amplifier as described in claim 14, characterized in that, The input signal whose conversion frequency or phase is modulated includes: A rail-to-rail input signal is provided to a delay-locked loop, the delay-locked loop including a multi-phase delay line having a plurality of selectable outputs configured to provide a positive 45-degree phase-shifted rail-to-rail signal, a non-shifted rail-to-rail signal and a negative 45-degree phase-shifted rail-to-rail signal. The positive 45-degree phase shift rail-to-rail signal and the negative 45-degree phase shift rail-to-rail signal are logically combined to provide a positive 25% duty cycle rail-to-rail signal and a negative 25% duty cycle rail-to-rail signal. as well as The non-displacement rail-to-rail signal is delayed to provide a 50% duty cycle rail-to-rail signal with the same time delay as the positive 25% duty cycle rail-to-rail signal and the negative 25% duty cycle rail-to-rail signal.

20. The method for suppressing harmonics in a switching power amplifier as described in claim 14, characterized in that, It also includes: A P-type drive rail-to-rail signal is generated by performing a logical OR operation on the 50% duty cycle rail-to-rail signal and an N-type drive rail-to-rail signal. The N-type drive rail-to-rail signal is generated by performing a logical AND operation on the 50% work cycle rail-to-rail signal and the P-type drive rail-to-rail signal, wherein the P-type drive rail-to-rail signal and the N-type drive rail-to-rail signal do not overlap. as well as Harmonic suppression is disabled by driving the upper P-channel transistors of the first and second branches of the power amplifier circuit with the P-type drive rail-to-rail signal and driving the lower N-channel transistors of the first and second branches of the power amplifier circuit with the N-type drive rail-to-rail signal.

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