A semiconductor structure and a method of manufacturing the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof, and is applied to the technical field of semiconductors. Specifically, the manufacturing method can make the bottom of the sidewall dielectric layer formed on both sides of the second gate structure on the top surface of the device structure completely cover the adjacent active region ACT in the following way: extending the gate material layer formed on the top surface of the device isolation structure in the direction parallel to the semiconductor substrate to cover part of the surface of the adjacent semiconductor substrate, so that the bottom of the sidewall dielectric layer formed on both sides of the second gate structure on the top surface of the device structure completely covers the adjacent active region ACT, that is, the sidewall dielectric layer on both sides of the second gate structure is not accumulated in the recessed notch of the device isolation structure (at this time, the STI recessed notch is filled with the gate material layer), thereby causing more nitrogen-containing polymer generated at this position during the etching process of the shared metal plug CT, which will cause etch stop, and finally cause process problems such as metal plug open circuit (CT open), and finally achieve the purpose of ensuring the yield of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration to achieve faster computing speeds, larger data storage capacity, and more functions. This places increasingly higher demands on their physical structure and manufacturing processes. Consequently, the area ratio of contact holes in logic circuits is increasing, requiring the use of special layout techniques to reduce area. Currently, in existing chip designs, SRAM, as a logic device, often uses a shared metal plug (CT) to connect the active region and the gate polysilicon (GPI) in order to reduce device size.

[0003] For existing sharedCT layout designs, due to the high step height and STI (shallow trench isolation) divot problem at the boundary between the active region (ACT) and the shallow trench isolation structure (STI), the Si3N4 film formed in the ONO sidewall structure on both sides of the gate structure easily accumulates at the STI / ACT interface. Figure 1 As shown, during the etching process of the shared metal plug CT, the large amount of nitrogen-containing polymer generated here will cause etchstop and eventually lead to process problems such as metal plug open circuit (CTopen). Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor structure and a method for manufacturing the same, so as to avoid the accumulation of sidewall dielectric layers covering both sides of the second gate structure in the recessed gaps of the device isolation structure by extending the gate material layer formed on the top surface of the device isolation structure in a direction parallel to the semiconductor substrate and covering the surface of a portion of the semiconductor substrate adjacent to the device isolation structure. This avoids the problem of nitrogen-containing polymers generated in the recessed gaps of the device isolation structure during the etching process of the shared contact hole structure (CT), which would lead to etchstop and ultimately cause process problems such as open circuit of the metal plug (CTopen).

[0005] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a test structure for a semiconductor device, the test structure comprising:

[0006] A semiconductor substrate is provided, the semiconductor substrate including an active region and a device isolation structure for defining the active region and having its top surface higher than the top surface of the semiconductor substrate, and a first oxide layer is also formed on the entire surface of the semiconductor substrate.

[0007] Remove the first oxide layer covering the top surface of the device isolation structure and the surface of the semiconductor substrate corresponding to the active region, so as to form the gate oxide layer of the MOS transistor on the active region and form recessed notches at both ends of the device isolation structure.

[0008] A gate material layer is deposited on the semiconductor substrate to form a discrete first gate structure on the active region. At the same time, a second gate structure that at least fills the recessed gap is formed on the top surface of the device isolation structure and on the surface of the semiconductor substrate corresponding to the portion of the active region adjacent to the device isolation structure. The gate material layer spans the active region and the device isolation structure and overlaps with the active region to a certain extent.

[0009] Sidewall dielectric layers are formed at least on both sides of the second gate structure, such that the bottom of the sidewall dielectric layers completely covers the surface of the semiconductor substrate corresponding to the active region:

[0010] A shared metal plug is formed to connect the active region and the gate material layer in the second gate structure, and the shared metal plug covers the overlap between the gate material layer in the second gate structure and the active region.

[0011] Furthermore, the material of the gate material layer can preferably be polycrystalline silicon, and the material of the first oxide layer can preferably be silicon dioxide.

[0012] Furthermore, the width of the second gate structure covering the surface of the semiconductor substrate corresponding to the portion of the active region adjacent to the device isolation structure can be the same as the width of the sidewall dielectric layer parallel to the surface of the semiconductor substrate.

[0013] Furthermore, the width of the sidewall dielectric layer along the surface parallel to the semiconductor substrate can specifically range from 0.04 μm to 0.12 μm.

[0014] Furthermore, the sidewall dielectric layer can be a single-layer membrane structure or a multi-layer membrane structure, and the multi-layer membrane structure can specifically be an ONO structure of oxide layer-nitride layer-oxide layer.

[0015] Furthermore, after forming the sidewall medium layer, the step of forming the shared metal plug provided by the present invention may include the following steps:

[0016] An interlayer dielectric layer is formed such that the second gate structure is buried within the interlayer dielectric layer;

[0017] The interlayer dielectric layer is etched to form a contact hole in the interlayer dielectric layer for connecting the gate material layer in the second gate structure and the adjacent active region thereto.

[0018] The contact hole is filled with conductive material to form a shared metal plug for simultaneously connecting the active region and the gate material layer in the second gate structure.

[0019] Furthermore, the process for removing the first oxide layer covering the top surface of the device isolation structure and the surface of the semiconductor substrate corresponding to the active region can specifically be a wet cleaning process.

[0020] Furthermore, the gate oxide layer can also extend to cover the surface of the semiconductor substrate corresponding to the active region adjacent to the device isolation structure.

[0021] Furthermore, the device isolation structure is preferably a shallow trench isolation structure (STI).

[0022] Secondly, based on the same inventive concept as the above-mentioned semiconductor structure manufacturing method, the present invention also provides a semiconductor structure prepared using the manufacturing method provided by the present invention. The specific steps can be referred to the manufacturing method provided in the first aspect, and will not be repeated here.

[0023] Thirdly, based on the same inventive concept, the present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the manufacturing steps of the semiconductor structure manufacturing method as described above.

[0024] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0025] In the semiconductor structure manufacturing method provided by the present invention, the gate material layer formed on the top surface of the device isolation structure is extended in a direction parallel to the semiconductor substrate and covers the surface of the semiconductor substrate adjacent to the isolation of part of the device structure. This ensures that the bottom of the sidewall dielectric layer on both sides of the second gate structure subsequently formed on the top surface of the device structure completely covers the adjacent active region ACT. In other words, the sidewall dielectric layer covering both sides of the second gate structure will not accumulate in the recessed notch of the device isolation structure (where the STI recessed notch is filled with the gate material layer). This would prevent the accumulation of nitrogen-containing polymers during the etching process of the shared metal plug CT, which would lead to etchstop and ultimately cause process problems such as metal plug open circuit (CTopen). This method ultimately achieves the goal of ensuring the yield of the semiconductor structure. Attached Figure Description

[0026] Figure 1 This is a TEM diagram showing the accumulation of Si3N4 film layers at the STI / ACT interface in the ONO sidewall structure on both sides of the gate structure of a semiconductor structure formed using existing manufacturing methods.

[0027] Figure 2 This is a schematic flowchart of a semiconductor structure manufacturing method according to an embodiment of the present invention.

[0028] Figure 3 This is a schematic diagram of a semiconductor structure formed by the manufacturing method of the semiconductor structure according to an embodiment of the present invention.

[0029] Figure 4 This is a TEM diagram showing that, according to an embodiment of the present invention, the Si3N4 film layer in the ONO sidewall structure on both sides of the second gate structure formed by the semiconductor structure manufacturing method does not accumulate at the STI / ACT interface.

[0030] in, Figure 3 The attached figures are labeled as follows:

[0031] 100 - Semiconductor substrate; 110 - Gate oxide layer;

[0032] 120 - Sidewall dielectric layer; 251 - First gate structure;

[0033] 252 - Second gate structure; 101 - Device isolation trench;

[0034] 102 - Shallow trench isolation structure (STI) has recessed notches at both ends;

[0035] ShareCT - Shared Metal Plug. Detailed Implementation

[0036] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0037] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0038] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0039] As described in the background section, in current chip designs, SR AM, as a logic device, often uses a shared metal plug (CT) to connect the active region (ACT) and the gate polysilicon (SPI) to reduce device size (referred to as shared metal plug, shareCT). For existing shareCT layout designs, the process involves first forming the active region (ACT) and shallow trench isolation (STI) on the semiconductor substrate, then forming a first oxide layer of a certain thickness across the entire surface of the substrate. A wet cleaning process is then used to remove part of the first oxide layer. During this process, two STI divots (sink defects) inevitably form on both sides of the STI. That is, at the boundary between the active region (ACT) and the STI, there is a high step height. Therefore, the Si3N4 film in the ONO sidewall structure formed on both sides of the gate structure easily accumulates at the STI / ACT interface. Figure 1 As shown, during the etching process of the shared metal plug CT, the large amount of nitrogen-containing polymer generated here will cause etchstop and eventually lead to process problems such as metal plug open circuit (CTopen).

[0040] To address this problem, the inventors of this invention propose a novel method for manufacturing semiconductor structures. Specifically, by extending a gate material layer formed on the top surface of a device isolation structure along a direction parallel to the semiconductor substrate and covering a portion of the semiconductor substrate surface adjacent to the device isolation structure, the bottom of the sidewall dielectric layers subsequently formed on both sides of the second gate structure on the top surface of the device structure completely covers the adjacent active region ACT. This ensures that the sidewall dielectric layers covering both sides of the second gate structure will not accumulate in the recessed gaps of the device isolation structure (where the STI recessed gaps are filled with gate material layers). Consequently, during the etching process of the shared metal plug CT, a large amount of nitrogen-containing polymer generated at this point would cause an etch stop, ultimately leading to process problems such as CTopen. This method ultimately achieves the goal of ensuring semiconductor structure yield.

[0041] Therefore, the present invention aims to provide a semiconductor structure and a method for manufacturing the same, so as to avoid the accumulation of sidewall dielectric layers covering both sides of the second gate structure in the recessed gaps of the device isolation structure by extending the gate material layer formed on the top surface of the device isolation structure in a direction parallel to the semiconductor substrate and covering the surface of a portion of the semiconductor substrate adjacent to the device isolation structure. This avoids the problem of nitrogen-containing polymers generated in this area during the etching process of the shared metal plug CT, which would lead to etchstop and ultimately cause process problems such as metal plug open circuit (CTopen).

[0042] For details, please refer to... Figure 2 , Figure 2 This is a schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the present invention. Figure 2 As shown, the method for manufacturing the semiconductor structure provided by the present invention may include at least the following steps:

[0043] Step S201: A semiconductor substrate is provided, the semiconductor substrate including an active region and a device isolation structure for defining the active region and having its top surface higher than the top surface of the semiconductor substrate, and a first oxide layer is formed on the entire surface of the semiconductor substrate.

[0044] Step S202: Remove the first oxide layer covering the top surface of the device isolation structure and the surface of the semiconductor substrate corresponding to the active region, so as to form the gate oxide layer of the MOS transistor on the active region and form recessed notches at both ends of the device isolation structure.

[0045] Step S203: A gate material layer is deposited on the semiconductor substrate to form a discrete first gate structure on the active region. At the same time, a second gate structure that at least fills the recessed gap is formed on the top surface of the device isolation structure and on the surface of the semiconductor substrate corresponding to the portion of the active region adjacent to the device isolation structure. The gate material layer spans the active region and the device isolation structure and overlaps with the active region to a certain extent.

[0046] Step S204: At least two sides of the second gate structure are formed with sidewall dielectric layers so that the bottom of the sidewall dielectric layers completely covers the surface of the semiconductor substrate corresponding to the active region.

[0047] Step S205: A shared metal plug is formed, which is used to connect the active region and the gate material layer in the second gate structure, and the shared metal plug covers the overlap between the gate material layer in the second gate structure and the active region.

[0048] Specifically, in step S201, for example, you can refer to... Figure 3 As shown, a semiconductor substrate 100 can be provided first. The semiconductor substrate 100 can be any suitable substrate known in the art, such as at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors. It can also include multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). Alternatively, it can be a double-sided polished wafer (DSP), or a ceramic substrate such as alumina, a quartz substrate, or a glass substrate. As a preferred example, the semiconductor substrate 100 in this embodiment can specifically be a silicon wafer.

[0049] Afterwards, it can be described Figure 3The semiconductor substrate 100 shown is etched using at least one of dry etching, wet etching, or a hybrid process to form a device isolation trench 101 defining the active region ACT. Then, an insulating material layer, such as silicon dioxide, is filled into the trench 101. A device isolation structure with its top surface higher than the top surface of the semiconductor substrate 100 is formed on the semiconductor substrate 100. As a preferred example, the device isolation structure of the present invention can specifically be a shallow trench isolation structure (STI). Next, a first oxide layer (not shown) of a certain thickness can be formed on the entire surface of the semiconductor substrate 100 using any existing thin film deposition process to facilitate the formation of a gate oxide layer as a gate structure in subsequent steps. The material of the first oxide layer is preferably silicon dioxide.

[0050] Specifically, in step S202, continue to refer to... Figure 3 As shown, a wet cleaning process can be used to etch the first oxide layer to remove the first oxide layer covering the entire top surface of the shallow trench isolation structure STI and to remove the first oxide layer on the surface of the semiconductor substrate 100 corresponding to the active region ACT. This allows the gate oxide layer 110 of the MOS transistor to be formed on the active region ACT, while simultaneously forming recessed notches 102 at both ends of the shallow trench isolation structure STI. Obviously, in this embodiment, while wet cleaning in step S202 forms the two recessed notches 102, only a portion of the first oxide layer is retained on the subsequent region of the active region ACT used to form the first gate structure and on the surface of the semiconductor substrate 100 adjacent to the active region ACT of the shallow trench isolation structure STI. The first oxide layer (or the gate oxide layer 110 obtained after etching) is not present on the entire surface of the shallow trench isolation structure STI.

[0051] Specifically, in step S203, continue to refer to Figure 3As shown, a gate material layer (not shown) of a certain thickness can be deposited on the entire surface of the semiconductor substrate 100 on which the gate oxide layer 110 and the two recessed notches 102 are formed. The gate material layer spans the active region and the device isolation structure and overlaps with the active region. The deposition process can be chemical vapor deposition or physical vapor deposition. The material of the gate material layer can be polysilicon. Then, the gate material layer is etched using at least one of dry etching, wet etching, and a hybrid process of the two, so that the gate material layer is retained only on the surface corresponding to the active region ACT on which the gate oxide layer 110 is formed and on the surface of the shallow trench isolation structure STI. This allows a discrete first gate structure 251 to be formed on the active region ACT, while a second gate structure 252 is formed on the top surface of the shallow trench isolation structure STI and on the surface of the gate oxide layer 110 corresponding to the active region adjacent to the shallow trench isolation structure STI.

[0052] Obviously, in this step, a portion of the second gate structure 252 formed is located on the surface of the shallow trench isolation structure (STI), while the other portion is located on the surface of the semiconductor substrate 100. That is, the manufacturing method provided by the present invention extends the gate material layer formed on the top surface of the device isolation structure in a direction parallel to the semiconductor substrate to cover the surface of the semiconductor substrate adjacent to the device structure isolation. This ensures that the bottom of the sidewall dielectric layers formed on both sides of the second gate structure on the top surface of the device structure completely covers the adjacent active region ACT. In other words, the sidewall dielectric layers covering both sides of the second gate structure will not accumulate in the recessed gaps of the device isolation structure (where the STI recessed gaps are filled with gate material layers). This would prevent the accumulation of nitrogen-containing polymers during the etching process of the shared metal plug CT, which would lead to etchstop and ultimately cause problems such as CTopen. This ultimately achieves the goal of ensuring the yield of the semiconductor structure.

[0053] In other words, in the manufacturing method provided by the present invention, a gate material layer made of polycrystalline silicon is used to fill the two STIdivots (recesses) on both sides of the shallow trench isolation structure (STI) caused by the wet cleaning process, instead of using a sidewall dielectric layer to fill them as in the prior art. This is the biggest difference between the present invention and the prior art.

[0054] Specifically, in step S204, continue to refer to... Figure 3As shown, using deposition and etching processes, sidewall dielectric layers 120 can be formed sequentially or simultaneously on both sides of the first gate structure 251 and both sides of the second gate structure 252. The bottom of the sidewall dielectric layers 120 formed on both sides of the second gate structure 252 completely covers the surface of the semiconductor substrate 100 corresponding to the active region ACT, that is, the surface of the gate oxide layer 110 corresponding to the active region adjacent to the shallow trench isolation structure STI.

[0055] Furthermore, as a preferred example, the width of the second gate structure 252 covering the surface of the semiconductor substrate 100 corresponding to the active region ACT adjacent to the shallow trench isolation structure (STI) is the same as the width of the sidewall dielectric layer 120 parallel to the surface of the semiconductor substrate 100. Specifically, the width of the sidewall dielectric layer 120 parallel to the surface of the semiconductor substrate 100 can range from 0.04 μm to 0.12 μm, that is, it can be 0.04 μm, 0.045 μm, 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.10 μm, 0.101 μm, 0.11 μm, 0.111 μm, 0.12 μm, and integers or decimals between any two of the above numbers.

[0056] Furthermore, as a preferred example, the sidewall dielectric layer is a single-layer membrane structure or a multi-layer membrane structure, wherein the multi-layer membrane structure is an ONO structure consisting of an oxide layer-nitride layer-oxide layer.

[0057] Specifically, in step S205, the present invention provides the following steps S205 to S207 to form a shared metal plug. The shared metal plug is used to connect the active region and the gate material layer in the second gate structure, and the shared metal plug covers the overlap between the gate material layer in the second gate structure and the active region, so as to achieve the purpose of not easily causing etch stop.

[0058] Step S205: Form an interlayer dielectric layer such that the interlayer dielectric layer buries the second gate structure within it.

[0059] Step S206: Etch the interlayer dielectric layer to form a contact hole in the interlayer dielectric layer for connecting the gate material layer in the second gate structure and its adjacent active region.

[0060] Step S207: Fill the contact hole with conductive material to form a shared metal plug (shareCT) for simultaneously connecting the active region and the gate material layer in the second gate structure 252.

[0061] In this embodiment, the shared metal plug (shareCT) can be formed using chemical vapor deposition and etching processes, and the method provided by this invention... Figure 4 As shown ( Figure 4 The TEM diagram showing that the Si3N4 film layer in the ONO sidewall structure 120 on both sides of the second gate structure 252 formed by the semiconductor structure manufacturing method provided by the present invention will not accumulate at the STI / ACT junction shows that the manufacturing method proposed by the present invention can achieve the purpose of the present invention.

[0062] Furthermore, based on the same inventive concept as the manufacturing method of the semiconductor structure described above, the present invention also provides a semiconductor structure prepared using the manufacturing method provided by the present invention. The specific steps can be referred to the manufacturing method provided in the first aspect, and will not be repeated here.

[0063] It is understood that, in the embodiments of the present invention, during the process of forming the semiconductor structure using the manufacturing method provided by the present invention, the layout used by the present invention can be improved first, and then used to form a design layout in which the active region ACT and the second gate structure 252 on the shallow trench isolation structure STI overlap. The shared metal plug shareCT covers the overlap, that is, the gate material layers in the active region ACT and the second gate structure 252 on the shallow trench isolation structure STI are connected together. The width of the overlap is consistent with the width of the sidewall dielectric layer 120 (Gatespacer) of the selected process platform.

[0064] In summary, the semiconductor structure manufacturing method provided by this invention specifically extends the gate material layer formed on the top surface of the device isolation structure in a direction parallel to the semiconductor substrate, covering a portion of the semiconductor substrate surface adjacent to the device structure isolation. This ensures that the bottom of the sidewall dielectric layers formed on both sides of the second gate structure on the top surface of the device structure completely covers the adjacent active region ACT. In other words, the sidewall dielectric layers covering both sides of the second gate structure will not accumulate in the recessed gaps of the device isolation structure (where the STI recessed gaps are filled with gate material layers). This would prevent the accumulation of nitrogen-containing polymers during the etching process of the shared metal plug CT, which would lead to etchstop and ultimately cause process problems such as CTopen. This method ultimately achieves the goal of ensuring the yield of the semiconductor structure.

[0065] It should be noted that, in another embodiment of the present invention, a computer-readable storage medium is also provided, which stores instructions that, when executed on a computer, cause the computer to perform the manufacturing method of any of the semiconductor structures described in the above embodiments.

[0066] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium, or a semiconductor medium (e.g., solid-state drive), etc.

[0067] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0068] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, and computer-readable storage media are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0069] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, It should include at least the following steps: A semiconductor substrate is provided, the semiconductor substrate including an active region and a device isolation structure for defining the active region and having its top surface higher than the top surface of the semiconductor substrate, and a first oxide layer is also formed on the entire surface of the semiconductor substrate. Remove the first oxide layer covering the top surface of the device isolation structure and the surface of the semiconductor substrate corresponding to the active region, so as to form the gate oxide layer of the MOS transistor on the active region and form recessed notches at both ends of the device isolation structure. A gate material layer is deposited on the semiconductor substrate to form a discrete first gate structure on the active region. At the same time, a second gate structure that at least fills the recessed gap is formed on the top surface of the device isolation structure and on the surface of the semiconductor substrate corresponding to the portion of the active region adjacent to the device isolation structure. The gate material layer spans the active region and the device isolation structure and overlaps with the active region to a certain extent. Sidewall dielectric layers are formed at least on both sides of the second gate structure, such that the bottom of the sidewall dielectric layers completely covers the surface of the semiconductor substrate corresponding to the active region: A shared metal plug is formed to connect the active region and the gate material layer in the second gate structure, and the shared metal plug covers the overlap between the gate material layer in the second gate structure and the active region.

2. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The gate material layer is made of polycrystalline silicon, and the first oxide layer is made of silicon dioxide.

3. The method for manufacturing a semiconductor structure as described in claim 2, characterized in that, The width of the second gate structure covering the surface of the semiconductor substrate corresponding to the active region adjacent to the device isolation structure is the same as the width of the sidewall dielectric layer parallel to the surface of the semiconductor substrate.

4. The method for manufacturing a semiconductor structure as described in claim 3, characterized in that, The width of the sidewall dielectric layer along the surface parallel to the semiconductor substrate ranges from 0.04 μm to 0.12 μm.

5. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The sidewall dielectric layer is a single-layer membrane structure or a multi-layer membrane structure, and the multi-layer membrane structure is an ONO structure consisting of an oxide layer, a nitride layer, and an oxide layer.

6. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The step of forming the shared metal plug includes: An interlayer dielectric layer is formed such that the second gate structure is buried within the interlayer dielectric layer; The interlayer dielectric layer is etched to form a contact hole in the interlayer dielectric layer for connecting the gate material layer in the second gate structure and the adjacent active region thereto. The contact hole is filled with conductive material to form a shared metal plug for simultaneously connecting the active region and the gate material layer in the second gate structure.

7. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The process of removing the first oxide layer covering the top surface of the device isolation structure and the surface of the semiconductor substrate corresponding to the active region is a wet cleaning process.

8. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The gate oxide layer also extends to cover the surface of the semiconductor substrate corresponding to the active region adjacent to the device isolation structure.

9. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The device isolation structure is a shallow trench isolation structure.

10. A semiconductor structure, characterized in that, It is prepared by the manufacturing method of the semiconductor structure as described in any one of claims 1-9.

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