Flash memory layout, flash memory and method of manufacturing the same

Abstract

The application provides a flash memory layout, a flash memory and a manufacturing method thereof. The layout comprises: an active region layout layer comprising a plurality of active regions arranged in parallel along a first direction, the active regions comprising effective active regions and virtual active regions; a first floating gate layout layer comprising a plurality of first floating gate patterns arranged in parallel along a second direction; a second floating gate layout layer comprising a plurality of second floating gate patterns arranged in parallel along the second direction, the second floating gate patterns being arranged oppositely on both sides of a connection region, in each connection region, the second floating gate patterns are arranged alternately on the first floating gate patterns, and adjacent first floating gate patterns are provided with the second floating gate patterns in different connection regions; and a control gate contact hole layout layer comprising a control gate contact hole pattern arranged in the connection region and extending along the second direction. Compared with the prior art, the layout layer is used to finally form the floating gate and the control gate, the area of the connection region is reduced, the effective area utilization rate of the storage unit is improved, and the process window is increased.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a flash memory layout, a flash memory, and a method for manufacturing the same. Background Technology

[0002] Flash memory, due to its advantages of high density, low cost, and electrically programmable and erasable capabilities, has been widely adopted as the optimal choice for non-volatile memory applications. Generally, floating-gate flash memory has similar basic memory cells; they all have stacked gate structures, including floating gates and at least a control gate covering the floating gates. The control gates are coupled to control the storage and release of electrons within the floating gates.

[0003] Erasing in Nord flash occurs via Fulnohaing tunneling between the floating gate and the word line. By applying high and low voltages to the word line and the control gate, a high potential difference and electric field strength are created between the floating gate and the word line. Electrons stored in the floating gate tunnel through the oxide layer, causing the potential on the floating gate to change from negative to positive, thereby changing the storage state.

[0004] Nord flash currently exposes the control gate by setting up a strip area every 256 active regions. The control gate is exposed by patterning a mask made from the control gate contact hole pattern and a mask made from the second floating gate pattern, and isolated from the control gates of other rows. The control gate is then exposed through the contact hole.

[0005] The specific process flow includes: after forming the control gate polysilicon layer, the control gate polysilicon layer in the area covered by the second floating gate pattern is removed by patterning (i.e., exposure and development) using a mask fabricated from the second floating gate pattern; then, the control gate polysilicon layer in the area covered by the control gate contact hole pattern is protected by patterning the control gate contact hole pattern; the control gate polysilicon layers in all other areas except those covered by the first floating gate pattern and the control gate contact hole pattern are removed, ultimately forming the control gate. However, this structure occupies a relatively large area and has a small process window. Summary of the Invention

[0006] The purpose of this invention is to provide a flash memory layout, a flash memory, and a method for manufacturing the same, thereby improving the effective area utilization of the memory cell and increasing the process window.

[0007] To address the aforementioned technical problems, according to a first aspect of the present invention, a flash memory layout is provided, including a plurality of active regions and a connection region located between adjacent active regions, the flash memory layout comprising:

[0008] An active area layer, the active area layer comprising a plurality of active areas arranged in parallel along a first direction, the active areas comprising an active active area located within the active area and a virtual active area located within the connecting area;

[0009] The first floating grid layer includes a plurality of first floating grid graphics arranged in parallel along the second direction;

[0010] The second floating grid layer includes multiple second floating grid patterns arranged parallel to each other along a second direction. The second floating grid patterns are arranged opposite each other on both sides of the connecting area. Within each connecting area, the second floating grid patterns are arranged in alternating rows on top of the first floating grid patterns. Adjacent first floating grid patterns have second floating grid patterns arranged in different connecting areas.

[0011] A control gate contact hole plate layer, the control gate contact hole plate layer including control gate contact hole patterns located within the connection area and extending along the second direction.

[0012] Optionally, the plurality of active regions are arranged in a straight strip shape parallel to each other along the first direction and extend along the second direction; the plurality of first floating gate patterns are arranged in a straight strip shape parallel to each other along the second direction and extend along the first direction; the first direction and the second direction are perpendicular to each other.

[0013] Optionally, the second floating gate pattern is a straight strip in the second direction, and the extension lines of the second floating gate patterns on the same side within the same connection area overlap in the second direction.

[0014] Optionally, the control gate contact hole pattern is elongated and extends along the second direction, and the control gate contact hole pattern partially overlaps with the second floating gate patterns on opposite sides of the connection area.

[0015] Optionally, the flash memory layout further includes an edge region, and a connection region is provided between the edge region and the active region. The second floating gate pattern on the side of the connection region closest to the edge region is a straight strip and extends along the second direction.

[0016] Optionally, two virtual active zones are provided within the connection area.

[0017] Optionally, the number of effective active regions within each effective region is 128.

[0018] To address the aforementioned technical problems, according to a second aspect of the present invention, a method for manufacturing a flash memory is also provided, which is fabricated using the flash memory layout described above, the method comprising:

[0019] providing a substrate, wherein the substrate includes a plurality of active regions and connection regions located between adjacent active regions;

[0020] forming a floating gate polysilicon layer and a control gate polysilicon layer on the substrate;

[0021] patterning the control gate polysilicon layer using a first mask, wherein the first mask has a second floating gate mask layer;

[0022] patterning the control gate polysilicon layer and the floating gate polysilicon layer using a second mask, wherein the second mask has a first floating gate mask layer; and

[0023] patterning the control gate polysilicon layer and the floating gate polysilicon layer using a third mask to form a control gate and a floating gate, wherein the third mask has a control gate contact hole mask layer;

[0024] wherein a set of two isolated control gates is disposed on each of the floating gates, each adjacent set of control gates is separated in different connection regions, a first control gate in each set of control gates has a connection block extending toward a second control gate of the next set, the second control gate has a connection block extending toward a first control gate of the previous set, and a contact hole is to be formed on the connection block.

[0025] Optionally, each set of control gates is separated at every other connection region.

[0026] Optionally, the length of the control gate includes 256 effective active regions and 2 dummy active regions.

[0027] Optionally, the substrate further includes an edge region, a connection region is disposed between the edge region and the active region, and each of the control gates is separated in the connection region on the side close to the edge region.

[0028] To solve the above technical problems, according to a third aspect of the present invention, a flash memory is further provided, which is fabricated by the above method for fabricating a flash memory.

[0029] In summary, in the flash memory layout, flash memory, and manufacturing method thereof provided by this invention, the flash memory layout includes an active area layout layer, a first floating gate layout layer, a second floating gate layout layer, and a control gate contact hole layout layer. The active area layout layer includes multiple active areas arranged parallel to each other along a first direction. The active areas include effective active areas located within the effective area and virtual active areas located within the connection area. The first floating gate layout layer includes multiple first floating gate patterns arranged parallel to each other along a second direction. The second floating gate layout layer includes multiple second floating gate patterns arranged parallel to each other along a second direction. The second floating gate patterns are arranged opposite each other on both sides of the connection area, and within each connection area, the second floating gate patterns are spaced apart. The second floating gate pattern is disposed on the first floating gate pattern, and adjacent first floating gate patterns are disposed in different connection areas. The control gate contact hole plate layer includes control gate contact hole patterns located in the connection area and extending along the second direction. The present invention uses a mask plate made from the above plate layer for patterning to finally form floating gates and control gates. Each floating gate is provided with a set of two isolated control gates. Adjacent control gates are separated in different connection areas. The first control gate in each control gate set has a connecting block extending to the second control gate of the upper group, and the second control gate has a connecting block extending to the first control gate of the lower group. The connecting blocks are used to form contact holes to lead out the control gates. Compared with the prior art, the connection area of ​​the present invention is reduced, the utilization rate of the effective area of ​​the memory cell is improved, and the process window is increased. Furthermore, since the active area structure in the connection area is repetitive, there is no large shallow trench isolation structure, so the active area does not need optical correction and there is no load effect, thereby increasing the process window.

[0030] Furthermore, the first floating gate pattern in the connection area is no longer S-shaped, eliminating the need to consider control gate bridging caused by small floating gate spacing, thus increasing the process window.

[0031] Furthermore, the control gate contact hole pattern is no longer an island shape, so there is no need to consider that the contact hole is formed in the island area of ​​the control gate contact hole pattern. The process window of the control gate contact hole pattern and the contact hole is increased.

[0032] Furthermore, the control gate in the connection area near the edge region is isolated, so MPOL ET does not need to etch the control gate in the edge region, thus increasing the process window of MPOL ET. Attached Figure Description

[0033] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0034] Figure 1This is a schematic diagram of the layout of the middle position of the storage cell array of a traditional flash memory.

[0035] Figure 2 This is a schematic diagram of the layout of the edge positions of the storage cell array in a traditional flash memory.

[0036] Figure 3 This is a schematic diagram of the layout of the storage cell array of a flash memory provided in an embodiment of the present invention.

[0037] Figure 4 This is a schematic diagram of the edge position of the storage cell array of a flash memory provided in an embodiment of the present invention.

[0038] Figure 5 This is a flowchart of a method for manufacturing a flash memory according to an embodiment of the present invention.

[0039] In the attached image:

[0040] Figure 1 and Figure 2 middle,

[0041] 10-Active region; 10a-Valid active region; 10b-Reference memory cell active region; 10c-Virtual active region; 11-First floating gate pattern; 12-Second floating gate pattern; 13-Control gate contact hole pattern; 14-Control gate; 15-Contact hole; I-Valid region; II-Connection region; III-Edge region.

[0042] Figure 3 and Figure 4 middle,

[0043] 100 - Active region; 100a - Effective active region; 100b - Virtual active region; 110 - First floating gate pattern; 120 - Second floating gate pattern; 130 - Control gate contact hole pattern; 140 - Control gate; 150 - Contact hole; I - Effective region; II - Connection region; III - Edge region. Detailed Implementation

[0044] Figure 1 This is a schematic diagram showing the layout of the middle position of the memory cell array in a traditional flash memory. Please refer to it. Figure 1As shown, the layout of the flash memory includes multiple active regions I and connection regions II (also known as strip regions or strap regions) located between adjacent active regions I. The connection regions II are used to bring out the control gate. The layout of the flash memory includes an active region layer (ACT), a first floating gate layer (FLGT), a second floating gate layer (FLGT2), and a control gate contact hole layer (CGCT). The active region layer includes multiple active regions 10 arranged parallel to a first direction x and extending along a second direction y. Each active region 10 includes an active active region 10a located within the active regions I, a reference memory cell active region 10b located on one side of the connection regions II and close to the active active region 10a, and two virtual active regions 10c located on both sides of the connection regions II. The first direction x is perpendicular to the second direction y.

[0045] The first floating grid layer includes a plurality of first floating grid patterns 11 arranged parallel to the second direction y and extending along the first direction x. The first floating grid pattern 11 includes straight strip patterns at both ends and S-shaped patterns located between the straight strip patterns. The S-shaped patterns are located within the connection area II, and the S-shaped patterns of two adjacent first floating grid patterns 11 are opposite and located at different positions in the connection area II. The first floating grid patterns 11 of the same shape are arranged at intervals.

[0046] The second floating grid layer includes multiple second floating grid graphics 12, which are located between adjacent first floating grid graphics 11. A second floating grid graphic 12 is positioned between the S-shaped graphic of each first floating grid graphic 11 and the straight bar graphic of the adjacent first floating grid graphic 11. Within the connection area II, the second floating grid graphics 12 have two columns arranged at intervals.

[0047] The control gate contact hole layer includes multiple control gate contact hole patterns 13, which are located within the connection area II and on the second floating gate pattern 12 and the adjacent S-shaped first floating gate pattern 11. Two columns of control gate contact hole patterns 13 are provided within each connection area II, with the two columns arranged at intervals.

[0048] An active area mask is created using an active area plate layer, a first floating grid mask is created using a first floating grid plate layer, a second floating grid mask is created using a second floating grid plate layer, and a control grid contact hole mask is created using a control grid contact hole plate layer.

[0049] After forming the control gate polysilicon layer, the control gate polysilicon layer in the area covered by the second floating gate mask is first removed by exposure and development. Then, the control gate polysilicon layer in the area covered by the control gate contact hole mask is protected by exposure and development. The control gate polysilicon layer outside the areas covered by the first floating gate mask and the control gate contact hole mask is then etched away, finally forming the floating gate (not shown) and... Figure 1 The control gate 14 shown. Each of the floating gates has a set of two isolated control gates 14 formed on it. Figure 1 Only three sets of the control gates 14 are shown. Two control gates 14 in each set are S-shaped within the connection area II, and this S-shape is located in the same area as the S-shape of the first floating gate pattern 11. The control gates 14 are led out by forming contact holes 15 on these S-shapes. The contact holes 15 are formed through the control gate contact hole pattern 13.

[0050] However, from the first direction x, assuming the pitch between the center lines of adjacent active regions 10 is 1 unit length, since the distance between the active regions 10 at both ends of the connection region II is relatively large, two virtual active regions 10c need to be set on each side of the connection region II to ensure the surrounding environment of the effective active region 10a. The spacing of the effective active regions 10a is 18, and the utilization rate of the effective area of ​​the storage unit is 256 / (256+18)=93.43%, which is relatively low.

[0051] Looking at the second direction y, assuming the distance between the center lines of adjacent first floating gate patterns 11 is 1 unit length, the spacing of the first floating gate patterns 11 in the effective area I is 0.53, while the spacing of the first floating gate patterns 11 in the connecting area II is 0.43. The process window is smaller, which can easily cause control gate bridging.

[0052] In addition, the control gate contact hole pattern 13 is a small square island. The contact hole 15 needs to be formed on the control gate contact hole pattern 13 in order to lead out the control gate 14. The exposure overlay accuracy requirements of the control gate contact hole pattern 13 and the contact hole 15 are relatively high.

[0053] Figure 2 This is a schematic diagram showing the layout of the edge positions of the memory cell array in a traditional flash memory. Please refer to it. Figure 2As shown, the layout of the flash memory includes an edge region III, and a connection region II is provided between the edge region III and the active region I. In the edge region III, the end of the first floating gate pattern 11 needs to be etched using MPOL ET (memory poly ET) to ensure that the two control gates 14 on the floating gate do not conduct. However, due to the complex structure of the memory cell, MPOL ET requires etching the silicon nitride in the edge region III as well as the silicon oxide and polysilicon at the end of the memory cell, which places high demands on the etching process.

[0054] To address the aforementioned issues, the inventors of this application provide a flash memory layout, a flash memory, and a method for manufacturing the same. By bringing out two control gates on the same floating gate through contact holes on two oppositely positioned connecting blocks, the utilization rate of the effective area of ​​the memory cell is improved, and the process window is increased.

[0055] Specifically, the present invention provides a flash memory layout including multiple active regions and connection regions located between adjacent active regions. The flash memory layout includes: an active region layout layer, which includes multiple active regions arranged parallel to each other along a first direction, the active regions including active active regions located within the active regions and virtual active regions located within the connection regions; a first floating gate layout layer, which includes multiple first floating gate patterns arranged parallel to each other along a second direction; a second floating gate layout layer, which includes multiple second floating gate patterns arranged parallel to each other along the second direction, the second floating gate patterns being arranged opposite each other on both sides of the connection regions, and within each connection region, the second floating gate patterns are arranged in alternating rows on the first floating gate patterns, and adjacent first floating gate patterns are provided with second floating gate patterns in different connection regions; and a control gate contact hole layout layer, which includes control gate contact hole patterns located within the connection regions and extending along the second direction.

[0056] The present invention also provides a method for fabricating a flash memory, which is fabricated using the flash memory layout described above. The method includes: providing a substrate, the substrate including a plurality of effective regions and connection regions located between adjacent effective regions; forming a floating gate polysilicon layer and a control gate polysilicon layer on the substrate; patterning the control gate polysilicon layer using a first mask, wherein the first mask has a second floating gate layer; patterning the control gate polysilicon layer and the floating gate polysilicon layer using a second mask, wherein the second mask has a first floating gate layer; patterning the control gate polysilicon layer and the floating gate polysilicon layer using a third mask to form a control gate and a floating gate, wherein the third mask has a control gate contact hole layer; each floating gate is provided with a set of two isolated control gates, each adjacent set of control gates is separated in different connection regions, the first control gate in each set of control gates has a connection block extending upward to the second control gate of the next set, and the second control gate has a connection block extending downward to the first control gate of the next set, wherein contact holes are formed on the connection blocks.

[0057] The present invention also provides a flash memory, which is manufactured using the flash memory manufacturing method described above.

[0058] The flash memory layout, flash memory, and manufacturing method provided by this invention reduce the area of ​​the connection region, improve the utilization rate of the effective area of ​​the memory cells, and increase the process window. Furthermore, because the connection region contains a repeating active region structure and there are no large shallow trench isolation structures, the active region does not require optical correction and there is no loading effect, thereby increasing the process window.

[0059] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0060] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature.

[0061] Figure 3 This is a schematic diagram of the layout of the storage cell array of a flash memory according to an embodiment of the present invention. Please refer to... Figure 3 As shown, the flash memory layout includes multiple active regions I and connection regions II located between adjacent active regions I. The flash memory layout includes:

[0062] An active area layer, the active area layer comprising a plurality of active areas 100 arranged in parallel along a first direction x, the active area 100 including an effective active area 100a located in the effective area I and a virtual active area 100b located in the connection area II;

[0063] The first floating grid layer contains a plurality of first floating grid graphics 110 arranged parallel to the second direction y.

[0064] The second floating grid layer includes a plurality of second floating grid patterns 120 arranged parallel to each other along the second direction y. The second floating grid patterns 120 are arranged opposite each other on both sides of the connecting area II. Within each connecting area II, the second floating grid patterns 120 are arranged in alternating rows on the first floating grid patterns 110. Adjacent first floating grid patterns 110 are provided with second floating grid patterns 120 in different connecting areas II.

[0065] The control gate contact hole plate layer includes a control gate contact hole pattern 130 located within the connection area II and extending along the second direction y.

[0066] In this embodiment, the plurality of active regions 100 are arranged in a straight strip shape parallel to each other along the first direction x and extending along the second direction y, wherein the first direction and the second direction are perpendicular to each other. For example, two virtual active regions 100b are provided within the connection region II. No virtual active region needs to be provided between the connection region II and the effective region I.

[0067] Compared with the prior art, the present invention reduces the area of ​​the connection region II, improves the utilization rate of the effective area of ​​the memory cell, and increases the process window. Furthermore, both the effective region I and the connection region II contain repeating active region structures, and the connection region II does not contain large shallow trench isolation (STI) structures, eliminating the need for optical correction of the active region and preventing loading effects, thereby increasing the process window.

[0068] Multiple first floating grid patterns 110 are arranged in a straight strip shape parallel to the second direction y and extend along the first direction x. Within the effective area I and the connecting area II, the first floating grid patterns 110 are all arranged in a straight strip shape, parallel to the second direction y and extending along the first direction x. Figure 1 Compared to the first floating gate pattern 11 composed of straight bars and S-shapes, this embodiment does not need to consider control gate bridging caused by the small floating gate spacing, thus increasing the process window.

[0069] The second floating gate pattern 120 is a straight strip in the second direction y, and the extension lines of the second floating gate patterns 120 on the same side within the same connection area II overlap in the second direction y. Within the same connection area II, the second floating gate patterns 120 are arranged in alternating rows on the first floating gate patterns 110, and adjacent first floating gate patterns 110 are provided with second floating gate patterns 120 in different connection areas II. For example, Figure 3 From left to right, in the first connection area II, the second floating grid pattern 120 is sequentially set on the first floating grid pattern 110 in the first row, third row, and fifth row; in the second connection area II, the second floating grid pattern 120 is sequentially set on the first floating grid pattern 110 in the second row, fourth row, and sixth row; in the third connection area II, the second floating grid pattern 120 is sequentially set on the first floating grid pattern 110 in the first row, third row, and fifth row, and so on, but not limited to this.

[0070] The control gate contact hole pattern 130 is elongated and extends along the second direction y. The control gate contact hole pattern 130 partially overlaps with the second floating gate patterns 120 on opposite sides within the connection area II. Alternatively, in other embodiments, the control gate contact hole pattern 130 and the second floating gate patterns 120 on opposite sides within the connection area II may not overlap, for example, they may be spaced apart or just touching. Only one control gate contact hole pattern 130 is provided in each connection area II. The control gate contact hole pattern 130 is elongated and extends along the second direction y. Figure 1 Compared to the control gate contact hole pattern 13, which is a small island in the middle, in this embodiment there is no need to consider that the contact hole is formed in the island area of ​​the control gate contact hole pattern, and the process window of the control gate contact hole pattern 130 and the contact hole is increased.

[0071] Figure 4 This is a schematic diagram of the edge positions of the memory cell array of a flash memory according to an embodiment of the present invention. Please refer to... Figure 4 As shown, the flash memory layout also includes an edge region III. A connection region II is disposed between the edge region III and the active region I. The second floating gate pattern 120 on the side of the connection region II closest to the edge region III is a straight strip and extends along the second direction. Alternatively, in this embodiment, a virtual active region 100b may be disposed between the connection region II near the edge region III and the active region I. In other embodiments, the virtual active region 100b may not be disposed between the connection region II near the edge region III and the active region I; this invention does not limit this.

[0072] In this embodiment, the number of active regions 100 within each effective region I is 128, but not limited to this. Assuming the pitch between the centerlines of the active regions 100 is 1 unit length, and the space between the effective active regions at the left and right ends of the connecting region II is 2.4, the utilization rate of the effective area of ​​the storage unit is 128 / (128+2.4) = 98.16%. Figure 1 Compared to 93.43% in the previous model, the utilization rate of its storage unit effective area has been greatly improved.

[0073] Using the above-mentioned plate layers, the final result can be as follows: Figure 3 The control gate 140 is shown. Please refer to [reference needed]. Figure 3As shown, each of the floating gates is provided with a set of two isolated control gates 140. Each set of adjacent control gates 140 is separated in different connection areas II. The first control gate in each set of control gates 140 has a connecting block extending to the second control gate of the upper set, and the second control gate has a connecting block extending to the first control gate of the lower set. The connecting blocks are used to form contact holes 150.

[0074] In this embodiment, for example, the storage cell area of ​​Nord flash is 0.042μm. 2 Taking the following example, at the middle position of the storage cell, the width of the active region 100 is 0.145 μm, and the spacing between adjacent active regions 100 is 0.08 μm; the width of the first floating gate pattern 110 is 0.176 μm, and the spacing between adjacent first floating gate patterns 110 is 0.2 μm; the width (dimension in the first direction x) of the second floating gate pattern 120 is 0.12 μm, and the length (dimension in the second direction y) of the second floating gate pattern 120 is 0.436 μm.

[0075] Figure 5 This is a flowchart illustrating a method for manufacturing a flash memory according to an embodiment of the present invention. Please refer to it. Figure 5 As shown, the method for manufacturing the flash memory includes the following steps:

[0076] S1: A substrate is provided, the substrate including a plurality of effective regions and a connection region located between adjacent effective regions;

[0077] S2: A floating gate polysilicon layer and a control gate polysilicon layer are formed on the substrate;

[0078] S3: The control gate polysilicon layer is patterned using a first mask, wherein the first mask has a second floating gate layer;

[0079] S4: Patterning the control gate polysilicon layer and the floating gate polysilicon layer using a second mask, wherein the second mask has a first floating gate layer; and

[0080] S5: The control gate polysilicon layer and the floating gate polysilicon layer are patterned using a third mask to form a control gate and a floating gate. The third mask has a control gate contact hole layer.

[0081] Each of the floating grids is provided with a set of two isolated control grids. Each set of adjacent control grids is separated in different connection areas. The first control grid in each set of control grids has a connecting block extending to the second control grid of the next set, and the second control grid has a connecting block extending to the first control grid of the next set. The connecting blocks are used to form contact holes.

[0082] Next, we will combine Figure 5 and Figure 3 , Figure 4 The method for manufacturing the flash memory provided by this invention will be described in detail. It is understood that... Figure 3 and Figure 4 The display shows the layout, which is used to create a mask. In the process of manufacturing flash memory, this mask is used for patterning and can eventually form a control gate.

[0083] In step S1, a substrate is provided, the substrate including a plurality of active regions I and a connection region II located between adjacent active regions I. The connection region II is used to bring out the control gate subsequently formed. This step also includes ion implantation of the substrate to form active regions 100 using a mask made of an active region layer (or a mask having the active region layer).

[0084] The active area layer includes multiple active areas 100 arranged in parallel along the first direction x. The active area 100 includes an active active area 100a located in the active area I and a virtual active area 100b located in the connection area II.

[0085] In step S2, a floating gate polysilicon layer and a control gate polysilicon layer are formed on the substrate. Of course, a dielectric layer may also be formed between the floating gate polysilicon layer and the control gate polysilicon layer. Before forming the floating gate polysilicon layer, a gate oxide layer may also be formed on the substrate. Since this embodiment focuses on forming the control gate using the layout described above, the fabrication of the remaining layers can be performed using existing methods, and will not be elaborated further in this embodiment.

[0086] In step S3, the control gate polysilicon layer is patterned using a first mask, which has a second floating gate layer. Please refer to [reference needed]. Figure 3 As shown, the second floating gate layer includes multiple second floating gate patterns 120 arranged parallel to each other along the second direction y. The second floating gate patterns 120 are arranged opposite each other on both sides of the connection area II. Within each connection area II, the second floating gate patterns 120 are arranged in alternating rows on the first floating gate patterns 110. Adjacent first floating gate patterns 110 are provided with second floating gate patterns 120 in different connection areas II. In this embodiment, a first mask made from the second floating gate layer is used to pattern the control gate polysilicon layer.

[0087] In step S4, the control gate polysilicon layer and the floating gate polysilicon layer are patterned using a second mask, the second mask having a first floating gate layer. Please refer to [reference needed]. Figure 3As shown, the first floating gate layer contains a plurality of first floating gate patterns 110 arranged parallel to the second direction y. In this embodiment, a second mask made from the first floating gate layer is used to pattern the control gate polysilicon layer and the floating gate polysilicon layer.

[0088] In step S5, the control gate polysilicon layer and the floating gate polysilicon layer are patterned using a third mask to form the control gate and the floating gate. The third mask has a control gate contact hole layer. Please refer to [reference needed]. Figure 3 As shown, the control gate contact hole pattern layer includes a control gate contact hole pattern 130 located within the connection area II and extending along the second direction y. In this embodiment, a third mask made from the control gate contact hole pattern layer is used to pattern the control gate polysilicon layer and the floating gate polysilicon layer, ultimately forming the floating gate and the control gate.

[0089] It is understandable that in this embodiment, the first mask, the second mask, and the third mask are all made by... Figure 3 The layers shown are created by various methods, and other masks or other production steps may be included between the above steps. This invention does not limit the scope of these methods.

[0090] Please refer to Figure 3 As shown, the floating gates fabricated using the flash memory fabrication method described in this embodiment are arranged parallel to the second direction y and extend along the first direction x. (Refer to...) Figure 3 The location of the first floating gate pattern 110 in the diagram. Each floating gate has a set of two isolated control gates 140. Adjacent sets of control gates 140 are separated in different connection areas II. The first control gate in each set of control gates 140 has a connecting block extending upward to a second control gate of the next set, and the second control gate has a connecting block extending downward to a first control gate of the next set. The connecting blocks are used to form contact holes 150. The contact holes 150 are formed during patterning using a third mask layer.

[0091] In this embodiment, each group of control gates 140 is separated by every other connection region II, and adjacent groups of control gates 140 are separated in different connection regions II. For example, Figure 3 From left to right, in the first connection area II, the control gates 140 in the first, third, and fifth rows are separated; in the second connection area II, the control gates 140 in the second, fourth, and sixth rows are separated; in the third connection area II, the control gates 140 in the first, third, and fifth rows are separated, and so on.

[0092] Within the connection area II where the control gate 140 is not isolated, for example Figure 3The control gate 140 on the fourth row of floating gates is located within the first connection area II. The upper first control gate is led out through a contact hole 150 on the connecting block extending upwards, and the lower second control gate is led out through a contact hole 150 on the connecting block extending downwards. It should be noted that... Figure 3 Only three sets of control gates and one of the other two sets of control gates are shown in the figure. In fact, each of the floating gates can have a set of control gates formed on it.

[0093] In this embodiment, the length of the control gate 140 includes two active areas I and one connection area II, that is, it includes 256 active active areas 100 and 2 virtual active areas 100b, with 2 virtual active areas 100b set every 128 active active areas 100a.

[0094] Please refer to Figure 4 As shown, the substrate further includes an edge region III, and a connection region II is disposed between the edge region III and the effective region I. Each control gate 140 is isolated in the connection region II near the edge region III. Therefore, MPOL ET does not require etching the control gate in the edge region III, and the process window of MPOL ET is increased.

[0095] The present invention also provides a flash memory, which is manufactured using the flash memory manufacturing method described above.

[0096] In the flash memory, each of the floating gates is provided with a set of two isolated control gates. Each set of adjacent control gates is separated in different connection areas. The first control gate in each set of control gates has a connecting block extending to the second control gate of the next set, and the second control gate has a connecting block extending to the first control gate of the next set. The connecting blocks are used to form contact holes.

[0097] In summary, in the flash memory layout, flash memory, and manufacturing method thereof provided by this invention, the flash memory layout includes an active area layout layer, a first floating gate layout layer, a second floating gate layout layer, and a control gate contact hole layout layer. The active area layout layer includes multiple active areas arranged parallel to each other along a first direction. The active areas include effective active areas located within the effective area and virtual active areas located within the connection area. The first floating gate layout layer includes multiple first floating gate patterns arranged parallel to each other along a second direction. The second floating gate layout layer includes multiple second floating gate patterns arranged parallel to each other along a second direction. The second floating gate patterns are arranged opposite each other on both sides of the connection area, and within each connection area, the second floating gate patterns are spaced apart. The second floating gate pattern is disposed on the first floating gate pattern, and adjacent first floating gate patterns are disposed on different connection areas. The control gate contact hole plate layer includes control gate contact hole patterns located in the connection area and extending along the second direction. The present invention uses a mask plate made from the above plate layer for patterning to finally form floating gates and control gates. Each floating gate is provided with a set of two isolated control gates. Adjacent control gates are separated in different connection areas. The first control gate in each control gate set has a connecting block extending to the second control gate of the upper group, and the second control gate has a connecting block extending to the first control gate of the lower group. The connecting blocks are used to form contact holes to lead out the control gates. Compared with the prior art, the connection area of ​​the present invention is reduced, the utilization rate of the effective area of ​​the memory cell is improved, and the process window is increased. Furthermore, since the active area structure in the connection area is repetitive, there is no large shallow trench isolation structure, so the active area does not need optical correction and there is no load effect, thereby increasing the process window.

[0098] Furthermore, the first floating gate pattern in the connection area is no longer S-shaped, eliminating the need to consider control gate bridging caused by small floating gate spacing, thus increasing the process window.

[0099] Furthermore, the control gate contact hole pattern is no longer an island shape, so there is no need to consider that the contact hole is formed in the island area of ​​the control gate contact hole pattern. The process window of the control gate contact hole pattern and the contact hole is increased.

[0100] Furthermore, the control gate in the connection area near the edge region is isolated, so MPOL ET does not need to etch the control gate in the edge region, thus increasing the process window of MPOL ET.

[0101] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A flash memory layout, comprising a plurality of active regions and connection regions located between adjacent active regions, characterized in that, The flash memory layout includes: An active area layer, the active area layer comprising a plurality of active areas arranged in parallel along a first direction, the active areas comprising an active active area located within the active area and a virtual active area located within the connecting area; The first floating grid layer includes a plurality of first floating grid graphics arranged in parallel along the second direction; The second floating grid layer includes multiple second floating grid patterns arranged parallel to each other along a second direction. The second floating grid patterns are arranged opposite each other on both sides of the connecting area. Within each connecting area, the second floating grid patterns are arranged in alternating rows on top of the first floating grid patterns. Adjacent first floating grid patterns have second floating grid patterns arranged in different connecting areas. A control gate contact hole plate layer, the control gate contact hole plate layer including control gate contact hole patterns located within the connection area and extending along the second direction.

2. The flash memory layout according to claim 1, characterized in that, The plurality of active regions are arranged in a straight strip shape parallel to each other along the first direction and extend along the second direction; the plurality of first floating gate patterns are arranged in a straight strip shape parallel to each other along the second direction and extend along the first direction; the first direction and the second direction are perpendicular to each other.

3. The flash memory layout according to claim 2, characterized in that, The second floating gate pattern is a straight strip in the second direction, and the extension lines of the second floating gate patterns on the same side within the same connection area overlap in the second direction.

4. The flash memory layout according to claim 3, characterized in that, The control gate contact hole pattern is elongated and extends along the second direction, and the control gate contact hole pattern partially overlaps with the second floating gate pattern on both sides of the connection area.

5. The flash memory layout according to claim 4, characterized in that, The flash memory layout also includes an edge region, and a connection region is provided between the edge region and the active region. The second floating gate pattern on the side of the connection region closest to the edge region is a straight strip and extends along the second direction.

6. The flash memory layout according to claim 1, characterized in that, The connection area is provided with two virtual active areas.

7. The flash memory layout according to claim 1, characterized in that, The number of effective active regions within each effective region is 128.

8. A method for manufacturing a flash memory, characterized in that, The flash memory layout as described in any one of claims 1 to 7 is used for fabrication, and the fabrication method includes: A substrate is provided, the substrate including a plurality of effective regions and a connection region located between adjacent effective regions; A floating gate polysilicon layer and a control gate polysilicon layer are formed on the substrate; The control gate polysilicon layer is patterned using a first mask, the first mask having a second floating gate layer; The control gate polysilicon layer and the floating gate polysilicon layer are patterned using a second mask, the second mask having a first floating gate layer; and The control gate polysilicon layer and the floating gate polysilicon layer are patterned using a third mask to form a control gate and a floating gate. The third mask has a control gate contact hole layer. Each of the floating grids is provided with a set of two isolated control grids. Each set of adjacent control grids is separated in different connection areas. The first control grid in each set of control grids has a connecting block extending to the second control grid of the next set, and the second control grid has a connecting block extending to the first control grid of the next set. The connecting blocks are used to form contact holes.

9. The method for manufacturing a flash memory according to claim 8, characterized in that, Each group of control gates is separated by every other connection area.

10. The method for manufacturing a flash memory according to claim 9, characterized in that, The length of the control gate includes 256 active regions and 2 virtual active regions.

11. The method for manufacturing a flash memory according to claim 8, characterized in that, The substrate further includes an edge region, and a connection region is provided between the edge region and the effective region. Each control gate is isolated in the connection region on the side closest to the edge region.

12. A flash memory, characterized in that, It is manufactured using the method for manufacturing a flash memory as described in any one of claims 8 to 11.

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