Memory device, method of manufacturing the same, and electronic device including the memory device

Abstract

A memory device, a manufacturing method thereof, and an electronic device including the memory device are disclosed. According to embodiments, the memory device can include: a plurality of first device layers vertically stacked on a substrate, each first device layer including first and second source / drain regions and a channel region therebetween respectively disposed at a lower vertical height and an upper vertical height; a plurality of second device layers stacked on the first device layers, each second device layer including third and fourth source / drain regions and a channel region therebetween respectively disposed at the lower vertical height and the upper vertical height; and a gate stack vertically extending to pass through the first and second device layers. The gate stack includes a gate conductor layer and a storage functional layer disposed between the gate conductor layer and each device layer, defining a memory cell at an intersection of the gate stack and each device layer. At a location where the first and second device layers are adjacent, the gate stack has a surface in a meander shape.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically to memory devices, methods of manufacturing the same, and electronic devices including such memory devices. Background Technology

[0002] In horizontal devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), the source, gate, and drain are arranged in a direction generally parallel to the substrate surface. Due to this arrangement, horizontal devices are not easily miniaturized further. In contrast, in vertical devices, the source, gate, and drain are arranged in a direction generally perpendicular to the substrate surface. Therefore, vertical devices are easier to miniaturize than horizontal devices. Furthermore, vertical devices are easier to stack on top of each other, making them suitable for three-dimensional (3D) structures.

[0003] The storage capacity of memory devices can be increased by stacking multiple layers of memory cell arrays. However, as the number of stacked layers increases, device performance deteriorates. For example, the channel material is typically polycrystalline silicon, which has increased resistance compared to monocrystalline silicon. In addition, it is difficult to etch holes with large aspect ratios (e.g., > about 40 to 80), or the maximum depth of the etched holes is limited (e.g., < about 4 to 8 μm), which restricts the increase in the number of stacked layers. Summary of the Invention

[0004] In view of this, the purpose of this disclosure is at least in part to provide a memory device with improved performance, a method of manufacturing the same, and an electronic device including such a memory device.

[0005] According to one aspect of this disclosure, a memory device is provided, comprising: a plurality of first device layers vertically stacked on a substrate, each first device layer including a first source / drain region disposed at a lower vertical height in the first device layer, a second source / drain region disposed at an upper vertical height in the first device layer, and a channel region between the first source / drain region and the second source / drain region; and a plurality of second device layers vertically stacked on the plurality of first device layers, each second device layer including a third source / drain region disposed at a lower vertical height in the second device layer, and a channel region disposed at an upper vertical height in the second device layer. The fourth source / drain region at vertical height and the channel region between the third source / drain region and the fourth source / drain region; and a gate stack extending vertically relative to the substrate through the plurality of first device layers and the plurality of second device layers, wherein the gate stack includes a gate conductor layer and a storage function layer disposed between the gate conductor layer and each of the plurality of first device layers and the plurality of second device layers, defining a storage cell where the gate stack intersects with each device layer, wherein the gate stack has a bent surface at the adjacency of the plurality of first device layers and the plurality of second device layers.

[0006] According to another aspect of this disclosure, a method for manufacturing a memory device is provided, comprising: forming a first stack of a plurality of first device layers and a plurality of first sacrificial layers on a substrate, each first device layer having a first sacrificial layer at least on one side; forming a first processing channel extending vertically relative to the substrate through the first stack based on a mask; growing a seed layer continuously extending on the first stack using the uppermost first device layer of the first stack as a seed; forming a second stack of a plurality of second device layers and a plurality of second sacrificial layers on the seed layer, each second device layer having a second sacrificial layer at least on one side; forming a second processing channel extending vertically relative to the substrate through the second stack based on a mask, wherein the second processing channel and the first device layer are connected in a first stack. A first processing channel is connected; a first sacrificial layer is removed via the first processing channel, and a second sacrificial layer is removed via a second processing channel; a first isolation layer is formed in the space released due to the removal of the first sacrificial layer via the first processing channel; a second isolation layer is formed in the space released due to the removal of the second sacrificial layer via the second processing channel; a first gate stack is formed in the first processing channel, the first gate stack including a first gate conductor layer and a first storage function layer disposed between the first gate conductor layer and a first device layer; and a second gate stack is formed in the second processing channel, the second gate stack including a second gate conductor layer and a second storage function layer disposed between the second gate conductor layer and a second device layer.

[0007] According to another aspect of this disclosure, an electronic device is provided, including the aforementioned storage device.

[0008] According to embodiments of this disclosure, a memory device may include a stack of first device layers and a stack of second device layers. A gate stack may extend vertically through each of the stacked layers. The portion of the gate stack extending through each stack may be formed within a processing channel or via through that stack. The corresponding processing channels or vias in different stacks may be formed separately. Thus, the depth of each processing channel or via may correspond to the thickness of the corresponding stack, rather than the total thickness of all device layers in the memory device. Therefore, the etching and / or filling difficulty for forming the processing channels or vias accommodating the gate stack can be reduced. Conductive metal layers may be provided as bit line / source line connections to reduce resistance. Additionally, stacks of single-crystal materials can be used as building blocks to construct three-dimensional (3D) memory devices. Therefore, when multiple memory cells are stacked on top of each other, an increase in resistance can be suppressed. Attached Figure Description

[0009] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0010] Figures 1 to 16(c) A schematic diagram of some stages in the process of manufacturing a storage device according to an embodiment of the present disclosure is shown;

[0011] Figure 17 An equivalent circuit diagram of an AND-type memory device according to an embodiment of the present disclosure is shown schematically;

[0012] Figure 18 An equivalent circuit diagram of a NOR-type memory device according to an embodiment of the present disclosure is shown schematically.

[0013] Figures 19 to 23 A schematic diagram of some stages in the process of manufacturing a storage device according to another embodiment of the present disclosure is shown;

[0014] Figures 24 to 26 A schematic diagram of some stages in the process of manufacturing a storage device according to another embodiment of the present disclosure is shown;

[0015] Figures 27 to 30 A schematic diagram of some stages in the process of manufacturing a storage device according to another embodiment of the present disclosure is shown.

[0016] in, Figure 2(a) , 16(a) This is a top view; Figure 2(a) shows the positions of lines AA′ and BB′.

[0017] Figure 1 , 2(b) Sections 3 to 7, 8(a), 8(b), 9 to 15(a), 16(b), and 19 to 30 are cross-sectional views along line AA′.

[0018] Figure 16(c) is a cross-sectional view along line BB′.

[0019] Figure 15(b) , 15(c) Figure 15(d) is a schematic enlarged view of different examples of part P in Figure 15(a).

[0020] Throughout the accompanying drawings, the same or similar reference numerals denote the same or similar parts. Detailed Implementation

[0021] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0022] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0023] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0024] The memory device according to embodiments of this disclosure is based on a vertical device. The vertical device may include an active region disposed on a substrate in a vertical direction (generally perpendicular to the substrate surface), including source / drain regions disposed at different vertical heights (e.g., at the top and bottom ends respectively) and a channel region located between the source / drain regions. A conductive path can be formed between the source / drain regions through the channel region. In the active region, the source / drain regions and the channel region may be defined, for example, by doping concentration.

[0025] According to embodiments of this disclosure, the active region can be defined by a device layer on a substrate. For example, the device layer can be a semiconductor material layer, where source / drain regions can be formed at opposite ends in the vertical direction by doping (e.g., in-situ doping described below), and a channel region can be formed in the middle of the semiconductor material layer in the vertical direction. Alternatively, the device layer can be a stack of source / drain layers, a channel layer, and source / drain layers, where the source / drain layers can be in-situ doped during growth to form source / drain regions. A gate stack can extend through the device layer, so that the active region can surround the outer periphery of the gate stack. Here, the gate stack can include at least one of a storage functional layer, such as a charge trapping material or a ferroelectric material, to realize a storage function. Thus, the gate stack cooperates with the opposite active region to define a memory cell. Here, the memory cell can be a flash memory cell.

[0026] Multiple gate stacks can be configured to extend through the device layer, thereby defining multiple memory cells at the intersections of these gate stacks and the device layer. These memory cells are arranged in an array (e.g., typically a two-dimensional array arranged in rows and columns) in the plane of the device layer, corresponding to the multiple gate stacks.

[0027] Due to the ease of stacking vertical devices, the memory devices according to embodiments of this disclosure can be three-dimensional (3D) arrays. Specifically, multiple such device layers can be arranged in the vertical direction. The gate stack can extend vertically through these multiple device layers. Thus, for a single gate stack, it intersects with the multiple device layers stacked in the vertical direction to define multiple memory cells stacked in the vertical direction.

[0028] To increase the capacity of memory devices, the number of vertically stacked device layers can be large. According to embodiments of this disclosure, a memory device may include several stacks, each containing multiple device layers. Gate stacks may extend vertically through the stacks stacked on top of each other. The portions of the gate stack extending through each stack may be formed within processing channels or vias passing through that stack. The corresponding processing channels or vias in different stacks may be formed separately. Thus, the depth of each processing channel or via may correspond to the thickness of the corresponding stack, rather than the total thickness of all device layers in the memory device. Therefore, the etching and / or filling difficulty for forming the processing channels or vias accommodating the gate stack can be reduced.

[0029] Because they are formed separately, the processing channels or holes in each layer may not be aligned with each other. Therefore, the gate stack can have bending shapes corresponding to this misalignment. Corresponding to the number of layers stacked together, the gate stack can have multiple bending shapes.

[0030] The grid stack may include a first portion adjacent to the bend below the bend, a second portion adjacent to the bend above the bend, and a connecting portion between the first and second portions corresponding to the bend. The connecting portion may have a reduced width relative to the first portion (particularly the top of the first portion) and the second portion (particularly the bottom of the second portion), thereby forming the bend shape. Note that the first portion, the second portion, and the connecting portion are merely geometric divisions and do not necessarily mean that these portions are physically separated from each other. For example, the first portion, the second portion, and the connecting portion may be formed together as a single unit, or they may be formed separately and include portions that are separate from each other.

[0031] Memory devices according to embodiments of this disclosure may have a NOR ("NOR") configuration or an AND ("AND") configuration. In a NOR-type memory device, each memory cell may be connected to a common source line. Given this configuration, to save wiring, two adjacent memory cells may share the same source line connection in the vertical direction. For example, for these two adjacent memory cells, their respective source / drain regions at their proximal ends (i.e., the ends where the two memory cells are close to each other) may serve as source regions and are therefore electrically connected to the source line, for example, through a common contact; their respective source / drain regions at their distal ends (i.e., the ends where the two memory cells are far from each other) may serve as drain regions and may be connected to different bit lines respectively.

[0032] The device layer can be formed through epitaxial growth and can be made of single-crystal semiconductor material. Compared to conventional processes that form multiple gate stacks stacked on top of each other and then form vertical active regions through these gate stacks, it is easier to form single-crystal active regions (especially channel regions). Furthermore, in-situ doping can be performed during growth to create a vertical doping distribution within the device layer. Doping concentration interfaces can exist between different doped portions. The device layer can constitute a bulk material, and therefore the channel region is formed within the bulk material. In this case, the process is relatively simple.

[0033] A conductive metal layer may be disposed on at least one of the lower and upper surfaces of a device layer, which helps to reduce resistance. When conductive metal layers are disposed on both the lower and upper surfaces of a device layer, one can be used as a bit line (BL) connection, and the other as a source line (SL) connection. Alternatively, when a conductive metal layer is disposed on one of the lower and upper surfaces of a device layer (while no conductive metal layer is disposed on the other surface), the conductive metal layer can be used as either a BL connection or an SL connection.

[0034] Such a vertical memory device can be manufactured, for example, as follows. Specifically, a first stack of multiple first device layers and multiple first sacrificial layers can be formed on a substrate, such that each first device layer has a first sacrificial layer on at least one side (upper and / or lower). For example, the first device layers and the first sacrificial layers can be alternately arranged, or a first sacrificial layer can be arranged between every two first device layers. The first device layers and the first sacrificial layers can be provided by epitaxial growth. The first sacrificial layer can then be replaced with an isolation layer (in particular, a structure in which a conductive metal layer sandwiches an isolation layer). In addition, in-situ doping can be performed during epitaxial growth to achieve the desired doping polarity and doping concentration. A first processing channel can be formed extending vertically relative to the substrate through the first stack.

[0035] A second stack can be similarly formed on the first stack. To form a single crystal, the uppermost first device layer in the first stack (particularly its top surface and the portion of its sidewalls exposed in the first processing channel) can be used as a seed to grow a seed layer. Although the uppermost first device layer serving as the seed has a cavity at the first processing channel, the portions growing around the cavity can join each other, allowing the seed layer to extend continuously along the first processing channel. On the seed layer, a second stack with multiple second device layers and multiple second sacrificial layers can be formed, such that each second device layer has a second sacrificial layer on at least one side (upper and / or lower). The second stack can have a configuration substantially the same as or similar to that of the first stack.

[0036] A second processing channel can be formed that extends vertically relative to the substrate to pass through the second stack and communicate with the first processing channel. The first and second processing channels can be formed based on the same mask, but there may be no complete misalignment between the photolithography process that forms the first processing channel and the photolithography process that forms the second processing channel, for example, there may be overlay errors, which can result in a bent shape as described above.

[0037] In the first processing channel, the sidewall of the first sacrificial layer can be exposed, thereby allowing it to be replaced with a structure in which a first conductive metal layer sandwiches a first insulating layer (for convenience, this can be referred to as the "first replacement process"). Similarly, in the second processing channel, the sidewall of the second sacrificial layer can be exposed, thereby allowing it to be replaced with a structure in which a second conductive metal layer sandwiches a second insulating layer (for convenience, this can be referred to as the "second replacement process").

[0038] The first replacement process can be performed after the first processing channel is formed (and before the seed layer is grown to close the top of the first processing channel), and the second replacement process can be performed after the second processing channel is formed. Alternatively, the first and second replacement processes can be performed using the same process after the first and second processing channels, which are connected to each other, are formed. In this case, the first and second conductive metal layers can include the same conductive metal layer, and the first and second isolation layers can include the same isolation layer. This provides different process options.

[0039] The first and second replacement processes can be performed, for example, as follows: A support layer can be formed in a portion of the processing channels (e.g., the first processing channel, or the second processing channel, or both the first and second processing channels that are interconnected) to support the stack during the replacement of the (first and / or second) sacrificial layer. The sacrificial layer can be removed via the remaining processing channels, for example, by selective etching. In the space freed up by the removal of the sacrificial layer, a conductive metal layer and an isolation layer can be formed, for example, by deposition followed by etching back.

[0040] In the first processing channel, a first gate stack can be formed (for convenience, this can be referred to as the "first gate stack forming process"). Similarly, in the second processing channel, a second gate stack can be formed (for convenience, this can be referred to as the "second gate stack forming process").

[0041] The first gate stack formation process can be performed after the formation of the first processing channel (and before the seed layer is grown to close the top of the first processing channel), and the second gate stack formation process can be performed after the formation of the second processing channel. Alternatively, the first and second replacement processes can be performed using the same process after the formation of the first and second processing channels that are interconnected. In this case, the first memory function layer in the first gate stack and the second memory function layer in the second gate stack can include the same memory function layer, and the first gate conductor layer in the first gate stack and the second gate conductor layer in the second gate stack can include the same gate conductor layer. This provides different process options.

[0042] This disclosure may be presented in various forms, some of which will be described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation, conductive materials for forming electrodes, interconnect structures, etc.) but also etching selectivity. In the following description, the desired etching selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etching selectivity relative to other layers exposed to the same etching formulation.

[0043] Figures 1 to 16(c) A schematic diagram of some stages in the process of manufacturing a storage device according to an embodiment of the present disclosure is shown.

[0044] like Figure 1 As shown, a substrate 1001 is provided. This substrate 1001 can be of various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, and compound semiconductor substrates such as SiGe substrates. In the following description, for ease of explanation, a bulk Si substrate, such as a Si wafer, will be used as an example.

[0045] On substrate 1001, a memory device, such as NOR or AND type flash memory, can be formed as described below. The memory cell in the memory device can be an n-type device or a p-type device. Here, an n-type memory cell is described as an example, for which a p-type well can be formed in substrate 1001. Therefore, the following description, particularly regarding the doping type, is for the formation of n-type devices. However, this disclosure is not limited thereto.

[0046] On substrate 1001, a sacrificial layer 10031 for defining an isolation layer, a first source / drain layer 10051 for defining a source / drain region, a channel layer 10071 for defining a channel region, and a second source / drain layer 10091 for defining a source / drain region can be formed, for example, by epitaxial growth. The growth temperature can be, for example, from about 600°C to about 700°C. The first source / drain layer 10051, the channel layer 10071, and the second source / drain layer 10091 will then define the active region of the device, which can be referred to as the "device layer", denoted as L1 in the figure.

[0047] The layers grown on the substrate 1001 can be single-crystal semiconductor layers. Because these layers are grown or doped separately, they can have crystal interfaces or doping concentration interfaces with each other.

[0048] The sacrificial layer 10031 can then be replaced with an isolation layer for isolating the device from the substrate, the thickness of which can correspond to the desired thickness of the isolation layer, for example, about 10 nm to 50 nm. Depending on the circuit design, the sacrificial layer 10031 may also be omitted. The first source / drain layer 10051 and the second source / drain layer 10091 can be doped (e.g., in-situ doping during growth) to form source / drain regions, the thickness of which can be, for example, about 20 nm to 50 nm. The channel layer 10071 can define a gate length, the thickness of which can correspond to the desired gate length, for example, about 15 nm to 200 nm.

[0049] These semiconductor layers can include a variety of suitable semiconductor materials, such as elemental semiconductor materials like Si or Ge, compound semiconductor materials like SiGe, etc. Consider the following process of replacing the sacrificial layer 10031 with an isolation layer, where the sacrificial layer 10031 can have etch selectivity relative to the device layer. For example, the sacrificial layer 10031 can include SiGe (the atomic percentage of Ge is, for example, about 15%-30%), and the device layer can include Si. In this example, both the source / drain layer and the channel layer in the device layer include Si, but this disclosure is not limited thereto. For example, etch selectivity can also exist between adjacent layers in the device layer.

[0050] During the growth of the first source / drain layer 10051 and the second source / drain layer 10091, they can be in-situ doped to subsequently form the source / drain regions. For example, for n-type devices, n-type doping can be performed, with a doping concentration of, for example, about 1E19-1E21 cm⁻¹. -3 Additionally, the channel layer 10071 may be undoped or lightly doped through in-situ doping during growth to improve short-channel effects and adjust the device threshold voltage (V). t For example, for n-type devices, p-type doping can be performed, with a doping concentration of approximately 1E17-1E19 cm⁻¹. -3Furthermore, in the vertical direction, the doping concentration in the channel layer 10071 can have a non-uniform distribution to optimize device performance. For example, the concentration can be relatively high in regions close to the drain region (e.g., subsequently connected to the bit line) to reduce short-channel effects, while the concentration can be relatively low in regions close to the source region (e.g., subsequently connected to the source line) to reduce channel resistance or optimize hot carrier injection to facilitate tunneling. This can be achieved by introducing different doses of dopant at different stages of growth.

[0051] Although device layer L1 is described herein as comprising three layers (a first source / drain layer 10051, a channel layer 10071, and a second source / drain layer 10091) formed separately, this disclosure is not limited thereto. For example, device layer L1 may be a single layer, but the source / drain region and the channel region may be defined by introducing different doses of dopant at different stages of growth.

[0052] To increase integration density, multiple device layers can be configured. For example, device layer L2 can be fabricated on device layer L1 via epitaxial growth, with the device layers spaced apart by a sacrificial layer 10032 used to define isolation layers. Although Figure 1 Only two device layers are shown, but this disclosure is not limited thereto. Depending on the circuit design, some device layers may not have isolation layers. Similarly, device layer L2 may have a first source / drain layer 10052, a channel layer 10072, and a second source / drain layer 10092. The corresponding layers in each device layer may have the same or similar thickness and / or material, or they may have different thicknesses and / or materials. Here, for the sake of convenience, it is assumed that each device layer L1 and L2 has the same configuration.

[0053] According to embodiments of this disclosure, for ease of manufacturing, particularly for ease of etching of processing channels or holes, the number of device layers etched together to form processing channels or holes therein can be between about 10 and 200. Figure 1 The diagram schematically illustrates two layers (L1 and L2), such that the total thickness of the first stack S1 (including the corresponding isolation layer) formed by these layers can be, for example, between about 2 μm and 10 μm. The maximum total thickness of the first stack S1 can be determined based on process capabilities, such as the aspect ratio achievable by the etching process used to etch the processing channels or holes, the backfilling capability / uniformity of the deposition process used to deposit material into the voids in the stack (e.g., voids released due to the removal of the sacrificial layer), etc. For example, when the processing channels or holes have a predetermined lateral dimension such as diameter, the total thickness of the first stack S1 (which is substantially equal to the depth of the processing channels or holes) can be controlled such that the aspect ratio of the processing channels or holes (≈ total thickness of the first stack S1 / diameter of the processing channels or holes) is less than, for example, about 40 to 80, thereby facilitating etching.

[0054] A hard mask layer 1011 may be disposed on the first stack S1 to facilitate patterning. For example, the hard mask layer 1011 may include a nitride (e.g., silicon nitride) with a thickness of about 50 nm to 200 nm.

[0055] Therefore, on the one hand, a processing channel is needed to reach the sacrificial layer in order to replace the sacrificial layer with an isolation layer; on the other hand, it is necessary to define the area for forming the gate. According to embodiments of this disclosure, these two can be combined. Specifically, the processing channel can be used to define the gate area.

[0056] For example, such as Figure 2(a) and 2(b) As shown, photoresist 1013 can be formed on the hard mask layer 1011 and patterned by photolithography to have a series of openings that define the locations of processing channels. The openings can be of various suitable shapes, such as circles, rectangles, squares, polygons, etc., and have suitable sizes, such as diameters or side lengths of approximately 20 nm to 500 nm. Here, these openings (particularly in the cell regions) can be arranged in an array, for example, a two-dimensional array along the horizontal and vertical directions in the plane of the paper in FIG. 2(a). This array can then define an array of memory cells. Although the openings are shown in FIG. 2(a) as being formed on the substrate (including the cell regions where memory cells will subsequently be fabricated and the contact regions where contacts will subsequently be fabricated) with substantially uniform size and a generally uniform density, this disclosure is not limited thereto. The size and / or density of the openings can be varied; for example, the density of openings in the contact regions can be less than the density of openings in the cell regions to reduce the resistance in the contact regions.

[0057] like Figure 3 As shown, a photoresist 1013 can be configured as an etching mask to etch layers on a substrate 1001 using anisotropic etching such as reactive ion etching (RIE) to form first processing channels T1. The RIE can be performed in a generally vertical direction (e.g., perpendicular to the substrate surface) and can extend into the substrate 1001. This leaves a series of vertical first processing channels T1 on the substrate 1001. The first processing channels T1 in the cell region also define gate regions. The photoresist 1013 can then be removed.

[0058] Currently, the sidewalls of the sacrificial layer are exposed in the first processing channel T1. Therefore, the sacrificial layer can be replaced with an isolation layer via the exposed sidewalls. Considering the support function for device layers L1 and L2 during replacement, a support layer can be formed.

[0059] For example, such as Figure 4As shown, a support material layer can be formed on substrate 1001 by deposition, for example, chemical vapor deposition (CVD). The support material layer can be formed in a generally conformal manner. Considering etching selectivity, especially relative to the hard mask layer 1011 (nitride in this example) and the subsequently formed isolation layer (oxide in this example), the support material layer can include, for example, SiC. A portion of the support material layer in the first processing channel T1 can be removed, for example, by forming photoresist 1017 and selectively etching, such as RIE, in conjunction with the photoresist 1017, while retaining the support material layer in the remaining first processing channels T1. The remaining support material layer forms support layer 1015. In this way, on the one hand, the sacrificial layer can be replaced by the processing channel in which support layer 1015 is not formed, and on the other hand, device layers L1 and L2 can be supported by support layer 1015 in other processing channels. Afterwards, photoresist 1017 can be removed.

[0060] The arrangement of processing channels with and without support layers 1015 can be achieved through the patterning of photoresist 1017, and for the sake of process consistency and uniformity, they can be distributed approximately evenly. Figure 4 As shown, the processing channels in which the support layer 1015 is formed can be arranged alternately with the processing channels in which the support layer 1015 is not formed.

[0061] Then, as Figure 5 As shown, the sacrificial layers 10031 and 10032 can be removed by selective etching via the first processing channel T1. The presence of the support layer 1015 prevents the device layers L1 and L2 from collapsing.

[0062] In the space freed up by the removal of sacrificial layers 10031 and 10032, a conductive metal layer 1019 and an isolation layer 1021 can be formed. For example, a conductive metal material such as tungsten (W) can be deposited in a generally conformal manner, followed by the deposition of a dielectric material such as an oxide (e.g., silicon oxide) to fill the freed-up space and any remaining voids in the processing channels. A conductive diffusion barrier layer can also be formed before the deposition of the conductive metal material. The deposited dielectric and conductive metal materials (and the diffusion barrier layer, if present) can be etched back, such as by a vertical RIE, to remove them from the processing channels (the freed-up processing channels will be used for gate stacking), leaving the conductive metal layer 1019 and the isolation layer 1021 in the space freed up by the removal of sacrificial layers 10031 and 10032.

[0063] The conductive metal layer 1019 can extend on the upper and lower surfaces of each device layer, except for the upper surface of the uppermost device layer (in this example, device layer L2), which can then be used as a growth seed for other layers on the first stack S1. The portions of the conductive metal layer 1019 extending on the upper and lower surfaces of each device layer can then be used as BL / SL connections for memory cells in the respective device layers. Additionally, due to the presence of the support layer 1015, the conductive metal layer 1019 has a portion extending along the sidewall of the isolation layer 1021 adjacent to the support layer 1015 (hereinafter referred to as the "sidewall portion" for convenience), which results in electrical communication between the BL / SL connections of different device layers. This may be undesirable.

[0064] Therefore, such as Figure 6 As shown, the support layer 1015 can be removed by selective etching. A masking layer 1023, such as photoresist, can be formed in the processing channels where the support layer 1015 was not previously formed, exposing the processing channels where the support layer 1015 was previously formed. Thus, the sidewall portions of the conductive metal layer 1019 are exposed in these processing channels. The sidewall portions of the conductive metal layer 1019 can be selectively etched through the unmasked processing channels. Therefore, the conductive metal layer 1019 can remain on the upper and lower surfaces of each device layer to serve as the BL / SL connection for the memory cells in the corresponding device layer, and the BL / SL connections of different device layers can be electrically isolated from each other. According to other embodiments, this conductive metal layer may not be formed, and the sacrificial layer may be directly replaced with an isolation layer. The purpose of the conductive metal layer is mainly to further reduce the connection resistance, and its formation does not hinder the electrical operation of the device.

[0065] After that, the masking layer 1023 can be removed.

[0066] In the first processing channel T1, particularly the first processing channel T1 of the cell region, a gate stack can be formed. Here, to form a storage device, the storage function can be achieved through the gate stack. For example, the gate stack can include storage structures such as charge-trapping materials or ferroelectric materials.

[0067] like Figure 7As shown, a first storage functional layer 1025 and a first gate conductor layer 1027 can be formed sequentially, for example, by deposition. The first storage functional layer 1025 can be formed in a generally conformal manner, and the first gate conductor layer 1027 can fill the gaps remaining in the first processing channel T1 after the formation of the first storage functional layer 1025. The formed first gate conductor layer 1027 and first storage functional layer 1025 can be planarized, such as by chemical mechanical polishing (CMP, for example, stopping at the hard mask layer 1011), so that the first gate conductor layer 1027 and the first storage functional layer 1025 can remain in the first processing channel T1, forming a first gate stack. Here, considering the crystal quality in subsequent growth processes, the planarized first gate stack can be further etched back so that its top surface is, for example, between the top and bottom surfaces of the second source / drain layer 10091 of the uppermost device layer (in this example, device layer L2). This allows the first gate stack to overlap with the entire vertical height of the channel layer 10072 to effectively control the channel region formed in the channel layer 10072, and exposes a portion of the sidewalls of the second source / drain layer 10091 for subsequent use as growth seeds.

[0068] The first storage functional layer 1025 can be based on dielectric charge trapping, ferroelectric material effects, or engineered charge storage (SONOS). For example, the first storage functional layer 1025 may include a dielectric tunneling layer (e.g., an oxide with a thickness of about 1 nm to 5 nm, which can be formed by oxidation or ALD) - a band shift layer (e.g., a nitride with a thickness of about 2 nm to 10 nm, which can be formed by CVD or ALD) - an isolation layer (e.g., an oxide with a thickness of about 2 nm to 6 nm, which can be formed by oxidation, CVD, or ALD). This three-layer structure can result in a band structure that traps electrons or holes. Alternatively, the first storage functional layer 1025 may include a ferroelectric material layer, such as HfZrO2 with a thickness of about 2 nm to 20 nm.

[0069] The first gate conductor layer 1027 may include, for example, (doped, such as p-type doped in the case of an n-type device) polysilicon or a metal gate material.

[0070] like Figure 7 As shown, a first gate stack (1025 / 1027) with a storage function layer is surrounded by device layers (in this example, device layers L1 and L2). The first gate stack cooperates with the device layers to define memory cells, such as... Figure 7The dotted circle in the diagram illustrates this. The channel region can connect the source / drain regions on opposite sides, and the channel region can be controlled by the first gate stack. One of the source / drain regions at the top and bottom of a single memory cell serves as the source region and can be electrically connected to the source line; the other serves as the drain region and can be electrically connected to the bit line. In the case of forming a NOR-type memory device, for every two vertically adjacent memory cells, the source / drain region at the top of the lower memory cell and the source / drain region at the bottom of the upper memory cell can serve as source regions, thus allowing them to share the same source line connection.

[0071] The first gate stack extends in a columnar shape in the vertical direction, overlapping with multiple device layers, thereby defining multiple memory cells stacked on top of each other in the vertical direction. Memory cells associated with a single gate stack pillar can form a memory cell string. Corresponding to the layout of the gate stack pillars (corresponding to the layout of the first processing channel T1 described above, such as a two-dimensional array), multiple such memory cell strings are arranged on the substrate to form a three-dimensional (3D) array of memory cells.

[0072] This completes the fabrication of the memory cell in the first stack S1. According to embodiments of this disclosure, one or more such stacks can be fabricated similarly to increase the number of stacked memory cells and thus increase the capacity of the storage device.

[0073] As shown in Figure 8(a), a protective sidewall 1029 can be formed on the top surface of the first gate stack within each first processing channel T1 using a spacer forming process. For example, the protective sidewall 1029 can be formed by depositing a dielectric layer in a generally conformal manner and then anisotropically etching the deposited dielectric, such as a vertical RIE, to remove the lateral extensions of the deposited dielectric, leaving its vertical extensions. The protective sidewall 1029 thus formed extends annularly along the sidewall of the first processing channel T1, allowing for reliable electrical isolation between the subsequently formed second gate conductor layer and the first stack S1 (particularly the second source / drain layer 10091 exposed as described above to serve as part of the sidewall for growth seeds). Here, considering the etching selectivity with the subsequently formed isolation layer (e.g., see 1031 in Figures 8(a) or 8(b)), the protective sidewall 1029 may include a nitride.

[0074] Furthermore, the top surface of the first gate conductor layer 1027 remains (partially) exposed in each of the first processing channels T1. To avoid undesirable electrical connections that may exist between the subsequently formed seed layer and the first gate conductor layer 1027, an isolation layer 1031 can be formed to shield the top surface of the first gate conductor layer 1027. For example, the isolation layer 1031 can be formed by depositing and subsequently planarizing an oxide such as CMP.

[0075] According to other embodiments, instead of forming a separate protective sidewall 1029, as shown in FIG8(b), in the above combination Figure 7 During the described etchback process of the first gate stack, the first gate conductor layer 1027 can be selectively etched back without etching back the first storage function layer 1025. Thus, the portion of the first storage function layer 1025 protruding above the top surface of the first gate conductor layer 1027 can similarly serve as a protective sidewall. Similarly, an isolation layer 1031 can be formed.

[0076] Next, the second source / drain layer 10092 of the uppermost device layer (L2 in this example) in the first stack S1 can be used as a seed to grow a seed layer that serves as the basis for the growth of other stacks.

[0077] Therefore, such as Figure 9 As shown, a planarization process such as CMP can be used to expose the upper surface of the second source / drain layer 10092 of the uppermost device layer (L2 in this example) in the first stack S1, thereby using the upper surface as a growth seed. Additionally, to improve the quality of the seed layer grown on this growth seed, the planarized protective sidewalls 1029 (and optionally, the isolation layer 1031) can be etched back to a certain extent to expose a portion of the sidewalls of the second source / drain layer 10092 of the uppermost device layer (L2 in this example) in the first stack S1.

[0078] Then, as Figure 10 As shown, the exposed portion (e.g., the upper surface and part of the sidewalls) of the second source / drain layer 10092 of the uppermost device layer (L2 in this example) in the first stack S1 can be used as a growth seed to form a seed layer 1033 through epitaxial growth. Semiconductor material grown from the periphery of each first processing channel T1 (e.g., the sidewalls of the second source / drain layer 10092 exposed in each first processing channel T1) can grow into the first processing channel T1 and can be bonded to each other, so that the seed layer 1033 can be formed as a semiconductor layer, particularly a single-crystal semiconductor layer, that extends continuously on the first stack S1. If necessary, the grown seed layer 1033 can also be planarized so that its top surface extends substantially flat. Here, a selective epitaxial growth process can be used to reduce defects in the seed layer 1033, especially in the region where the first processing channel T1 is located, because the seed layer 1033 grows from the second source / drain layer 10092 of a single crystal (which can result in a single crystal) rather than from the protective sidewall 1029 and the isolation layer 1031 (which would result in a polycrystalline or amorphous crystal).

[0079] Here, the seed layer 1033 is in physical contact with the second source / drain layer 10092 of the uppermost device layer (L2 in this example) in the first stack S1. Therefore, in addition to serving as the growth base for the upper stack, it can also, together with the second source / drain layer 10092, define the source / drain regions of memory cells in the device layer L2 (and thus can also be considered as part of the device layer L2, particularly the second source / drain layer 10092 therein). Thus, the seed layer 1033 can comprise the same material as the device layer L2 (particularly the second source / drain layer 10092 therein) (Si in this example), and can comprise substantially the same doping type and concentration (e.g., by in-situ doping during growth).

[0080] like Figure 11 As shown above, in combination Figure 1 The formation of the first stack S1 on the substrate 1001 can be followed by the formation of a second stack S2 on the seed layer 1033 in a substantially similar manner. The second stack S2 may include device layers L3 and L4 (the specific number of device layers is not limited thereto). Device layer L3 may include a first source / drain layer 10053, a channel layer 10073, and a second source / drain layer 10093; device layer L4 may include a first source / drain layer 10054, a channel layer 10074, and a second source / drain layer 10094. Similarly, sacrificial layers 10033 and 10034 are also provided. When the second stack S2 is the uppermost stack in the memory device, a sacrificial layer 10035 can also be provided on the second stack S2 so that, as described above, by replacing the sacrificial layer 10035 with a conductive metal layer (and an isolation layer), a BL / SL connection can be provided for the second source / drain layer 10094 of the uppermost device layer (device layer L4 in this example) of the uppermost stack (the second stack S2). Similarly, for ease of patterning, a hard mask layer 1035 can be formed on the second stack S2. For information on the device layer, sacrificial layer, and hard mask layer 1035 in the second stack S2, please refer to the above combination. Figure 1 The explanation is as follows. For example, the second stack S2 can have the same configuration as the first stack S1 (except that a sacrificial layer 10035 is added when it is the topmost stack). Similarly, to facilitate the etching of channels or holes, the total thickness of the second stack S2 can be, for example, between about 2 μm and 10 μm.

[0081] Although only two stacks S1 and S2 are shown herein, this disclosure is not limited thereto and may include more stacks to increase the storage capacity of the storage device.

[0082] like Figure 12 As shown, for the second stack S2, it can be combined as described above. Figures 2(a) to 3As described above, a second processing channel T2 is formed therein by anisotropic etching, such as RIE. During etching, the sidewall 1029 and / or the isolation layer 1031 can be used as a stop layer. The mask used to form the second processing channel T2 can be the same as the mask used to form the first processing channel T1, but due to manufacturing tolerances (e.g., overlay error), the second processing channel T2 obtained through the same mask may be offset relative to the first processing channel T1, as shown by the dashed circle in the figure. Of course, this offset is relatively small relative to the size of the first processing channels T1 and T2, so that the second processing channel T2 can still maintain communication with the first processing channel T1 (where the gate stack and the protective sidewall 1029 and isolation layer 1031 are currently formed). In addition, as described above... Figures 4 to 6 As shown, sacrificial layers 10033, 10034 and 10035 can be removed via the second processing channel T2, and a conductive metal layer 1037 and an isolation layer 1039 can be formed in the space released due to their removal.

[0083] like Figure 12 As shown by the dashed circle, due to overlay offset, the second source / drain layer 10092 of the uppermost device layer (L2 in this example) in the first stack S1 may be partially exposed at the bottom of the second processing channel T2. To avoid any undesirable electrical connection that may exist between the exposed portion of the second source / drain layer 10092 and the second gate conductor layer subsequently formed in the second processing channel T2, as... Figure 13 As shown, the exposed portion of the second source / drain layer 10092 can be etched via the second processing channel T2 using selective etching such as RIE to form an isolation trench. The etching depth D is, for example, approximately 10 nm to 30 nm. This depth can be greater than the overlay offset so that the isolation layer subsequently formed in the isolation trench can reliably isolate the second gate conductor layer formed in the second processing channel T2 from the second source / drain layer 10092; conversely, it can be less than the thickness of the second source / drain layer 10092 to prevent the isolation trench from extending into the channel layer 10072. To more accurately control the etching depth D, atomic layer etching (ALE) can be used. The isolation layer 1041 can be formed in the isolation trench by depositing and then etching back a dielectric. The deposition thickness of the dielectric can be greater than the etching depth D to fill the isolation trench. To more accurately control the deposition thickness, atomic layer deposition (ALD) can be used. In addition, considering etching selectivity (especially relative to hard mask layer 1035, protective sidewall 1029 and isolation layer 1031), isolation layer 1041 may include, for example, SiC.

[0084] Subsequently, a gate stack can be formed similarly in the second processing channel T2.

[0085] As described above, one processing channel can correspond to one memory cell string. Each first processing channel T1 in the first stack S1 and the corresponding second processing channel T2 in the second stack S2 are interconnected (although offset) and can correspond to the same memory cell string. More specifically, the gate stacks formed in each first processing channel T1 in the first stack S1 and the corresponding second processing channel T2 in the second stack S2 can be electrically connected to each other and correspond to the same word line WL. To achieve the electrical connection between the gate stacks in the corresponding processing channels, as follows... Figure 14 As shown, a second storage functional layer 1043 extending vertically along the sidewall of the second processing channel T2 can be formed in the second processing channel T2, instead of the first storage functional layer 1025 extending along the bottom of the first processing channel T1 as in the first processing channel T1. This second storage functional layer 1043 can be formed using a sidewall process. Considering the consistency of performance between storage cells, the second storage functional layer 1043 can have the same configuration as the first storage functional layer 1025 (e.g., substantially the same stack structure, where each layer has substantially the same material composition and thickness). Furthermore, via the second processing channel T2 (where the second storage functional layer 1043 is formed on the sidewall), the isolation layer 1031 can be selectively etched, such as in a vertical RIE, to form an opening therein, thereby exposing the underlying first gate stack (particularly the first gate conductor layer 1027), allowing communication between the second processing channel T2 (particularly the second gate conductor layer subsequently formed therein) and the first processing channel T1 (particularly the first gate conductor layer 1027 already formed therein). Since the isolation layer 1031 in each first processing channel T1 is surrounded by annular protective sidewalls 1029 (or, the protruding portion of the first storage function layer 1025, as shown in FIG8(b)), the opening in the isolation layer 1031 will not expose the sidewalls of the first processing channel T1 (especially the sidewalls of the semiconductor layer in the first stack S1) to the outside and contact the subsequently formed second gate conductor layer.

[0086] Then, as shown in FIG15(a), the second gate conductor layer 1045 can be formed by depositing and then planarizing the conductive material. Considering the consistency of performance between memory cells, the second gate conductor layer 1045 can have the same configuration as the first gate conductor layer 1027 (e.g., substantially the same stack structure, in which each layer has substantially the same material composition and thickness).

[0087] Therefore, the second gate stack (1043 / 1045) with the storage function layer is surrounded by the device layers (in this example, device layers L3 and L4). The second gate stack cooperates with the device layers to define the memory cell.

[0088] The second gate stack is adjacent to the first gate stack (in particular, the second gate conductor layer 1045 and the first gate conductor layer 1027 are in physical contact with each other), and can thus be regarded as a generally vertically extending "gate stack". This gate stack overlaps with the device layers (e.g., L1, L2, L3, L4) in the first stack S1 and the second stack S2 to form a corresponding memory cell string.

[0089] The vertically extending grid stack has a bent-shaped surface at the junction of the first stack S1 and the second stack S2.

[0090] Figure 15(b) is a schematic enlarged view of portion P in Figure 15(a). Note that Figure 15(b) shows machining channels T1 and T2 with sloping sidewalls (e.g., due to the limited capabilities of the etching process). In other illustrations, such sidewall sloping may not be shown for convenience only.

[0091] like Figure 15(a) and 15(b) As shown, the first gate conductor layer 1027 and the second gate conductor layer 1045, which are in physical contact with each other, can together serve as the gate conductor layers of the gate stack. The gate conductor layer may include a first portion I extending in the first stack S1, a second portion II above the first portion I, and a connecting portion III between the two portions. The connecting portion III may have a reduced width relative to the first portion I (particularly its top) and the second portion II (particularly its top). Due to the overlay error described above, the straight line containing the vertical center line of the first portion I and the straight line containing the vertical center line of the second portion II (see the dashed line in FIG. 15(a)) may not coincide with each other, for example, having a lateral distance d between them limited by the overlay accuracy of the photolithography system, d being, for example, greater than about 2 nm.

[0092] Note that Figure 15(b) only shows a local area. The first part I of the gate conductor layer can extend downward from the area shown in Figure 15(b), and the second part II of the gate conductor layer can extend upward from the area shown in Figure 15(b), as shown in Figure 15(a).

[0093] The first storage layer 1025 extends on the sidewall (and bottom, since in this example, the first portion I is the bottommost part of the gate stack) of the first portion I of the gate conductor layer, and the second storage layer 1043 may extend on the sidewall of the second portion II of the gate conductor layer. The first storage layer 1025 and the second storage layer 1043 are formed as described above, and may be disconnected or discontinuous from each other. This discontinuity means that the storage layer may not be present on the sidewall of the connection portion III of the gate conductor layer. As described above, the protective sidewall 1029 may surround the connection portion III to prevent unwanted electrical connections between the gate conductor layer (especially the connection portion III) and the device layer.

[0094] As shown in the dashed box Q in the figure, the top of the first portion I of the gate conductor layer may have a portion that overlaps vertically with the uppermost device layer in the first stack S1 (in this example, L2, particularly the seed layer 1033 therein, which, as described above, can be considered as part of the device layer L2, particularly the second source / drain layer 10092 therein). The size of this overlap depends on the offset d of the second processing channel T2 relative to the first processing channel T1 (in the case of a small offset, the overlap may not exist). As described above, an isolation layer 1031 may be located between the top of the first portion I of the gate conductor layer and the uppermost device layer in the first stack S1 to prevent unwanted electrical connections between the gate conductor layer (particularly the first portion I) and the device layer. For example, the sidewall of the seed layer 1033 facing the gate stack may include a portion extending along the sidewall of the first processing channel T1 and a portion extending along the sidewall of the second processing channel T2, both of which form downwardly protruding portions as shown in M ​​due to the offset of the second processing channel T2 relative to the first processing channel T1. The isolation layer 1031 may be formed below this protruding portion N.

[0095] As shown in the dashed box R in the figure, the bottom of the second portion II of the gate conductor layer may have a portion that overlaps vertically with the uppermost device layer in the first stack S1 (in this example, L2, particularly the second source / drain layer 10092 therein). The size of this overlap depends on the offset d of the second processing channel T2 relative to the first processing channel T1 (in the case of a small offset, this overlap may not exist). As described above, an isolation layer 1041 may be located between the bottom of the second portion II of the gate conductor layer and the uppermost device layer in the first stack S1 to prevent unwanted electrical connections between the gate conductor layer (particularly the second portion II) and the device layer. For example, the sidewalls of the second source / drain layer 10092 facing the gate stack may include portions extending along the sidewalls of the first processing channel T1 and along the sidewalls of the second processing channel T2, which form a stepped portion as shown in N due to the offset of the second processing channel T2 relative to the first processing channel T1. The isolation layer 1041 may be formed on this stepped portion N.

[0096] exist Figure 15(a) and 15(b) In the example shown, when viewed from above, the region defined by the top of the first portion I of the gate conductor layer and the region defined by the bottom of the second portion II of the gate conductor layer can partially overlap each other. However, different configurations can exist depending on the relative dimensions between the first processing channel I (particularly its top) and the second processing channel II (particularly its bottom) and the offset d.

[0097] For example, as shown in Figure 15(c), if the top dimension of the first processing channel I is larger than the bottom dimension of the second processing channel II, when viewed from above, the area defined by the bottom of the second portion II of the gate conductor layer can be within the area defined by the top of the first portion I of the gate conductor layer (as mentioned above, due to the offset d, the lines containing their respective centerlines may not coincide). In this case, in the above combination Figure 12 In the described process for forming the second processing channel T2, the bottom of the second processing channel T2 can completely rest on the protective sidewall 1029 and / or isolation layer 1031 formed in the first processing channel T, and the device layer in the first stack S1 may not be exposed at the bottom of the second processing channel T2. Therefore, in the above combination... Figure 13 In the described process for forming the isolation layer 1041, the isolation layer 1041 is not actually formed. Furthermore, in this embodiment, the second portion II can extend continuously to the top of the first portion I, and the connecting portion III, whose width abruptly changes relative to the first portion I and the second portion II as described above, may not exist.

[0098] For example, as shown in Figure 15(d), if the top dimension of the first processing channel I is larger than the bottom dimension of the second processing channel II, when viewed from above, the area defined by the top of the first portion I of the gate conductor layer can be within the area defined by the bottom of the second portion II of the gate conductor layer (as mentioned above, due to the offset d, the lines containing their respective centerlines may not coincide). In this case, in the above combination... Figure 14 In the process described for opening in the isolation layer 1031, the isolation layer 1031 can be completely removed. Thus, the connecting portion III can be surrounded by the protective sidewalls 1029, and the isolation layer 1031 may not exist between them.

[0099] This completes the fabrication of the storage cell (in the cell area). Then, various electrical contacts can be fabricated (in the contact area) to achieve the required electrical connections.

[0100] To achieve electrical connections to various device layers, a stepped structure can be formed in the contact area. Various methods exist in the art for forming such stepped structures, which will not be elaborated upon here. For example... Figure 16(a) , 16(b) As shown in 16(c), the formed stepped structure causes the ends of each source / drain region (the conductive metal layer on the surface is also patterned in the same way as the corresponding source / drain region) and optional trench region that require electrical connection in each device layer to protrude relatively from the region above, so as to define the contact pads to the contact portion of that region.

[0101] After forming a stepped structure in the contact region, an interlayer dielectric layer 1047 can be formed by depositing, for example, oxides and planarizing, such as CMP. Here, since both are oxides, the previous isolation layers 1021 and 1039 are shown as integral with the interlayer dielectric layer 1047. Then, as shown, contacts 1049 and 1051 can be formed in the interlayer dielectric layer 1047. Specifically, contacts 1049 are formed in the cell region and electrically connected to the second gate conductor layer 1045 in the gate stack (and thus electrically connected to the first gate conductor layer 1027); contacts 1051 are formed in the contact region and electrically connected to the respective source / drain regions and optionally the channel region. The contacts 1051 in the contact region can avoid residual gate stacking in the contact region. These contacts can be formed by etching holes in the interlayer dielectric layer 1047 and filling them with a conductive material such as a metal.

[0102] Here, contact 1049 can be electrically connected to the word line. A gate control signal can be applied to the gate conductor layers 1027 and 1045 via the word line and contact 1049. Contact 1051 can be electrically connected to the source line or bit line. More specifically, for the same memory cell, one source / drain region can be electrically connected to the bit line, while the other source / drain region can be electrically connected to the source line. Due to the presence of conductive metal layers 1019 and 1037, the resistance when applying electrical signals from the bit line and source line to the corresponding source / drain region can be reduced. A contact to the channel region is also formed here. This contact can be called a body contact and can receive body bias to adjust the device threshold voltage.

[0103] Figure 17 An equivalent circuit diagram of an AND-type memory device according to an embodiment of the present disclosure is shown schematically.

[0104] exist Figure 17 The example illustrates eight memory cell layers stacked on top of each other (the four device layers L1 to L4 in the aforementioned embodiment each constitute a corresponding memory cell layer) and three word lines WL1, WL2, and WL3 passing through these eight memory cell layers. As described above, these memory cell layers can be formed in multiple stages (e.g., a portion of the memory cell layers, such as the lower four memory cell layers, is formed through a first stack S1, a portion of the memory cell layers, such as the upper four memory cell layers, is formed through a second stack S2, and so on), thereby reducing the difficulty of etching the processing channels. Each word line WL1, WL2, and WL3 can correspond to a vertically extending (possibly with bends) gate stack, including, for example, a first gate conductor layer and a second gate conductor layer.

[0105] Memory cells in each memory cell layer can be connected in parallel between corresponding bit lines / source lines. The figure schematically illustrates the bit lines / source lines BL / SL1a, BL / SL1b, BL / SL2a, BL / SL2b, BL / SL3a, BL / SL3b, BL / SL4a, BL / SL4b, BL / SL5a, BL / SL5b, BL / SL6a, BL / SL6b, BL / SL7a, BL / SL7b, BL / SL8a, and BL / SL8b for these eight memory cell layers. For each pair of bit lines / source lines BL / SLia and BL / SLib (where 1 ≤ i ≤ 8), one (e.g., BL / SLia) can serve as a bit line, and the other (e.g., BL / SLib) can serve as a source line. It should be noted that the number of memory cell layers, and therefore the number of bit lines / source lines and word lines, is not limited to this. A memory cell MC is located at the intersection of a bit line and a word line. Additionally, Figure 17 The optional volume connections to each memory cell are also schematically shown in dashed lines.

[0106] For illustrative purposes only, a two-dimensional array of storage cells MC is shown here. Multiple such two-dimensional arrays can be arranged in directions intersecting with this two-dimensional array (e.g., the direction perpendicular to the plane of the paper in the figure) to obtain a three-dimensional array.

[0107] Figure 18 An equivalent circuit diagram of a NOR-type memory device according to an embodiment of the present disclosure is shown schematically.

[0108] exist Figure 18 The example schematically shows three word lines WL1, WL2, WL3 and eight bit lines BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8. However, the specific number of bit lines and word lines is not limited to this. A memory cell MC is located at the intersection of the bit lines and word lines. Figure 18 The diagram also shows four source lines SL1, SL2, SL3, and SL4. As shown, vertically, adjacent memory cells in any two layers can share the same source line connection. Furthermore, the source lines can be interconnected, allowing each memory cell (MC) to be connected to a common source line. Figure 18 The optional body connections to each memory cell are also schematically shown in dashed lines. The body connection of each memory cell can be electrically connected to the source line connection of that memory cell.

[0109] Figure 18 The extension direction of the middle bit lines WL1 to WL3 can correspond to the extension direction of the gate stack, that is, the vertical direction relative to the substrate in the aforementioned embodiment. In this direction, adjacent bit lines are isolated from each other.

[0110] Here, two vertically adjacent memory cells are configured as source / drain regions located between them, electrically connected to the source line. This reduces the number of wires required.

[0111] In the above embodiments, a corresponding gate stack is formed for each layer. However, this disclosure is not limited thereto.

[0112] Figures 19 to 23 A schematic diagram of a portion of the process for manufacturing a storage device according to another embodiment of the present disclosure is shown.

[0113] like Figure 19 As shown, it can be combined as described above. Figures 1 to 6 A first stack S1 is formed on the substrate 1001, and a first processing channel T1 is formed in the first stack S1. Through the first processing channel T1, the sacrificial layer in the first stack S1 can be replaced with a conductive metal layer 1019 and an isolation layer 1021.

[0114] Unlike the above embodiment where a first gate stack is formed in the first processing channel T1 and then the second processing channel T2 is formed, in this embodiment, after both the first processing channel T1 and the second processing channel T2 are formed, a gate stack is formed together in the processing channels T1 and T2 that are connected to each other.

[0115] For example, a shielding layer 1053 can be formed on the sidewall of the first processing channel T1 using a sidewall forming process. The shielding layer 1053 can shield the sidewalls of each semiconductor layer in the first stack S1 exposed in the first processing channel T1 (except for the upper sidewall of the second source / drain layer in the uppermost device layer of the first stack S1, to improve crystal growth quality, as described above) to prevent growth on these sidewalls during subsequent seed layer growth processes. Considering etching selectivity in subsequent processes, the shielding layer 1053 can include, for example, SiC, with a thickness of, for example, about 10 nm to 30 nm.

[0116] like Figure 20 As shown, the hard mask layer 1011 can be removed by selective etching, and then it can be combined as described above. Figure 10The seed layer 1033' is grown. Similarly, the seed layer 1033' can be formed as a continuously extending, substantially flat single-crystal semiconductor layer. Here, although growth may occur at the bottom of the first processing channel T1, the amount of growth source material entering the bottom of the first processing channel T1 is relatively small due to the relatively large aspect ratio of the first processing channel T1, resulting in a lower growth rate. Furthermore, even if a small amount of material such as Si is grown in the seed layer 1033' at the bottom of the first processing channel T1, the potential impact of this growth can be avoided by increasing its depth into the substrate 1001 during the previous etching of the first processing channel T1. That is, the depth of the first processing channel T1 can be set taking this process margin into account.

[0117] After that, as Figure 21 As shown, it can be combined as described above. Figure 11 and 12 A second stack S2 is formed on the seed layer 1033', and a second processing channel is formed in the second stack S2. As described above, the second processing channel can communicate with the first processing channel (although there is an offset), and is therefore integrally shown as processing channel T. Through processing channel T, the sacrificial layer in the second stack S2 can be replaced with a conductive metal layer 1037 and an isolation layer 1039.

[0118] A gate stack can be formed within a processing channel T that continuously passes through the first stack S1 and the second stack S2. For example, as... Figure 22 As shown, the masking layer 1053 can be removed by selective etching. Then, as... Figure 23 As shown, a storage functional layer 1025′ and a gate conductor layer 1027′ can be formed within the processing channel T. For details regarding the materials and formation of the storage functional layer 1025′ and the gate conductor layer 1027′, please refer to the above description of the first storage functional layer 1025 and the first gate conductor layer 1027. In this example, the storage functional layer 1025′ extends along the sidewalls and bottom of the processing channel T that runs through the first stack S1 and the second stack S2, and the gate conductor layer 1027′ fills its inner space. Additionally, gaps may exist in the lower portion of the gate conductor layer 1027′, particularly in the portion within the first stack S1, because the deposited material needs to pass through a narrowed channel between the first stack S1 and the second stack S2, which easily leads to gaps.

[0119] Similarly, the gate conductor layer 1027' may include a first portion I, a second portion II above the first portion I, and a connecting portion III between the two portions. The connecting portion III may have a reduced width relative to the first portion I (particularly its top) and the second portion II (particularly its top). In this example, the first portion I, the second portion II, and the connecting portion III are integral with each other. As described above, a gap may be present in the first portion I, which may extend approximately along the vertical centerline of the first portion I.

[0120] Unlike the embodiments described above, the storage function layer 1025' can extend continuously on the surfaces of the first part I, the second part II, and the connecting part III. Therefore, in this embodiment, it is not necessary to separately form the protective sidewall 1029 and the isolation layers 1031 and 1041 as described in the embodiments above.

[0121] This embodiment describes an example of forming a gate stack together for two adjacent layers. However, this disclosure is not limited thereto. For example, depending on the fill capability of the deposition process, a gate stack can be formed together for more adjacent layers.

[0122] According to the above embodiments, the following process options are provided: for a single stack, the gate stack is formed separately; for several (two or more) adjacent stacks, the gate stack is formed together. For memory devices comprising multiple stacks, various combinations of process options can be freely selected. For example, for some of the stacks, the gate stacks can be formed separately for each of them; for other stacks, several adjacent stacks can be formed together to form the gate stack.

[0123] In the above embodiments, a corresponding conductive metal layer is formed for each stack, and then a corresponding gate stack is formed, either alone or together with adjacent stacks. However, this disclosure is not limited thereto.

[0124] Figures 24 to 26 A schematic diagram of a portion of the process for manufacturing a storage device according to another embodiment of the present disclosure is shown.

[0125] like Figure 24 As shown, it can be combined as described above. Figures 1 to 3 The first stack S1 is formed on the substrate 1001, and a first processing channel T1 is formed in the first stack S1.

[0126] Unlike the embodiments described above where the sacrificial layer in the first stack S1 is replaced with the conductive metal layer 1019 and the isolation layer 1021 via the first processing channel T1, in this embodiment, the sacrificial layer can be retained while combining as described above. Figure 19 The shielding layer 1053 is formed.

[0127] Then, it can be combined as described above. Figure 20 and 21 The seed layer 1033' is grown, a second stack S2 is formed on the seed layer 1033', and a second processing channel (shown together with the first processing channel as processing channel T) is formed in the second stack S2.

[0128] like Figure 26 As shown, the masking layer 1053 can be removed by selective etching. Then, via processing channel T, the sacrificial layer in the first stack S1 and the second stack S2 can be replaced with the conductive metal layer 1019′ and the isolation layer 1021′. For the formation and materials of the conductive metal layer 1019′ and the isolation layer 1021′, please refer to the above description of the conductive metal layer 1019 and the isolation layer 1021. Afterwards, it can be combined as described above... Figure 23 The gate stack is formed.

[0129] Therefore, more process options can be provided. For example, for multiple stacks of a memory device, for some of the stacks, the corresponding conductive metal layer and the corresponding gate stack can be formed separately; for other stacks, several adjacent stacks can be used together to form the corresponding gate stack, and the conductive metal layer of each of these several adjacent stacks can be formed separately or together.

[0130] In the above embodiments, conductive metal layers are formed on both the upper and lower surfaces of each device layer as bit line / source line connections to reduce resistance. However, embodiments according to this disclosure are not limited to this. For example, conductive metal layers may be formed only on the upper or lower surface.

[0131] Figures 27 to 30 A schematic diagram of a portion of the process for manufacturing a storage device according to another embodiment of the present disclosure is shown.

[0132] like Figure 27 As shown, it can be combined as described above. Figure 1 The first stack S1 is formed on substrate 1001. Unlike the embodiments described above, the sacrificial layer may include a first sacrificial layer 10031 and a second sacrificial layer 20032 that have etch selectivity relative to each other, such that one of the first sacrificial layer and the second sacrificial layer is formed on the upper surface of each device layer L1, L2, while the other of the first sacrificial layer and the second sacrificial layer is formed on the lower surface (similar to the embodiments described above, no sacrificial layer is formed on the upper surface of the uppermost device layer L2 in the first stack S1, this is to account for the subsequent formation of a seed layer on its upper surface). For example, the first sacrificial layer and the second sacrificial layer may include SiGe with different Ge atomic percentages, or one of the first sacrificial layer and the second sacrificial layer may include SiGe and the other may include SiC.

[0133] Next, as Figure 28 As shown above in conjunction with Figures 2 to 4, a first processing channel T1 can be formed in the first stack S1, and a support layer 1015 can be formed in a portion of the first processing channel T1.

[0134] like Figure 29 As shown, the second sacrificial layer 20032 can be removed by selective etching (especially relative to the first sacrificial layer 10031), and an isolation layer 1021″ can be formed in the space released by the removal of the second sacrificial layer 20032 by depositing and then etching back a dielectric (e.g., an oxide).

[0135] Then, as Figure 30 As shown, the first sacrificial layer 10031 can be removed by selective etching, and the space released due to the removal of the first sacrificial layer 10031 can be combined as described above. Figure 5 As described above, a conductive metal layer 1019 and an isolation layer 1021 are formed. Thus, for each device layer L1, L2, the conductive metal layer 1021 may be formed only on its upper or lower surface (the conductive metal layer for device layer L2 will be formed on the upper surface of the seed layer that is subsequently formed), and an isolation layer 1021 or 1021″ may be formed on the other surface without a conductive metal layer.

[0136] Subsequent processes can be carried out according to the above embodiments, such as removing the support layer, etching the sidewall portion of the conductive metal layer 1021, and forming a gate stack in the processing channel.

[0137] According to another embodiment, only one of the first sacrificial layer and the second sacrificial layer can be removed to form a conductive metal layer (with an isolation layer sandwiched in between), while the other is retained. For example, one of the first sacrificial layer and the second sacrificial layer may include SiGe, while the other may include Si or a Si layer with a pnp doping distribution or an npn doping distribution along the vertical direction (such a Si layer can form electrical isolation through a pn junction).

[0138] The storage device according to embodiments of this disclosure can be applied to various electronic devices. For example, the storage device can store various programs, applications, and data required for the operation of the electronic device. The electronic device may also include a processor that works in conjunction with the storage device. For example, the processor can operate the electronic device by running programs stored in the storage device. Such electronic devices include, for example, smartphones, personal computers (PCs), tablet computers, artificial intelligence devices, wearable devices, power banks, automotive electronic devices, communication devices, or Internet of Things (IoT) devices.

[0139] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0140] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A storage device, comprising: A plurality of first device layers are vertically stacked on a substrate, each first device layer including a first source / drain region disposed at a lower vertical height in the first device layer, a second source / drain region disposed at an upper vertical height in the first device layer, and a channel region between the first source / drain region and the second source / drain region; A plurality of second device layers are vertically stacked on the plurality of first device layers, each second device layer including a third source / drain region disposed at a lower vertical height in the second device layer, a fourth source / drain region disposed at an upper vertical height in the second device layer, and a channel region between the third source / drain region and the fourth source / drain region; and A gate stack extending vertically relative to the substrate through the plurality of first device layers and the plurality of second device layers is provided, wherein the gate stack includes a gate conductor layer and a memory functional layer disposed between the gate conductor layer and each of the plurality of first device layers and the plurality of second device layers, and a memory cell is defined at the intersection of the gate stack and each device layer. Wherein, at the junction of the plurality of first device layers and the plurality of second device layers, the gate stack has a bent surface. Each device layer includes a single-crystal semiconductor. In this configuration, the second source / drain region in the uppermost of the plurality of first device layers is formed within vertically stacked first and second semiconductor layers, with a crystal interface between the first and second semiconductor layers. The bending shape of the gate stack surface is located in the uppermost first device layer. The second semiconductor layer is stacked on the first semiconductor layer and includes a downwardly extending portion that extends along the sidewall of the first semiconductor layer toward the first semiconductor layer.

2. The storage device according to claim 1, wherein, The gate conductor layer includes a first portion extending in the first device layer and a second portion above the first portion.

3. The storage device according to claim 2, wherein, The folded shape is such that, when viewed from above, the area defined by the top of the first portion partially overlaps with the area defined by the bottom of the second portion.

4. The storage device according to claim 2, wherein, The bent shape is such that, when viewed from above, the bottom of the second portion is within the area defined by the top of the first portion.

5. The storage device according to claim 2, wherein, The vertical center line of the first part does not coincide with the vertical center line of the second part.

6. The storage device according to claim 5, wherein, The vertical centerline of the first part and the vertical centerline of the second part have a lateral distance of more than 2 nm.

7. The storage device according to claim 2, wherein, The gate conductor layer also includes a connection portion between the first portion and the second portion having a reduced width relative to the top of the first portion and the bottom of the second portion.

8. The storage device according to claim 2 or 7, wherein, The first and second portions of the gate conductor layer are integral.

9. The storage device according to claim 8, wherein, The first portion of the gate conductor layer has a slit that extends approximately along the vertical centerline of the first portion.

10. The storage device according to claim 8, wherein, The storage function layer extends continuously on the surface of the gate conductor layer.

11. The storage device according to claim 2 or 7, wherein, The storage function layer includes a first portion extending on the sidewall of a first portion of the gate conductor layer and a second portion extending on the sidewall of a second portion of the gate conductor layer, wherein the first portion and the second portion of the storage function layer are discontinuous.

12. The storage device according to claim 7, further comprising: A protective sidewall surrounding the outer periphery of the connection portion of the gate conductor layer, the protective sidewall having a material different from that of the storage function layer.

13. The storage device according to claim 7, wherein, The bottom of the second portion of the gate conductor layer partially overlaps with the uppermost first device layer in the vertical direction, and the memory device further includes an isolation layer between the bottom of the second portion of the gate conductor layer and the uppermost first device layer.

14. The storage device according to claim 7, wherein, The top of the first portion of the gate conductor layer partially overlaps with the uppermost first device layer in the vertical direction, and the storage device further includes an isolation layer between the top of the first portion of the gate conductor layer and the uppermost first device layer.

15. The storage device according to claim 7, wherein, The second portion of the gate conductor layer and the connection portion are integral, and the connection portion is in physical contact with the first portion.

16. The storage device according to claim 1, further comprising: A plurality of third device layers are vertically stacked on the plurality of second device layers. Each third device layer includes a fifth source / drain region located at a lower vertical height in the third device layer, a sixth source / drain region located at an upper vertical height in the third device layer, and a channel region between the fifth source / drain region and the sixth source / drain region. The gate stack also extends vertically through the plurality of third device layers. Wherein, the gate stack has a bent-shaped surface at the location where the plurality of second device layers are adjacent to the plurality of third device layers.

17. The storage device according to claim 2, wherein, The protruding portion has a first sidewall and a second sidewall, the first sidewall being substantially coplanar with the sidewall of the storage function layer on the sidewall of the first portion of the gate conductor layer, and the second sidewall extending along the sidewall of the storage function layer on the sidewall of the second portion of the gate conductor layer.

18. The storage device according to claim 1, wherein, Multiple gate stacks are provided, arranged in an array on a substrate, each gate stack having substantially the same bending shape.

19. The storage device according to claim 1, further comprising: A conductive metal layer is disposed on at least one of the lower and upper surfaces of each device layer.

20. The storage device according to claim 19, wherein, Each device layer extends in a lateral direction relative to the substrate, thereby surrounding the outer periphery of the gate stack. The device comprises a plurality of gate stacks arranged in an array on a substrate, wherein each of the conductive metal layers extends on the upper or lower surface of the corresponding device layer to surround the outer periphery of the gate stack.

21. The storage device according to claim 19, wherein, The conductive metal layer is used as a bit line connection or a source line connection.

22. A method for manufacturing a storage device, comprising: A first stack of multiple first semiconductor layers and multiple first sacrificial layers of single crystal is disposed on a substrate, wherein each first semiconductor layer has a first sacrificial layer on at least one side thereof; A first processing channel is formed based on a mask, extending vertically relative to the substrate to pass through the first stack; Using the upper surface of the uppermost first semiconductor layer in the first stack and a portion of the sidewall exposed in the first processing channel as seeds, a seed layer that extends continuously and is single-crystal on the first stack is grown. The uppermost first semiconductor layer and the seed layer in the first stack form the uppermost first device layer, and the remaining first semiconductor layers in the first stack form the remaining first device layers. Each first device layer includes a first source / drain region disposed at a lower vertical height in the first device layer, a second source / drain region disposed at a higher vertical height in the first device layer, and a channel region between the first source / drain region and the second source / drain region. A second stack of multiple second device layers and multiple second sacrificial layers of single crystal is disposed on the seed layer. Each second device layer has a second sacrificial layer on at least one side. Each second device layer includes a third source / drain region disposed at a lower vertical height in the second device layer, a fourth source / drain region disposed at an upper vertical height in the second device layer, and a channel region between the third source / drain region and the fourth source / drain region. Based on the mask, a second processing channel is formed that extends vertically relative to the substrate to pass through the second stack, wherein the second processing channel communicates with the first processing channel; The first sacrificial layer is removed via the first processing channel, and the second sacrificial layer is removed via the second processing channel; A first isolation layer is formed in the space released due to the removal of the first sacrificial layer via the first processing channel; and a second isolation layer is formed in the space released due to the removal of the second sacrificial layer via the second processing channel; and A first gate stack is formed in the first processing channel, the first gate stack including a first gate conductor layer and a first storage function layer disposed between the first gate conductor layer and the first device layer; and a second gate stack is formed in the second processing channel, the second gate stack including a second gate conductor layer and a second storage function layer disposed between the second gate conductor layer and the second device layer, wherein storage cells are defined at the intersections of the first gate stack and each of the first device layers and at the intersections of the second gate stack and each of the second device layers. Where the first device layer and the second device layer are adjacent, the surfaces of the first gate stack and the second gate stack form a bent shape, and the bent shape is in the uppermost first device layer. The seed layer includes a downwardly extending portion that extends along the sidewall of the uppermost first semiconductor layer toward the uppermost first semiconductor layer.

23. The method according to claim 22, wherein, Before the seed layer is grown, the first sacrificial layer is removed and the first isolation layer is formed in the space thus freed up.

24. The method according to claim 23, wherein, After the first isolation layer is formed and before the seed layer is grown, the first gate stack is formed in the first processing channel.

25. The method according to claim 24, wherein, The first gate stack is formed such that its top is recessed relative to the top of the uppermost first device layer, and the method further includes: A protective sidewall is formed on the sidewall of the first processing channel.

26. The method according to claim 24, wherein, The first gate stack is formed such that the top of the first gate conductor layer is recessed relative to the top of the first storage function layer.

27. The method according to claim 25 or 26, further comprising: An isolation layer is formed in the first processing channel to shield the top of the first gate stack. The method further includes, after forming the second processing channel, selectively etching the isolation layer via the second processing channel to form an opening therein, thereby connecting the second processing channel with the first processing channel.

28. The method according to claim 23, in, After forming the first isolation layer and before growing the seed layer, the method further includes: forming a shielding layer on the sidewall of the first processing channel, the top of the shielding layer being recessed relative to the top of the uppermost first device layer. The method further includes, after forming the second isolation layer via the second processing channel: Remove the masking layer; A storage function layer and a gate conductor layer are formed in the first processing channel and the second processing channel that are interconnected with each other. The storage function layer includes the first storage function layer and the second storage function layer, and the gate conductor layer includes the first gate conductor layer and the second gate conductor layer.

29. The method according to claim 22, in, After forming the first processing channel and before growing the seed layer, the method further includes: forming a shielding layer on the sidewall of the first processing channel, the top of the shielding layer being recessed relative to the top of the uppermost first device layer. The method further includes: Remove the masking layer; The first sacrificial layer and the second sacrificial layer are removed via the interconnected first and second processing channels, and the first isolation layer and the second isolation layer are formed respectively in the space thereby released; and A storage function layer and a gate conductor layer are formed in the first processing channel and the second processing channel that are interconnected with each other. The storage function layer includes the first storage function layer and the second storage function layer, and the gate conductor layer includes the first gate conductor layer and the second gate conductor layer.

30. The method according to claim 22, wherein, The operation of forming the first isolation layer via the first processing channel further includes forming a first conductive metal layer on the lower and / or upper surfaces of each first device layer exposed due to the removal of the first sacrificial layer, wherein the first isolation layer electrically isolates the first conductive metal layers from each other. In the operation of forming the second isolation layer via the second processing channel, a second conductive metal layer is also formed on the lower and / or upper surfaces of each of the second device layers exposed due to the removal of the second sacrificial layer, wherein the second isolation layer electrically isolates the second conductive metal layers from each other.

31. The method according to claim 30, in, Removing the first sacrificial layer via the first processing channel and removing the second sacrificial layer via the second processing channel include: A support layer is formed within a portion of a corresponding processing channel in the first processing channel and the second processing channel; and Through other portions of the corresponding processing channels, the corresponding sacrificial layers in the first and second sacrificial layers are removed by selective etching. The process of forming the first conductive metal layer and the first isolation layer via the first processing channel, and forming the second conductive metal layer and the second isolation layer via the second processing channel, includes: The conductive metallic material is formed in a substantially conformal manner through the other portions of the corresponding processing channels; The other portions of the corresponding processing channels are filled with dielectric material; The dielectric material and the conductive metal material are etched back to leave them in the space, and the etched-back dielectric material forms the corresponding isolation layer in the first isolation layer and the second isolation layer; The support layer is removed from the portion of the corresponding processing channel, and a shielding layer is formed in the other portions of the corresponding processing channel; The portion of the conductive metal material extending on the sidewall of the dielectric material is etched via the corresponding processing channel, and the etched conductive metal material forms the corresponding conductive metal layer in the first conductive metal layer and the second conductive metal layer; and Remove the masking layer.

32. An electronic device comprising a storage device as claimed in any one of claims 1 to 21.

33. The electronic device according to claim 32, wherein, The electronic devices include smartphones, personal computers, tablets, artificial intelligence devices, wearable devices, power banks, automotive electronic devices, communication devices, or Internet of Things (IoT) devices.

Images