Electrically tunable optoelectronic neuromorphic semiconductor memristive device and method of fabrication thereof

Abstract

The application relates to the technical field of semiconductor devices, in particular to an electrically adjustable optoelectronic neuromorphic semiconductor memristor device and a preparation method thereof. The optoelectronic neuromorphic semiconductor memristor comprises a top electrode, a window layer, a dielectric layer, a bottom electrode and a substrate which are sequentially connected; wherein the dielectric layer is a PN junction structure composed of CCZTSe / ZnSO. The application takes CCZTSe / ZnSO as the dielectric layer of the neuromorphic device, adopts a solar cell structure, so that the dielectric layer has high light absorption, the device is electrically adjustable, the cost is low, and the preparation process is mature.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to an electrically tunable optoelectronic neuromorphic semiconductor memristor device and its fabrication method. Background Technology

[0002] In the late 1980s, Caltech first proposed the concept of "neuromorphic computing": using very large-scale integrated chips to process information by analog signals, mimicking the nervous system in the biological brain. The current integrated circuit industry faces challenges such as the gradual slowdown of Moore's Law, the sharp increase in energy consumption during size reduction, and the von Neumann bottleneck caused by the separation of in-memory and computing. New methods and new hardware are necessary to supplement and develop existing computing technologies.

[0003] Significant progress has been made in constructing artificial neurons and synaptic circuits using complementary metal-oxide-semiconductor (CMOS) technology, demonstrating the feasibility of large-scale construction of heuristic circuit systems. These devices, capable of building neuromorphic circuits, are called neuromorphic devices (NMDs). They can directly simulate the behavior of synapses and neurons at the physical level. NMDs can mimic many known functions of biological neurons and synapses, and when integrated into arrays, they can directly rely on physical laws to perform large-scale parallel, efficient in-memory computations, such as accelerating vector-matrix multiplication in the training and inference of artificial neural networks. They have already been used to achieve classic machine learning tasks such as information encoding, data classification, and reinforcement learning. Currently, memristors are considered the most promising neuromorphic devices. Memristors are circuit devices that represent the relationship between magnetic flux and electric charge. While memristors have the dimension of resistance, unlike resistors, their resistance is determined by the charge flowing through them. Therefore, by measuring the resistance of a memristor, the amount of charge flowing through it can be determined, thus enabling it to remember charge.

[0004] Currently reported neuromorphic memristor devices are mainly driven by electrical signals, which suffer from high power consumption and poor stability, severely restricting the development of neuromorphic computing. Optoelectronic neuromorphic memristors driven by optical signals have significant advantages in terms of power consumption, speed, and stability. Patent CN110690345A utilizes an ABX3 perovskite active layer as the dielectric layer, and this material also exhibits high photoelectric conversion efficiency. However, perovskite materials suffer from instability and high fabrication difficulty. Therefore, it is evident that in optoelectronic neuromorphic devices, there are still challenges such as difficult material fabrication, complex processes, difficulty in large-scale production, high device cost, and the need to improve uniformity. Summary of the Invention

[0005] This invention provides an electrically tunable optoelectronic neuromorphic semiconductor memristor device with CCZTSe / ZnSO as the dielectric layer and its fabrication method, aiming to solve the synaptic response problem in the near-infrared band, and has the characteristics of being electrically tunable, low cost, and simple process.

[0006] To address the aforementioned technical problems, this invention provides an electrically tunable opto-neuromorphic semiconductor memristor device, comprising a top electrode, a window layer, a dielectric layer, a bottom electrode, and a substrate connected in sequence; wherein the dielectric layer is a PN junction structure composed of CCZTSe / ZnSO.

[0007] In some exemplary embodiments, the top electrode is a NiAlNi dot-shaped metal electrode with a thickness of 500 nm to 1200 nm. Specifically, the top electrode is prepared using electron beam evaporation.

[0008] In some exemplary embodiments, the window layer is made of aluminum-doped zinc oxide (AZO) or indium tin oxide (ITO), with a thickness of approximately 500 nm to 1000 nm. Specifically, the window layer is prepared using magnetron sputtering, a method that produces ZnSO thin films with high transmittance and good uniformity, playing a crucial role in protecting the dielectric layer and improving light transmittance.

[0009] In some exemplary embodiments, the dielectric layer includes an interconnected P-type layer and an N-type layer. The P-type layer is made of a copper-cadmium-zinc-tin-selenide compound or a copper indium selenide group p-type compound, and has a thickness of 10 nm to 100 nm. The N-type layer is made of zinc-sulfur-oxygen compound and has a thickness of 1000 nm to 1500 nm. The P-type layer is prepared using molecular beam epitaxy, and the N-type layer is prepared using atomic layer deposition. The N-type layer forms a PN junction with the copper-cadmium-zinc-tin-selenide compound and prevents oxidation of the P-type layer.

[0010] In some exemplary embodiments, both the N-type layer and the window layer are scribed along a direction perpendicular to the plane of the substrate by photolithography, and the top electrode is deposited on each unit formed by the slicing, thereby effectively preventing leakage current.

[0011] In some exemplary embodiments, the bottom electrode is a molybdenum layer with a thickness of 500 nm to 1000 nm. Specifically, the bottom electrode is fabricated using magnetron sputtering to connect the substrate and the dielectric layer.

[0012] In some exemplary embodiments, the electrode is scribed along a direction perpendicular to the plane of the substrate using photolithography, and each segmented unit is connected to the P-type layer, thereby avoiding the problem of potential detachment of the P-type layer.

[0013] In some exemplary embodiments, the substrate is a silicon substrate or a CMOS chip.

[0014] This invention also provides a method for fabricating an electrically tunable optoelectronic neuromorphic semiconductor memristor device as described above. The method includes: preparing a substrate and depositing a bottom electrode on the substrate by magnetron sputtering; preparing a first etching solution and scribing the bottom electrode using photolithography; wherein the solution ratio of the first etching solution is phosphoric acid:water:acetic acid:nitric acid 250:200:50:4; growing the required compound for a P-type layer on the bottom electrode using molecular beam epitaxy, controlling the substrate temperature at 150°C; and performing a two-stage annealing process in an annealing furnace under a 2%–5% selenium atmosphere, the first stage... The process involves two stages: a first stage at 290℃ for 40-70 minutes, followed by a second stage at 390℃ for 50-80 minutes, to obtain a P-type layer in the dielectric layer. An N-type layer is then prepared on the P-type layer using atomic layer deposition in an atmosphere of argon and hydrogen sulfide. A window layer is prepared on the N-type layer using a magnetron sputtering apparatus. A second etching solution is prepared, and the N-type layer and window layer are etched using photolithography. The second etching solution is 3%-5% dilute hydrochloric acid. A top electrode is then prepared on the window layer using electron beam evaporation to obtain an electrically tunable optoelectronic neuromorphic semiconductor memristor device.

[0015] In some exemplary embodiments, the method specifically includes: Step 1, taking out a completely dust-free silicon substrate and depositing a molybdenum layer on the silicon substrate using magnetron sputtering; Step 2, preparing a molybdenum etching solution and performing a line-scribing process on the molybdenum layer using photolithography; wherein, the molybdenum etching solution has a phosphoric acid:water:acetic acid:nitric acid ratio of 250:200:50:4; laser is also used for line scribing here, but it has a certain impact on the effect of the upper coating layer and may reduce the uniformity of the film. Step 3: Grow a copper-cadmium-zinc-tin-selenium (Ccadmium-Zn-T-Se) layer on the molybdenum layer using molecular beam epitaxy (MBE), controlling the substrate temperature at 150°C. Step 4: Perform a two-stage annealing process in an annealing furnace under a 2%–5% selenium atmosphere: the first stage at 290°C for 40–70 minutes, and the second stage at 390°C for 50–80 minutes, to obtain a P-type layer in the dielectric layer. Step 5: Prepare a zinc-sulfur oxide (ZSO) layer on the Ccadmium-Zn-T-Se layer using an atomic layer deposition (ALD) method in an argon and hydrogen sulfide atmosphere, using a zinc oxide source, to obtain an N-type layer in the dielectric layer. Step 6: Sputter the ZnO:AlO3 layer on the ZSO layer using a magnetron sputtering apparatus with a ZnO:AlO3 ratio of 99.8:0.2 to obtain an aluminum-doped zinc oxide (ANO) layer. Step 7: Prepare an acid etching solution and perform a photolithography etching process to scribing and segment the ZSO layer and the ANO layer; the acid etching solution is 3%–5% dilute hydrochloric acid; over-etching can be appropriately performed here to ensure complete segmentation. Step 8: Fabricate NiAlNi dot-shaped metal electrodes on the aluminum-doped zinc oxide layer using an electron beam evaporation apparatus to obtain an electrically tunable optoelectronic neuromorphic semiconductor memristor device. Note that a mask is required here to align the etched cells.

[0016] The technical solution provided by this invention has at least the following advantages:

[0017] This invention provides an electrically tunable optoelectronic neuromorphic semiconductor memristor device and its fabrication method. CCZTSe / ZnSO is used as the dielectric layer of the neuromorphic device, and a solar cell structure is adopted. This results in high light absorption of the dielectric layer, electrically tunable device, low cost, and mature fabrication process. Attached Figure Description

[0018] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0019] Figure 1 This is a schematic diagram of the overall cross-sectional structure of an electrically tunable optoelectronic neuromorphic semiconductor memristor device provided in an embodiment of the present invention.

[0020] In the figure, 1-substrate, 2-bottom electrode, 3-P-type layer, 4-N-type layer, 5-window layer, 6-top electrode. Detailed Implementation

[0021] As is known from the background technology, existing neuromorphic devices suffer from problems such as unstable performance, high fabrication difficulty, and immature technology. The purpose of this invention is to utilize the high absorption rate and low cost of solar cell structures to fabricate high-performance neuromorphic semiconductor memristors, which are compatible with solar cell structures, have mature technology, can be mass-produced, and can be used to create integrated chips for charging, computing, and sensing.

[0022] Specifically, the first aspect of this invention provides an electrically tunable opto-neuromorphic semiconductor memristor device, the opto-neuromorphic semiconductor memristor comprising a top electrode, a window layer, a dielectric layer, a bottom electrode, and a substrate connected in sequence; wherein the dielectric layer is a PN junction structure composed of CCZTSe / ZnSO. More specifically, Figure 1 A schematic cross-sectional view of an electrically tunable optoelectronic neuromorphic semiconductor memristor device according to one embodiment of the present invention is shown. Figure 1 As shown, the neuromorphic semiconductor memristor includes a substrate 1, a bottom electrode 2 for connecting the substrate and the dielectric layer, a P-type layer 3 and an N-type layer 4 in the dielectric layer, a window layer 5 for protecting the dielectric layer and improving light transmittance, and a top metal electrode 6.

[0023] This invention also provides a method for fabricating an electrically tunable optoelectronic neuromorphic semiconductor memristor device as described above, the method comprising:

[0024] Prepare a substrate 1, and deposit a bottom electrode 2 on the substrate by magnetron sputtering.

[0025] The first etching solution is prepared, and the bottom electrode 2 is scribed using a photolithography etching process; wherein the solution ratio of the first etching solution is phosphoric acid: water: acetic acid: nitric acid 250: 200: 50: 4.

[0026] The required compound for growing the P-type layer 3 on the bottom electrode 2 was grown using a molecular beam epitaxy apparatus, with the substrate temperature controlled at 150°C. The substrate was then annealed in a two-stage annealing furnace under a 2%–5% selenium atmosphere: the first stage at 290°C for 40–70 min, and the second stage at 390°C for 50–80 min, to obtain the P-type layer 3 in the dielectric layer.

[0027] An N-type layer 4 was prepared on the P-type layer 3 using an atomic layer deposition method in an atmosphere of argon and hydrogen sulfide.

[0028] A window layer 5 is fabricated on the N-type layer 4 using a magnetically controlled construction device.

[0029] Prepare a second etching solution and use photolithography etching process to scribing and dividing the N-type layer 4 and window layer 5; wherein the second etching solution is 3% to 5% dilute hydrochloric acid.

[0030] The top electrode 6 is fabricated on the window layer 5 using an electron beam evaporation apparatus to obtain an electrically tunable optoelectronic neuromorphic semiconductor memristor device.

[0031] Example

[0032] The specific preparation method is as follows:

[0033] Step 1: Take out a completely dust-free silicon substrate and use magnetron sputtering to deposit a molybdenum layer on the silicon substrate, with a thickness of approximately 500nm to 1000nm.

[0034] Step 2: Prepare the molybdenum etching solution and use photolithography to scribing and dividing the molybdenum layer;

[0035] The molybdenum etching solution is prepared with a phosphoric acid:water:acetic acid:nitric acid ratio of 250:200:50:4. Laser scribing is also used here, but it has a certain impact on the effect of the upper coating and may reduce the uniformity of the film.

[0036] Step 3: Use a molecular beam epitaxy (MBE) device to grow a copper cadmium zinc tin selenide (CDS) layer on the molybdenum layer. The thickness of the CDS layer is approximately 10 nm to 100 nm, and the substrate temperature is controlled at 150 °C.

[0037] Step 4: Perform two-stage annealing in an annealing furnace under a selenium atmosphere of 2% to 5%. The first stage is 290℃ for 40 to 70 minutes, and the second stage is 390℃ for 50 to 80 minutes to obtain the P-type layer in the dielectric layer.

[0038] Step 5: Using atomic layer deposition, a zinc oxide layer is prepared on a copper-cadmium-zinc-tin-selenium layer in an atmosphere of argon and hydrogen sulfide using a zinc oxide source, resulting in an N-type layer in the dielectric layer with a thickness of approximately 1000 nm to 1500 nm.

[0039] Step 6: Using a magnetron sputtering device, sputtering is performed on the zinc oxide layer with a ZnO:AlO3 ratio of 99.8:0.2 to obtain an aluminum-doped zinc oxide layer with a thickness of approximately 500nm to 1000nm.

[0040] Step 7: Prepare the acid etching solution and use photolithography to scribing and segment the zinc oxide layer and the aluminum-doped zinc oxide layer; wherein, the acid etching solution is 3% to 5% dilute hydrochloric acid; here, over-etching can be appropriately performed to ensure complete segmentation.

[0041] Step 8: Fabricate NiAlNi dot-shaped metal electrodes on the aluminum-doped zinc oxide layer using an electron beam evaporation apparatus to obtain an electrically tunable optoelectronic neuromorphic semiconductor memristor device. Note that a mask is required to align the etched cells; the thickness is approximately 500 nm to 1200 nm.

[0042] In summary, the copper-cadmium-zinc-tin-selenium / zinc-sulfur-oxygen vertical structure neuromorphic semiconductor memristor provided by this invention utilizes a photovoltaic solar cell structure, exhibiting not only excellent synaptic characteristics in the visible light band but also significant synaptic characteristics in the near-infrared band. Furthermore, the synapses can be modulated by voltage, the device technology is mature, and it can be mass-produced, greatly reducing process costs.

[0043] Those skilled in the art will understand that the above-described embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this application. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. An electrically tunable optoelectronic neuromorphic semiconductor memristor device, characterized in that, The opto-neuromorphic semiconductor memristor includes a top electrode, a window layer, a dielectric layer, a bottom electrode, and a substrate connected in sequence. The dielectric layer is a PN junction structure composed of CCZTSe / ZnSO.

2. The electrically tunable optoelectronic neuromorphic semiconductor memristor device according to claim 1, characterized in that, The top electrode is a Ni / Al / Ni stacked point metal electrode with a thickness of 500 nm to 1200 nm.

3. The electrically tunable optoelectronic neuromorphic semiconductor memristor device according to claim 1, characterized in that, The window layer is made of aluminum-doped zinc oxide or indium tin oxide, and has a thickness of 500 nm to 1000 nm.

4. The electrically tunable optoelectronic neuromorphic semiconductor memristor device according to claim 1, characterized in that, The dielectric layer includes a connected P-type layer and an N-type layer. The P-type layer is made of one of the following materials: copper cadmium zinc tin selenide compound or copper indium selenide group p-type compound, with a thickness of 10 nm to 100 nm. The N-type layer is made of zinc sulfur oxide, with a thickness of 1000 nm to 1500 nm.

5. The electrically tunable optoelectronic neuromorphic semiconductor memristor device according to claim 4, characterized in that, Both the N-type layer and the window layer are scribed along a direction perpendicular to the plane of the substrate using photolithography, and the top electrode is deposited on each unit formed by the slicing.

6. The electrically tunable optoelectronic neuromorphic semiconductor memristor device according to claim 1, characterized in that, The bottom electrode is a molybdenum layer with a thickness of 500 nm to 1000 nm.

7. The electrically tunable optoelectronic neuromorphic semiconductor memristor device according to claim 4, characterized in that, The electrode is scribed along a direction perpendicular to the plane of the substrate using photolithography, and each segmented unit is connected to the P-type layer.

8. The electrically tunable optoelectronic neuromorphic semiconductor memristor device according to claim 1, characterized in that, The substrate is a silicon substrate or a CMOS chip.

9. The method for fabricating an electrically tunable optoelectronic neuromorphic semiconductor memristor device according to any one of claims 1 to 8, characterized in that, The method includes: Prepare a substrate and deposit a bottom electrode on the substrate by magnetron sputtering; The first etching solution is prepared, and the bottom electrode is scribing and segmented using photolithography etching process; wherein, the solution ratio of the first etching solution is phosphoric acid: water: acetic acid: nitric acid 250: 200: 50: 4; The required compound for growing the P-type layer on the bottom electrode was grown using a molecular beam epitaxy apparatus, with the substrate temperature controlled at 150°C. The substrate was then annealed in a two-stage annealing furnace under a 2%~5% selenium atmosphere, with the first stage at 290°C for 40~70 min and the second stage at 390°C for 50~80 min, to obtain the P-type layer in the dielectric layer. An N-type layer was prepared on the P-type layer using an atomic layer deposition method in an atmosphere of argon and hydrogen sulfide. A window layer was fabricated on the N-type layer using a magnetically controlled construction device; Prepare a second etching solution and use photolithography to scribing and segment the N-type layer and the window layer; wherein, the second etching solution is 3%~5% dilute hydrochloric acid; A top electrode was fabricated on the window layer using an electron beam evaporation apparatus to obtain an electrically tunable optoelectronic neuromorphic semiconductor memristor device.

10. The method for fabricating the electrically tunable optoelectronic neuromorphic semiconductor memristor device according to claim 9, characterized in that, The method specifically includes: Step 1: Remove the completely dust-free silicon substrate and deposit a molybdenum layer on the silicon substrate using magnetron sputtering; Step 2: Prepare the molybdenum etching solution and use photolithography to scribing and segment the molybdenum layer; wherein, the molybdenum etching solution is prepared in the ratio of phosphoric acid:water:acetic acid:nitric acid of 250:200:50:

4. Step 3: Use a molecular beam epitaxy (MBE) device to grow a copper-cadmium-zinc-tin-selenium (Cd-Zn) layer on the molybdenum layer, and control the substrate temperature at 150°C. Step 4: Perform two-stage annealing in an annealing furnace under a selenium atmosphere of 2%~5%. The first stage is 290℃ for 40 min~70 min, and the second stage is 390℃ for 50 min~80 min to obtain the P-type layer in the dielectric layer. Step 5: Using atomic layer deposition, a zinc oxide layer is prepared on a copper-cadmium-zinc-tin-selenium layer in an atmosphere of argon and hydrogen sulfide using a zinc oxide source, thus obtaining an N-type layer in the dielectric layer. Step 6: Using a magnetron sputtering device, sputtering is performed on the zinc oxide layer with a ZnO:AlO3 ratio of 99.8:0.2 to obtain an aluminum-doped zinc oxide layer; Step 7: Prepare the acid etching solution and use photolithography to scribing and dividing the zinc oxide layer and the aluminum-doped zinc oxide layer; wherein, the acid etching solution is 3%~5% dilute hydrochloric acid; Step 8: Use an electron beam evaporation device to prepare Ni / Al / Ni stacked dot-shaped metal electrodes on the aluminum-doped zinc oxide layer to obtain an electrically tunable optoelectronic neuromorphic semiconductor memristor device.

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