vector processing

Abstract

The present disclosure provides an apparatus comprising: an instruction decoder to decode processing instructions; one or more first registers; first processing circuitry to execute decoded processing instructions in a first processing mode, wherein the first processing circuitry is configured to use the one or more first registers to execute the decoded processing instructions; and control circuitry to selectively initiate execution of the decoded processing instructions in a second processing mode, wherein the decoded processing instructions are selectively executed using one or more second registers; the instruction decoder is configured to decode processing instructions selected from a first instruction set in the first processing mode and to decode processing instructions selected from a second instruction set in the second processing mode, wherein one or both of the first instruction set and the second instruction set comprises at least one instruction that is not available in the other of the first instruction set and the second instruction set; the instruction decoder is configured to decode one or more mode change instructions to change between the first processing mode and the second processing mode; and the first processing circuitry is configured to change the current processing mode between the first processing mode and the second processing mode in response to execution of the mode change instructions.

Description

Background Technology

[0001] This disclosure relates to vector processing.

[0002] Some data processing arrangements allow for vector processing operations, which involve applying a single vector processing instruction to a data item in a data vector that has multiple data items at a corresponding position within the data vector. In contrast, scalar processing operates effectively on individual data items rather than on the data vector itself.

[0003] Vector processing is useful when processing operations are performed on many different instances of data. In a vector processing setup, a single instruction can be applied simultaneously to multiple data items (of a data vector). This can improve the efficiency and throughput of data processing compared to scalar processing.

[0004] It has been proposed to provide a vector processing instruction set that is "agnostic" relative to the physical vector length provided by the hardware, by which the hardware executes code containing instructions from that instruction set. An example is an instruction set defined by the so-called "Scalable Vector Extensions" (SVE) or the SVE2 architecture derived from Arm Ltd. However, the decoding and / or execution of at least some instructions in such an instruction set requires knowledge of an available vector length compatible with the vector length provided by the actual hardware. Summary of the Invention

[0005] In one exemplary arrangement, an apparatus is provided, the apparatus comprising:

[0006] An instruction decoder is used to decode processing instructions.

[0007] One or more first registers;

[0008] A first processing circuit is configured to execute decoded processing instructions in a first processing mode, wherein the first processing circuit is configured to execute the decoded processing instructions using one or more first registers; and

[0009] Control circuitry for selectively initiating the execution of decoded instructions in a second processing mode, wherein one or more second registers are used to selectively execute the decoded instructions;

[0010] The instruction decoder is configured to decode processing instructions selected from a first instruction set in a first processing mode and to decode processing instructions selected from a second instruction set in a second processing mode, wherein one or both of the first and second instruction sets include at least one instruction that is not available in the other of the first and second instruction sets.

[0011] The instruction decoder is configured to decode one or more mode-change instructions used to switch between a first processing mode and a second processing mode; and

[0012] The first processing circuit is configured to change the current processing mode between a first processing mode and a second processing mode in response to the execution of a mode change instruction.

[0013] In another exemplary arrangement, a method is provided that includes:

[0014] Decode the processing instructions;

[0015] In the first processing mode, decoded processing instructions are executed, wherein the processing circuitry is configured to use one or more first registers to execute the decoded processing instructions; and

[0016] Selectively initiate the execution of decoded instructions in a second processing mode, wherein one or more second registers are used to selectively execute the decoded instructions;

[0017] The decoding step includes: decoding a processing instruction selected from a first instruction set in a first processing mode and decoding a processing instruction selected from a second instruction set in a second processing mode, wherein one or both of the first instruction set and the second instruction set include at least one instruction that is not available in the other of the first instruction set and the second instruction set.

[0018] The decoding step includes decoding one or more mode-changing instructions used to switch between a first processing mode and a second processing mode; and

[0019] The execution steps include: in response to the execution of the mode change instruction, changing the current processing mode between the first processing mode and the second processing mode.

[0020] In another exemplary arrangement, a computer program is provided for controlling a host data processing device to provide an instruction execution environment, and includes:

[0021] An instruction decoder is used to decode processing instructions.

[0022] One or more first registers;

[0023] A first processing circuit is configured to execute decoded processing instructions in a first processing mode, wherein the first processing circuit is configured to execute the decoded processing instructions using one or more first registers; and

[0024] Control circuitry for selectively initiating the execution of decoded instructions in a second processing mode, wherein one or more second registers are used to selectively execute the decoded instructions;

[0025] The instruction decoder is configured to decode processing instructions selected from a first instruction set in a first processing mode and to decode processing instructions selected from a second instruction set in a second processing mode, wherein one or both of the first and second instruction sets include at least one instruction that is not available in the other of the first and second instruction sets.

[0026] The instruction decoder is configured to decode one or more mode-change instructions used to switch between a first processing mode and a second processing mode; and

[0027] The first processing circuit is configured to change the current processing mode between a first processing mode and a second processing mode in response to the execution of a mode change instruction.

[0028] Further corresponding aspects and features of this technology are defined by the appended claims. Attached Figure Description

[0029] The present invention will be further described by way of example only, with reference to embodiments shown in the accompanying drawings, wherein:

[0030] Figure 1 The data processing device is shown schematically.

[0031] Figure 2 The use of a device with a dedicated memory management unit is illustrated schematically;

[0032] Figure 3 The data processing equipment is shown schematically.

[0033] Figure 4 and Figure 5 The storage device of the vector length register is schematically shown;

[0034] Figure 6 This is a schematic flowchart illustrating the method;

[0035] Figure 7 The data processing equipment is shown schematically.

[0036] Figures 8 to 10 This is a schematic flowchart illustrating the corresponding method;

[0037] Figure 11 The composite device is schematically illustrated; and

[0038] Figure 12 The simulator implementation is illustrated schematically. Detailed Implementation

[0039] Before discussing the implementation scheme with reference to the accompanying drawings, the following description of the implementation scheme is provided.

[0040] An exemplary embodiment provides an apparatus comprising:

[0041] An instruction decoder is used to decode processing instructions.

[0042] One or more first registers;

[0043] A first processing circuit is configured to execute decoded processing instructions in a first processing mode, wherein the first processing circuit is configured to execute the decoded processing instructions using one or more first registers; and

[0044] Control circuitry for selectively initiating the execution of decoded instructions in a second processing mode, wherein one or more second registers are used to selectively execute the decoded instructions;

[0045] The instruction decoder is configured to decode processing instructions selected from a first instruction set in a first processing mode and to decode processing instructions selected from a second instruction set in a second processing mode, wherein one or both of the first and second instruction sets include at least one instruction that is not available in the other of the first and second instruction sets.

[0046] The instruction decoder is configured to decode one or more mode-change instructions used to switch between a first processing mode and a second processing mode; and

[0047] The first processing circuit is configured to change the current processing mode between a first processing mode and a second processing mode in response to the execution of a mode change instruction.

[0048] The embodiments of this disclosure can provide a mode change initiated by the execution of processing instructions between a first mode and a second mode, the first mode and the second mode having corresponding instruction sets that do not completely overlap and using corresponding first and second sets of registers (it should be noted that the first register and the second register can be different registers, possibly having different sizes and / or capabilities, for example, some of which act as matrix registers and / or at least some of the first register and the second register may be vector registers with potentially different physical vector lengths).

[0049] The instruction decoder is configured to decode processing instructions selected from a first instruction set in a first processing mode and processing instructions selected from a second instruction set in a second processing mode; and one or both of the first and second instruction sets include at least one instruction that is not available in the other of the first and second instruction sets. This advantageously enables the possibility of: (a) providing additional functionality at one processing circuit, for example at the second processing circuit (e.g., a coprocessor), that is not available at the other processing circuit; and (b) avoiding the need to provide some basic functionality at both processing circuits, where such functionality can be appropriately provided by only one processing circuit (e.g., some scalar processing functionality provided only at the first processing circuit). As another example, the second processing circuit may include matrix processing circuitry; and the second instruction set includes one or more matrix processing instructions that are not available in the first instruction set.

[0050] In some embodiments, the processing instructions include vector processing instructions; one or more first registers include one or more first vector registers having a first vector length; in a first processing mode, the first processing circuit is configured to: execute the decoded processing instructions using one or more first vector registers according to a vector length not greater than the first vector length; and in a second processing mode, wherein the decoded processing instructions are selectively executed using one or more second vector registers having a second vector length according to a vector length not greater than the second vector length.

[0051] Such embodiments of the present disclosure can provide an additional mode of operation in the context of vector processing, such that a change between a first processing mode and a second processing mode can be initiated by executing a mode-changing instruction, wherein such a change has the effect of potentially altering the routing of decoded processing instructions (e.g., routing to a second processing circuit, such as a coprocessor, in the second processing mode) and may also alter the vector length applicable to executing instructions in the second processing mode.

[0052] This arrangement advantageously allows, for example, the use of a coprocessor (which may have a hardware vector length different from that of the main CPU (which executes all instructions, for example, in a first processing mode)) while allowing code that may be, for example, vector length-agnostic code to utilize the vector lengths available at the main CPU in the first processing mode and at the coprocessor in the second processing mode.

[0053] In some examples, the first processing circuitry is operable to execute processing instructions at the primary exception level of an exception level hierarchy, each exception level having a corresponding privilege level for accessing the processing resources of the device. For example, the first processing circuitry may be configured to detect the vector length for executing instructions in a first processing mode and the vector length for executing instructions in a second processing mode by executing a vector length detection processing instruction.

[0054] In operation, the first processing circuit can be configured to execute a vector length setting processing instruction at an exception level other than the lowest exception level, to set a maximum vector length applicable to that exception level and at least one lower exception level. In other words, code executed at the lowest exception level cannot set its own maximum vector length during normal operation. For example, the first processing circuit can be configured to execute a vector length setting processing instruction to set the vector length used in a first processing mode to no higher than a first vector length, and to set the vector length used in a second processing mode to no higher than a second vector length. In some examples, the first processing circuit is configured to execute a vector length setting processing instruction at a given exception level to set the vector length used in a given processing mode to no higher than a maximum vector length for that given processing mode, which is set by executing a vector length setting processing instruction at an exception level higher than the given exception level. However, it is worth noting that in some embodiments, the first processing circuit is configured to execute a mode change instruction at any exception level in the exception level hierarchy. The combination of these features allows code execution at the lowest exception level (such as the so-called EL0 level in some practical examples) to initiate a change in processing mode, even though it cannot set the maximum vector length in either the first or second processing mode.

[0055] This disclosure can be embodied in a CPU and coprocessor arrangement, wherein the CPU provides a first processing circuitry and the coprocessor provides a second processing circuitry. In other examples, a single CPU may provide the first and second processing circuitry and an associated set of vector registers. In any case, this disclosure covers an apparatus that further includes: one or more second vector registers having a second vector length; and second processing circuitry configured to execute decoded vector processing instructions according to a vector length not greater than the second vector length.

[0056] In the second processing mode, there is no prohibition on the execution of instructions by the first processing circuit. For example, even when the device is operating in the second processing mode, scalar instructions can be most appropriately executed by the first processing circuit. In order to properly handle the routing of such instructions, in an exemplary embodiment, the control circuit is configured to detect in the second processing mode whether a given processing instruction can be executed by the first processing circuit or by the second processing circuit.

[0057] This disclosure is highly effective for operations in which two or more connected CPUs share a common coprocessor, for example by providing a sequence of instructions for processing by the coprocessor, which are then queued for execution by the coprocessor (such as so-called streaming execution). In such an arrangement, the apparatus may include two or more instances of a first processing circuit; wherein the instruction decoder of each instance of the first processing circuit is configured to selectively route second vector processing instructions to a common second processing circuit.

[0058] As mentioned, in some examples, the vector processing instructions themselves may be unknown relative to the vector length defined by the current processing mode (e.g., using the SVE / SVE2 technique discussed above).

[0059] In some exemplary arrangements, the device includes a vector length register storage device configured to store a vector length not greater than a first vector length for use in a first processing mode, and to store a vector length not greater than a second vector length for use in a second processing mode, wherein the instruction decoder is configured to access the vector length storage device according to the current processing mode.

[0060] In an exemplary arrangement that uses memory address translation, the device may include: a data memory; and address translation circuitry for translating between an input memory address in an input memory address space and an output memory address in an output memory address space, according to which the data memory is accessible. Advantageously, in the second processing mode: the control circuitry can be configured to initiate the translation of the input memory address associated with a processing instruction to be executed by the second processing circuitry, and to provide the translated output memory address to the second processing circuitry. This avoids the need for memory address translation to be performed by the second processing circuitry.

[0061] While there is no fundamental requirement that the first and second processing circuits have different native or inherent vector lengths, in some examples, the second vector length differs from the first vector length. For instance, the second vector length may be greater than the first vector length.

[0062] Another exemplary implementation provides a method comprising:

[0063] Decode the processing instructions;

[0064] In the first processing mode, decoded processing instructions are executed, wherein the processing circuitry is configured to use one or more first registers to execute the decoded processing instructions; and

[0065] Selectively initiate the execution of decoded instructions in a second processing mode, wherein one or more second registers are used to selectively execute the decoded instructions;

[0066] The decoding step includes: decoding a processing instruction selected from a first instruction set in a first processing mode and decoding a processing instruction selected from a second instruction set in a second processing mode, wherein one or both of the first instruction set and the second instruction set include at least one instruction that is not available in the other of the first instruction set and the second instruction set.

[0067] The decoding step includes decoding one or more mode-changing instructions used to switch between a first processing mode and a second processing mode; and

[0068] The execution steps include: in response to the execution of the mode change instruction, changing the current processing mode between the first processing mode and the second processing mode.

[0069] Another exemplary embodiment provides a computer program for controlling a host data processing device to provide an instruction execution environment, and includes:

[0070] An instruction decoder is used to decode processing instructions.

[0071] One or more first registers;

[0072] A first processing circuit is configured to execute decoded processing instructions in a first processing mode, wherein the first processing circuit is configured to execute the decoded processing instructions using one or more first registers; and

[0073] Control circuitry for selectively initiating the execution of decoded instructions in a second processing mode, wherein one or more second registers are used to selectively execute the decoded instructions;

[0074] The instruction decoder is configured to decode processing instructions selected from a first instruction set in a first processing mode and to decode processing instructions selected from a second instruction set in a second processing mode, wherein one or both of the first and second instruction sets include at least one instruction that is not available in the other of the first and second instruction sets.

[0075] The instruction decoder is configured to decode one or more mode-change instructions used to switch between a first processing mode and a second processing mode; and

[0076] The first processing circuit is configured to change the current processing mode between a first processing mode and a second processing mode in response to the execution of a mode change instruction.

[0077] Exemplary device

[0078] Now refer to the attached diagram, Figure 1 A data processing apparatus 100 is schematically shown, which includes one or more central processing units (CPUs) or processing elements 110, 120, 130, a memory management unit (MMU) 140, and a coprocessor 150, all of which are connected to an interconnect 160, to which a main memory subsystem 170 is also connected.

[0079] In operation, each CPU can execute program instructions that can be loaded, for example, from memory subsystem 170 and optionally stored in one or more local caches. The CPU can also reference instructions for execution by coprocessor 150. Techniques for selectively providing local execution (at the CPU) and remote execution (at the coprocessor) will be discussed below.

[0080] Using the techniques described below Figure 1 Therefore, examples of two or more instances 110, 120, 130 of the first processing circuit are provided; wherein the instruction decoder (described below) of each instance of the first processing circuit is configured to selectively decode processing instructions, some of which may be routed to a common second processing circuit 150 for execution (using the techniques below).

[0081] Memory address translation

[0082] The function of MMU 140 is to provide address translation between input memory addresses in the input memory address space (such as virtual addresses VA in the VA space) and output memory addresses in the output memory address space (such as physical addresses PA in the PA space). The reason for providing memory address translation is to allow the CPU and / or different threads or processes executing on the CPU to be isolated, so that they each operate according to their respective VA spaces, where virtual addresses do not grant direct access to data physically stored by the memory subsystem 170. Higher-level control processes (such as the operating system or hypervisor) have control over address translation, and thus, security and isolation can be provided between different CPUs, threads, or processes to prevent one CPU, thread, or process from accessing data that is an attribute (for which access is reserved) of another CPU, thread, or process.

[0083] Figure 1 The use of the standalone MMU 140 shown is only one option. (As...) Figure 2 As illustrated schematically, CPU 200 may have its own MMU functionality 210. Similarly, coprocessor 220 may have its own MMU functionality 230. In other examples, upon initiation of instructions to be executed by the coprocessor, the CPU itself may obtain any necessary address translations and provide the translated memory addresses (such as physical memory addresses) to the coprocessor.

[0084] The examples above have already illustrated a single-level memory address translation process, by way of illustration only. However, more than one level of memory address translation can be used, such as translating from the VA to the intermediate physical address (IPA) and from the intermediate physical address to the PA. One reason why such multi-level address translation can be used in some examples is to allow the first translation level to be controlled by, for example, the operating system, and to allow the second level to be controlled by, for example, a process (such as a hypervisor) that may monitor multiple operating systems.

[0085] This technology is applicable to any of these memory address translation scenarios.

[0086] Exemplary CPU

[0087] Figure 3 This is a schematic diagram showing an example 300 of one of the CPUs 110, ..., 130.

[0088] CPUs are capable of scalar and vector processing.

[0089] The general difference between scalar and vector processing is as follows. Vector processing involves applying a single vector processing operation to multiple data items in a data vector, each data item having a corresponding position within the data vector. In contrast, scalar processing (effectively) operates on individual data items rather than vectors.

[0090] Vector processing is useful when the same or similar processing is applied to many different instances of a data item. In a vector processing arrangement, a single processing instruction can be applied to multiple data items of a data vector, which can be effective simultaneously (but the choice between concurrent or sequential execution is usually left to the hardware designer). This can improve the efficiency and / or throughput of the processing arrangement compared to scalar processing.

[0091] Reference Figure 3 Level 2 cache 305 is connected to memory subsystem 170 via interconnect 160 (307). Level 1 instruction cache 310 provides a more localized cache for processing instructions, and Level 1 data cache 315 provides a more localized cache for data to be retrieved from or stored in memory subsystem.

[0092] The extraction circuit 320 extracts program instructions from the memory subsystem 170 via various caches and provides the extracted program instructions to the decoder circuit 325. The decoder circuit 325 decodes the extracted program instructions and generates control signals to control the execution unit 330 to perform processing operations in at least a first operating mode.

[0093] The indexing of the first operating mode will now be discussed.

[0094] Generally speaking, Figure 3 The device is capable of operating in a first processing mode, wherein the execution unit 330 (as an example of a first processing circuit) is configured to execute decoded processing instructions provided by the decoder circuit 325.

[0095] In the second processing mode, Figure 3 Additional (second) processing circuitry, not shown, is used for at least a portion of the execution of the decoded processing instructions. For example, the second processing circuitry may be located at coprocessor 150 and will be discussed below.

[0096] First processing mode

[0097] In the first processing mode, decoder circuit 325 provides decoded processing instructions of the first instruction set to issuing circuit 335, which controls the issuance of the decoded instructions to execution unit 330, which in turn includes vector processor 332, scalar processor 334, and load / store circuit 336. It should be understood that other user circuits or circuits may be provided as part of the functionality of execution unit 330, but these user circuits or circuits are not shown here for clarity.

[0098] Vector processor 332 uses one or more vector registers 340 with a first vector length VL1 to execute decoded vector processing instructions. Scalar processor 334 uses one or more scalar registers 345 to execute decoded scalar processing instructions. In either case, vector processor 330 or scalar processor 334 may receive values ​​from the corresponding registers and may write the values ​​back to the registers via write-back circuitry 350. When it is necessary to retrieve data from or store data in memory subsystem 170, this is performed by load / store circuitry 336 via a cache arrangement as shown in the drawing. The previously proposed coherent techniques may be applied by a coherent controller (not shown), for example, implemented as part of interconnect 160.

[0099] A set of one or more “ZCR” registers 355 is provided as part of this set of scalar registers 345. Using techniques described below, the ZCR registers provide a primary vector length 360 to the decoder 325 for decoding the extracted instructions. The extracted instructions themselves are “vector length agnostic,” for example, following a so-called “Scalable Vector Extension” (SVE) or SVE2 architecture as defined by Arm Ltd. That is, the program code itself can operate on hardware with vector lengths selectable from at least one set of supported vector lengths, such that the same program code will operate on different hardware with different examples of such vector lengths. However, the actual vector length available to the hardware on which the decoded instructions are to be executed is what is required to decode the instructions into appropriate control signals to control execution.

[0100] Second processing mode

[0101] In the second processing mode, at least some of the operations required to execute the decoded instructions of the second instruction set (which is not entirely consistent with the first instruction set, i.e., at least one of the first and second instruction sets contains instructions that are not available in the other instruction set) are performed by the second processing circuitry (such as coprocessor 150).

[0102] The second processing mode does not require that certain instructions cannot be fully executed by the first processing circuitry. The second processing mode allows instructions to be routed to either the first or second processing circuitry as appropriate. For example, even in the second processing mode, scalar instructions can still be fully executed at the connected CPU. However, instructions can only be routed to the second processing circuitry, such as at the coprocessor, in the second processing mode.

[0103] In this arrangement, the decoder circuit 325 receives a vector length from an alternative register or register field (indicating a suitable length for the second processing circuit). Figure 3 The received vector length is schematically shown as ZCR'. It should be noted that this can (but is not required to) differ from the vector length associated with the first processing circuitry and execution unit 330, and in some examples, it can be greater than the vector length of the first processing circuitry. In such arrangements, the hardware vector lengths VL1, VL2 associated with the first and second processing circuitry can be different, and / or the maximum vector length allowed by the respective ZCR registers can also be different. Decoder circuitry 325 decodes the extracted instructions in the second processing mode, but does not merely route the instructions to execution unit 330; issue circuitry 335 interfaces with coprocessor interface 365, which communicates with coprocessor 150 via interconnect 160 370.

[0104] It should be noted that even when the instruction is executed for the coprocessor, the use of the second processing mode does not completely exclude the possibility of performing some auxiliary operations on the CPU 300 itself.

[0105] In one example, CPU 300 may be associated with memory management unit 140 or its own MMU 210 (if provided) (but for clarity of the diagram, ...). Figure 3 (Not shown in the text) to interact with the coprocessor to obtain any necessary memory address translations for the coprocessor to execute instructions, and to include these translations in the communication with the coprocessor.

[0106] In another example, the coprocessor can generate results (such as scalar values ​​or condition codes) that are returned to the CPU 300 via the coprocessor interface 365 for writing to scalar registers, condition flags, etc.

[0107] In another example, CPU 300 can perform some operations to prepare one or more operands for the coprocessor to act upon.

[0108] In this regard, the processing of any necessary operations at CPU 300 and the transmission of messages defining the required instructions to the coprocessor are handled by issuing circuitry 335 and coprocessor interface 365, which together provide the functionality of control circuitry 375 to selectively initiate the execution of decoded instructions in a second processing mode, wherein the decoded instructions can be executed using (all or at least partially) a second processing circuit having one or more second vector registers, according to a second vector length (e.g., the vector length defined by register field ZCR'). The operation of circuitry 375 can be in response to information provided by the decoder circuitry and / or in response to the current state of the SM bit or field, as discussed below.

[0109] ZCR and ZCR' registers or fields provide an example of a vector length register storage device configured to: store a vector length not greater than a first vector length for use in a first processing mode, and store a vector length not greater than a second vector length for use in a second processing mode, wherein the instruction decoder is configured to access the vector length storage device according to the current processing mode.

[0110] Therefore, in summary, Figure 3 An example of a device is provided, which includes:

[0111] Instruction decoder 325 is used to decode processing instructions that may include vector processing instructions;

[0112] One or more first registers 340, such as a vector register 340 having a first vector length VL1;

[0113] A first processing circuit 330 is configured to execute decoded processing instructions in a first processing mode, wherein the first processing circuit is configured to, for example (in the case that one or more first registers are vector registers), use one or more first registers to execute the decoded processing instructions according to a vector length not greater than a first vector length; and

[0114] Control circuit 375 is used to selectively initiate the execution of decoded instructions in a second processing mode, wherein, for example, based on a vector length not greater than the second vector length, one or more second registers (such as a second vector register) are used to selectively execute the decoded instructions.

[0115] The instruction decoder 325 is configured to decode processing instructions selected from a first instruction set in a first processing mode and to decode processing instructions selected from a second instruction set in a second processing mode, wherein one or both of the first and second instruction sets include at least one instruction that is not available in the other of the first and second instruction sets.

[0116] Instruction decoder 325 is configured to decode one or more mode-change instructions (Mstart, Mstop, discussed below) used to switch between a first processing mode and a second processing mode; and

[0117] The first processing circuit is configured to change the current processing mode between a first processing mode and a second processing mode in response to the execution of a mode change instruction.

[0118] It should be noted that the underlying technologies that provide different capabilities (such as potentially different registers and different or at least not completely overlapping instruction sets) in the first and second modes apply, regardless of whether the processed instructions are vector instructions and whether the registers are vector registers, matrix registers or scalar registers.

[0119] Abnormal level

[0120] In this example, CPU 300 is operable as the primary exception level of a processing instruction and exception level hierarchy, each of which has a corresponding privilege level to access the processing resources associated with CPU 300.

[0121] In one example, four exception levels EL0…EL3 may be provided, where the privilege for accessing processing resources increases with the numerical value n of the ELn name, such that EL3 has a higher privilege than EL2, and so on. The current privilege level can only be changed when the CPU 300 encounters or returns from an exception. In the exemplary arrangement, application code can operate at EL0, the operating system at EL1, the hypervisor at EL2, and the security firmware at EL3. However, this is merely an illustrative example. The term “privilege” can refer to privileges accessing the memory system, and in the given example, can encompass privileges to modify translated information used by the MMU 140 and / or privileges to access other processing resources (such as processing registers).

[0122] Therefore, this arrangement provides an example in which the first processing circuitry is operable to execute processing instructions at the primary exception level of an exception level hierarchy, each of which has a corresponding privilege level for accessing the processing resources of the device.

[0123] Hardware-supported vector length

[0124] While it's theoretically possible to implement a system that allows for any physical (hardware) vector length, in this example, the physical vector length is constrained to a multiple of 128 bits, up to a maximum of 2048 bits. In some examples, only hardware support for multiples of 128 bits related to powers of 2 is required, i.e., 128 × 2. nHowever, at a general level, it can be assumed that there exists a set of permissible vector lengths and a maximum vector length that can be supported by hardware in at least some implementations. Specific examples of hardware may, of course, have a single associated physical vector length (e.g., 256 bits).

[0125] ZCR register

[0126] Figure 4 and Figure 5 Provided Figure 3 A schematic example of ZCR register 355. Generally, a ZCR register is provided for each of EL1, EL2, and EL3. ZCR_EL3 is a control register used to control the accessible vector lengths of EL3, EL2, EL1, and EL0. ZCR_EL2 is a control register used to control the accessible vector lengths of EL2, as well as the so-called non-secure EL1 and EL0. ZCR_EL1 is a control register used to control the accessible vector lengths of EL1 and EL0. In each case, the second part of the register name indicates the privilege level or exception level required to change the contents of the register, such that, for example, ZCR_EL3 requires changing the exception level EL3.

[0127] These ZCR registers are hierarchical, such that ZCR_EL2 cannot select a vector length longer than that defined by ZCR_EL3, and similarly, if EL2 is implemented and enabled under the same security conditions as EL1 (which can be controlled by the SCR_EL3.EEL2 control), then ZCR_EL1 cannot select a vector length longer than that defined by ZCR_EL2. It should also be noted that EL2 and EL3 are actually optional for a given specific implementation; therefore, the EL2 / EL3 constraints only apply if those exception levels are implemented.

[0128] In other words, the first processing circuit is configured to execute a vector length setting processing instruction at a given exception level to set the vector length used in a given processing mode to no higher than the maximum vector length for the given processing mode, which is set by executing a vector length setting processing instruction at an exception level higher than the given exception level.

[0129] exist Figure 4 In the example, two sets of ZCR registers are provided, one set 400 for a first processing mode and one set 410 for a second processing mode, wherein appropriate control circuitry 420 routes desired values ​​to and from the appropriate registers. Figure 5 In the example, each register 500 has two fields 510 and 520, which store relevant values ​​for either the first processing mode or the second processing mode.

[0130] You can use the reference Figure 6 The technique discussed uses a hardware-supported vector length to populate the ZCR register.

[0131] exist Figure 3 In the SVE / SVE2 processor of the type shown, the instruction set itself is vector-length unknown, but the ZCR register is filled by querying the hardware to find the actual vector length implemented by the physical circuitry in which the instruction to be executed is to be executed. As described above, the vector length defined by the ZCR register applicable to the current exception level is used by the decoding process to decode the extracted program instructions.

[0132] Figure 6 The process can be performed sequentially at each exception level, starting from the highest exception level EL3 and proceeding down to EL1. It should be noted that instructions executed at EL0 cannot modify any register within the ZCR register itself, but can detect the effect of at least the ZCR_EL1 register on the available vector length.

[0133] At step 600, program instructions are executed to write values ​​to the relevant ZCR register (ZCR_EL3, assuming the procedure is first run in EL3). This could be, for example, the maximum vector length mentioned above (e.g., 2048 bits). Then, at step 610, the hardware is polled, for example, by executing an RDVL (Read Vector Length) instruction, to detect the effect of the same ZCR register on the available vector lengths. This prompts the hardware to write to the target register of the instruction a vector length it can support, and that the vector length is as close as possible to, but not greater than, the vector length written to the ZCR_EL3 register. Thus, the program code can detect the result of the procedure at step 620 based on the detection of at least one usable, permissible vector length. The procedure can be executed iteratively at a specific exception level to populate one or more vector lengths currently allowed by the hardware. This procedure can be performed, for example, at device startup.

[0134] Once one or more hardware-supported vector lengths for that group have been derived in this way, the ZCR_EL3 register can be filled with one of the allowed vector lengths.

[0135] The list of supported vector lengths is a fundamental property of the design of the first and second vector processors and their vector register files. The coprocessor can transfer a set of its supported vector lengths to the CPU, or this set can be fixed and known to both the CPU and the coprocessor.

[0136] The RDVL instruction does not modify the ZCR value itself; it only returns the vector length (or the highest hardware-supported value compatible with it) selected by the ZCR_ELn register. The ZCR is written via a separate MSR (Move to System Register) instruction. In practice, when writing to ZCR_ELn, or when the exception level changes due to an exception occurrence or return, resulting in the application of a different set of ZCR registers, a new vector length (VL) can be calculated and stored in internal CPU memory used by the CPU decoder and returned via RDVL.

[0137] The processing at the RDVL instruction level can therefore include, for example, the following. The hardware has information available to it (e.g., as a hard-coded storage device 342 or as part of the functionality of the vector register itself), which indicates one or more hardware-supported vector lengths that the hardware can operate at. The RDVL instruction execution prompt execution unit 330 detects the hardware vector length from this source and (considering the value held by the relevant ZCR register) sets the VL used for the current application to a value that is as high as possible while being compatible with this information and the value previously written to the ZCR register, and returns the set value.

[0138] Once all this has happened, a similar process can be performed for ZCR_EL2, causing the register to be filled with an allowed vector length no greater than the vector length held by ZCR_EL3. Similarly, the same process can be performed for ZCR_EL1.

[0139] Thus, in subsequent normal operations following the above initialization process, the ZCR_ELn register or register field contains the corresponding hardware-supported vector length.

[0140] The alternative field or register ZCR_ELn can be filled using a similar technique, but operates in a second processing mode where the hardware response may originate from a second processing circuit (such as a coprocessor) rather than the first processing circuit (execution unit 330) and will reflect the vector length of the vector register, as discussed below, and other hardware capabilities associated with the second processing circuit. The hardware capabilities of the second processing circuit may be stored (similar to 342 or as part thereof) at the first processing circuit, where the first and second processing circuits are, for example, discussed below. Figure 11 The shown are either implemented jointly as a common System-on-Chip (SoC) or Network-on-Chip (NoC), or, in the case of a discrete coprocessor, can be obtained by querying a similar hardware storage device at the coprocessor.

[0141] therefore, Figure 6An example is provided in which the first processing circuit is configured to detect the vector length for executing instructions in a first processing mode and the vector length for executing instructions in a second processing mode by executing a vector length detection processing instruction.

[0142] The ZCR register settings (for example, as mentioned above) Figure 6 The process discussed at the end provides an example in which the first processing circuit is configured to execute a vector length setting processing instruction at an anomaly level other than the lowest anomaly level, to set a maximum vector length applicable to that anomaly level and at least one lower anomaly level. This is also an example in which the first processing circuit is configured to execute a vector length setting processing instruction to set a vector length used in a first processing mode to be no higher than a first vector length, and to set a vector length used in a second processing mode to be no higher than a second vector length.

[0143] Exemplary coprocessor

[0144] Figure 7 An example 700 of a coprocessor (such as coprocessor 160) is schematically shown. The coprocessor communicates 705 with one or more connected CPUs 110…130 via an interconnect and also provides a Level 2 cache 710 and a Level 1 cache 715 associated with load / store circuitry 720 to provide communication with the memory subsystem. It should be noted that in some embodiments, and depending on the overall system design, some caches (such as the Level 2 cache) may be shared between the CPU (or, if only one is provided) and the coprocessor.

[0145] In this example, the second processing circuit 725 includes a vector processor 730, a matrix processor 735, and a load / store circuit 720. This second processing circuit is associated with a matrix register 740 and a vector register 745, both having a physical vector length VL2, which may be the same as or different from VL1 of the first processing circuit. In some examples, VL2 may be greater than VL1.

[0146] Generally speaking, at the coprocessor 700, a corresponding set of registers 740, 745 is provided for each of the connected CPUs. This corresponding set allows interleaved instructions to be executed on behalf of different CPUs without writing the register contents back to main memory (which is generally expected to be a slow process compared to the time it takes to execute instructions received from the connected CPUs).

[0147] The write-back circuit 760 controls the writing of the results from the second processing circuit 725 back to registers 740 and 745.

[0148] Examples of first and second instruction sets

[0149] Matrix processor 735 executes specialized matrix processing instructions that, in this example, are not available for execution by CPU execution unit 330. Similarly, some instructions executable by the CPU (e.g., aggregate load and scatter store vector operations and / or some scalar operations that can be performed sufficiently and efficiently at a connected CPU) are not available for execution by second processing circuitry 725. This provides an example where an instruction decoder is configured to decode processing instructions selected from a first instruction set in a first processing mode and processing instructions selected from a second instruction set in a second processing mode; and one or both of the first and second instruction sets include at least one instruction that is not available in the other of the first and second instruction sets. In an example where the second processing circuitry includes matrix processing circuitry, the second instruction set may include one or more matrix processing instructions that are not available in the first instruction set.

[0150] Queuing and streaming

[0151] Communication from the connected CPU is handled by a queue manager 760, which receives information defining instructions that need to be executed for a specific CPU and forms a queue of such instructions associated with the identity of the connected CPU requesting the instruction. When an instruction arrives at the appropriate level in the queue, it is passed to an optional decoder circuit 765. This is called "optional" because in some examples, the entire decoding process can occur at the connected CPU, such that the information passed to the coprocessor is in a decoded form; however, in other examples, at least a partial level of decoding may be required at the coprocessor. From there, control signals are passed to an issuing circuit 770 to control the issuance of instructions to the second processing circuit 725.

[0152] In many exemplary instances, no additional interaction is required beyond the handshake interaction confirming successful reception and queuing of instructions from the connected CPU. That is, the connected CPU can instruct the coprocessor to retrieve information from memory or registers, perform a specific operation on that information, and store the result in a register or memory. As long as the instruction is completed before subsequent instructions that may depend on it are submitted, no additional information needs to be returned to the connected CPU that requested the instruction. Thus, the operation of the connected CPU providing instructions to the coprocessor can be called a so-called "streaming mode" because consecutive instructions can be transmitted to the coprocessor, where the only interaction is a handshake indicating successful reception and queuing.

[0153] However, it is conceivable that a coprocessor executes instructions, generating results that need to be returned to the CPU of the connected network that requested the execution. Examples could include extracting a single scalar value from a vector or matrix held at the coprocessor and returned to the CPU of the connected network that requested the instruction, or generating condition codes that are also returned to the CPU of the connected network that requested the instruction. This type of reverse interaction could also be handled by a queue manager, which could represent interactions with connected CPUs via interconnect 160.

[0154] One or both of the queue manager 760 and the issuing circuit 770 can control which group of registers 750 is enabled for execution of a specific instruction by the second processing circuit 725, such that the appropriate group for the CPU of the connection requesting the execution of the instruction is used.

[0155] therefore, Figure 7 An example is provided, showing: one or more second vector registers 745 (750) having a second vector length; and a second processing circuit 725 configured to execute decoded vector processing instructions based on a vector length not greater than the second vector length.

[0156] Example of communication between a connected CPU and a coprocessor

[0157] The connected CPU can provide the coprocessor with at least some of the following information, for example, in the form of data processing transactions or packets addressed to the coprocessor:

[0158] • Identification of the connected CPU (to allow selection of the correct register set at the coprocessor, allow queue arbitration, and / or provide a return address for handshake or response signals);

[0159] • The identity of the coprocessor (if any ambiguity exists);

[0160] • The identifier of the instruction to be executed (which may be an opcode that needs to be at least partially decoded at the coprocessor; it may be in decoded form);

[0161] • Identification and / or values ​​of one or more operands (e.g., one or more PAs; one or more VAs or IPAs that the coprocessor will need to obtain for translation; identification of one or more coprocessor registers);

[0162] • The value required by the instruction for the selected scalar register.

[0163] As described above, the CPU can provide the translated PA to the coprocessor, which avoids the need for the coprocessor to have its own MMU functionality or to initiate actions performed by a separate MMU. An example is provided where the device provides: a data memory 170; and address translation circuitry 140, 210 for translating input memory addresses in the input memory address space and output memory addresses in the output memory address space, according to which the data memory can be accessed; wherein in a second processing mode, control circuitry 375 is configured to initiate the translation of the input memory address associated with a processing instruction to be executed by the second processing circuitry, and to provide the translated output memory address to the second processing circuitry.

[0164] Switching between the first processing mode and the second processing mode

[0165] A pair of instructions is provided to execute at the CPU at any exception level (from EL0 upwards) to switch between a first processing mode and a second processing mode. In other words, the first processing circuitry is configured to execute mode-changing instructions at any exception level in the exception level hierarchy. These instructions are:

[0166] Mstart: It switches the operation to the second processing mode, that is, the execution unit 330 performs at least the following operations in response to the Mstart instruction:

[0167] • Configure "Streaming Mode" (SM) control bits, registers, or fields (e.g., at the decoder, execution unit, or scalar register, so that they can be referenced by various units of the CPU) to indicate the second processing mode.

[0168] • Choose the ZCR_ELn variant that uses the ZCR register / field

[0169] • Enable the instruction set associated with the second processing circuitry

[0170] • The control decoder circuit 325 decodes the instructions of the instruction set into appropriate control signals that will be forwarded to the second processing circuit.

[0171] • The control circuit 375 selectively initiates the execution of decoded instructions by the second processing circuit.

[0172] Mstop: It switches the operation to the first processing mode, that is, the execution unit 330 performs at least the following operations in response to the Mstop instruction:

[0173] • Cancel setting the "Streaming Mode" (SM) control bit, register, or field to indicate the first processing mode.

[0174] • Choose the ZCR_ELn variant that uses the ZCR register / field

[0175] • Enable the instruction set associated with the first processing circuit.

[0176] • The control decoder circuit 325 decodes the instructions of the instruction set into appropriate control signals to be sent to the first processing circuit.

[0177] • The control circuit 375 sends a decoded command to the first processing circuit.

[0178] As mentioned above, these instructions can be executed at any exception level. Therefore, compared to the setting of the ZCR register (which cannot be executed in EL0), these provide a technique available even in EL0 to potentially change the main vector length of the instructions being executed.

[0179] It should be noted that the change from one vector length to another is not necessarily a change between the physical vector lengths VL1 and VL2 of the first and second processing circuits, but rather a change between the main permissible vector lengths defined by the ZCR register for the first and second processing circuits, which is suitable for the main exception level.

[0180] It should be noted here that the exception level discussed is the primary exception level at the CPU of a specific connection.

[0181] pass Figure 8 The schematic flowchart summarizes the use of these instructions. Here, the execution of the Mstart instruction 800 causes various results 810, including accessing the second processing mode register or register field ZCR_ELn', decoding the second processing mode instruction set, and routing the decoded instructions to the coprocessor where appropriate. The execution of the Mstop instruction 820 causes results 830, including accessing the first processing mode register or register field ZCR_ELn, decoding the first processing mode instruction set, and executing the decoded instructions at the first processing circuit. The SM bit is also set / de-set as described above, although in Figure 8 Not shown in the image.

[0182] Example of operation in the second processing mode

[0183] Figure 9 The exemplary flowchart assumes that at the starting point 900 of the second processing mode, that is, the Mstart instruction has been executed. Figure 9 The arrangement is such that operations performed by the connected CPU are schematically shown on the left side of the dashed line 905, and operations performed by the coprocessor are shown on the right side of the drawn dashed line 905.

[0184] At step 910, the connected CPU's decoder circuitry decodes the next fetched instruction based on a major vector length suitable for the major exception level, as defined by a register or register field ZCR_ELn'. If necessary, at step 915, the CPU obtains one or more operands associated with the decoded instruction.

[0185] Even in the second processing mode, some instructions (such as scalar instructions) may not need to be executed by the coprocessor. This relates to the terminology used regarding the "selective" initiation of execution by the second processing circuitry. At step 920, a detection is made as to whether this operation is needed (e.g., by comparing the current instruction with a predetermined set of instructions in that category), and if not, control proceeds to step 925, where an instruction is issued for the first processing circuitry to execute locally. Control then proceeds to step 930, where the process is repeated for the next instruction. This provides an example where the control circuitry is configured in the second processing mode to detect whether a given processing instruction is executable by the first or second processing circuitry.

[0186] However, if the second processing circuitry needs to execute at least a portion of the code, control proceeds to step 935, where instruction definition information is transmitted to the coprocessor. At step 940, a check is performed to determine whether any results need to be returned at the connected CPU. If the answer is yes, the connected CPU halts at step 945 to await these results before proceeding control to step 930. If the answer is no, control proceeds directly to step 930.

[0187] The test performed at step 940 involves a simple mapping of instruction types. Some instruction types will produce the results expected to be returned at the connected CPU, but some instruction types (instructions that can operate in the so-called streaming mode described above) will not produce results.

[0188] The operation at the coprocessor, step 950, involves receiving communication from the connected CPU, queuing the communication, and acknowledging it.

[0189] At step 952, the next instruction is dequeued from the head of the queue and (at step 955) decoded or further decoded if necessary (as discussed above). At step 960, the instruction is executed at the second processing circuit. If it is not necessary to send the results back to the connected CPU, the process can end at the coprocessor; however, if the results are needed, they are returned at step 965. Control then returns to step 952 to dequeue the next instruction from the queue.

[0190] Therefore, it should be noted that the loops 952…965 can operate independently of step 950, that is, in the streaming operation mode described above, except that, as in the instance of step 950, at least some filling of the queue is required from time to time. As long as the queue contains instructions, the execution performed at the coprocessor by loops 952…965 will continue to process each instruction from the queue (if the queue is empty, step 952 will only pause or stop until an instruction enters the queue). Step 960 will proceed whenever the CPU sends an instruction to the coprocessor to be added to the queue.

[0191] Invention Content and Method

[0192] Figure 10 This is a schematic flowchart illustrating a method, which includes:

[0193] Decode the processing instructions (at step 1000);

[0194] In the first processing mode, the decoded processing instructions are executed (at step 1010), wherein the processing circuitry is configured to use one or more first registers to execute the decoded processing instructions; and

[0195] Execution of the decoded instructions is selectively initiated in the second processing mode (at step 1020), wherein one or more second registers are used to selectively execute the decoded instructions;

[0196] The decoding step includes: decoding a processing instruction selected from a first instruction set in a first processing mode and decoding a processing instruction selected from a second instruction set in a second processing mode, wherein one or both of the first instruction set and the second instruction set include at least one instruction that is not available in the other of the first instruction set and the second instruction set.

[0197] The decoding step includes decoding one or more mode-changing instructions used to switch between a first processing mode and a second processing mode; and

[0198] The execution steps include: in response to the execution of the mode change instruction, changing the current processing mode between the first processing mode and the second processing mode.

[0199] Single CPU implementation

[0200] The second processing circuit is not required to be implemented by a separate processing device (such as the coprocessor discussed above). In fact, the second processing circuit can be provided by a second processing circuit contained within a single CPU, which thus provides both the first and second processing circuits, possibly with different associated vector lengths and different sizes of vector registers.

[0201] Figure 11 Such an arrangement is schematically illustrated, wherein the processing unit or CPU 1100 includes connections to... Figure 7 Circuit 1120 Figure 3 Circuit 1110. In at least some examples, interconnectors of the type described above are not required; that is, they can be used... Figure 3 The control circuit of the circuit and Figure 7 The circuit queue managers use direct connections, but in other examples (such as SoC or NoC), the interconnects described above can be provided.

[0202] It should be noted that in this implementation, the "queue manager" arrangement may not even be necessary; the second processing circuit may be located within the CPU resources, and some or all of the instructions associated with the second mode may be executed using only the CPU vector processing resources, but with a second vector length (which may be the same as or different from the first vector length).

[0203] Simulator Implementation Plan

[0204] Figure 12 This demonstrates that it can be used with respect to a standalone CPU as described above, or in combination with a coprocessor, or according to... Figure 11The invention is implemented in a specific manner for the use of an emulator. While the previously described embodiments implement the invention in terms of means and methods for operating specific processing hardware supporting the technologies involved, it is also possible to provide an instruction execution environment according to the embodiments described herein, which is implemented using a computer program. Such computer programs are generally referred to as emulators, in part because they provide a software-based implementation of a hardware architecture. Types of emulator computer programs include simulators, virtual machines, models, and binary converters, including dynamic binary converters. Typically, the emulator implementation can run on a host processor 1230 that supports the emulator program 1210, which optionally runs a host operating system 1220. In some arrangements, multiple emulation layers may exist between the hardware and the provided instruction execution environment and / or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors were required to provide emulator implementations that execute at a reasonable speed, but this approach may be reasonable in certain situations, such as when it is desirable to run code native to another processor for compatibility or reuse reasons. For example, the emulator implementation may provide additional functionality to the instruction execution environment that is not supported by the host processor hardware, or provide an instruction execution environment that is typically associated with a different hardware architecture. An overview of the simulation is given in the following literature: “Some Efficient Architecture Simulation Techniques”, Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0205] With respect to embodiments previously described with reference to specific hardware constructions or features, in simulated embodiments, equivalent functionality may be provided by suitable software constructions or features. For example, a particular circuit system may be implemented as computer program logic in a simulated embodiment. Similarly, memory hardware such as registers or cache memory may be implemented as software data structures in a simulated embodiment. One or more of the hardware elements referenced in the previously described embodiments are present in an arrangement on host hardware (e.g., host processor 1230), and where appropriate, some simulated embodiments may utilize the host hardware.

[0206] The simulator program 1210 may include, for example, instruction decoding program logic 1212, register simulation program logic 1214, and address space mapping program logic 1216, and may be stored on a computer-readable storage medium (which may be a non-transitory medium). It provides a program interface (instruction execution environment) to the target code 1200 (which may include an application program, operating system, and management program), the same as the application program interface of the hardware architecture modeled by the simulator program 1210. Therefore, the simulator program 1210 can be used to execute program instructions of the target code 1200 from within the instruction execution environment, including the aforementioned features, enabling a host computer 1230, which does not actually possess the hardware features described above, to emulate these features.

[0207] When used for simulation, such as reference Figure 3 When describing the operation, Figure 12 The arrangement thus provides an example of a computer program for controlling the host data processing device to provide an instruction execution environment, the computer program comprising:

[0208] An instruction decoder is used to decode processing instructions;

[0209] One or more first registers;

[0210] A first processing circuit is configured to execute decoded processing instructions in a first processing mode, wherein the first processing circuit is configured to execute the decoded processing instructions using one or more first registers; and

[0211] Control circuitry for selectively initiating the execution of decoded instructions in a second processing mode, wherein one or more second registers are used to selectively execute the decoded instructions;

[0212] The instruction decoder is configured to decode processing instructions selected from a first instruction set in a first processing mode and to decode processing instructions selected from a second instruction set in a second processing mode, wherein one or both of the first and second instruction sets include at least one instruction that is not available in the other of the first and second instruction sets.

[0213] The instruction decoder is configured to decode one or more mode-change instructions used to switch between a first processing mode and a second processing mode; and

[0214] The first processing circuit is configured to change the current processing mode between a first processing mode and a second processing mode in response to the execution of a mode change instruction.

[0215] Overview

[0216] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operations. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operations, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operations.

[0217] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of the invention as defined in the appended claims.

Claims

1. A data processing apparatus, the apparatus comprising: An instruction decoder, which is used to decode processing instructions; One or more first registers; A first processing circuit is configured to execute a decoded processing instruction in a first processing mode, wherein the first processing circuit is configured to use the one or more first registers to execute the decoded processing instruction. and A control circuit for selectively initiating the execution of the decoded instructions in a second processing mode, wherein one or more second registers are used to selectively execute the decoded instructions; The instruction decoder is configured to decode processing instructions selected from a first instruction set in the first processing mode and to decode processing instructions selected from a second instruction set in the second processing mode, wherein one or both of the first instruction set and the second instruction set include at least one instruction that is not available in the other of the first instruction set and the second instruction set. The instruction decoder is configured to decode one or more mode-change instructions for switching between the first processing mode and the second processing mode; and The first processing circuit is configured to change the current processing mode between the first processing mode and the second processing mode in response to the execution of a mode change instruction. in: The processing instructions include vector processing instructions; The one or more first registers include one or more first vector registers having a first vector length; In the first processing mode, the first processing circuit is configured to: execute the decoded processing instruction using the one or more first vector registers according to a vector length not greater than the first vector length; and In the second processing mode, the decoded processing instructions are selectively executed using one or more second vector registers having the second vector length, based on a vector length not greater than the second vector length.

2. The apparatus of claim 1, wherein the first processing circuit is operable to execute processing instructions at a major anomaly level of an anomaly level hierarchy, each of the anomaly levels having a corresponding privilege level to access the processing resources of the apparatus.

3. The apparatus of claim 2, wherein the first processing circuit is configured to: detect the vector length for executing instructions in the first processing mode and the vector length for executing instructions in the second processing mode by executing a vector length detection processing instruction.

4. The apparatus of claim 2 or claim 3, wherein the first processing circuit is configured to execute a vector length setting processing instruction at an anomaly level other than the lowest anomaly level to set a maximum vector length applicable to the anomaly level and at least one lower anomaly level.

5. The apparatus of claim 4, wherein the first processing circuit is configured to execute the vector length setting processing instruction to set the vector length used in the first processing mode to be no higher than the first vector length, and to set the vector length used in the second processing mode to be no higher than the second vector length.

6. The apparatus of claim 5, wherein the first processing circuit is configured to: execute the vector length setting processing instruction at a given anomaly level to set the vector length used in a given processing mode to be no higher than the maximum vector length for the given processing mode, the maximum vector length being set by executing the vector length setting processing instruction at an anomaly level higher than the given anomaly level.

7. The apparatus of claim 2 or claim 3, wherein the first processing circuit is configured to execute the mode change instruction at any anomaly level of the anomaly level hierarchy.

8. The apparatus according to any one of claims 1 to 3, wherein the apparatus comprises: One or more second vector registers, the one or more second vector registers having the second vector length; and A second processing circuit is configured to execute the decoded processing instruction based on a vector length not greater than the second vector length.

9. The apparatus according to any one of claims 1 to 3, wherein the vector processing instruction is unknown relative to the vector length defined by the current processing mode.

10. The apparatus according to any one of claims 1 to 3, the apparatus comprising a vector length register storage device configured to: store a vector length not greater than the first vector length for use in the first processing mode, and store a vector length not greater than the second vector length for use in the second processing mode, the instruction decoder being configured to access the vector length register storage device according to the current processing mode.

11. The apparatus according to any one of claims 1 to 3, wherein the second vector length is different from the first vector length.

12. The apparatus of claim 11, wherein the second vector length is greater than the first vector length.

13. The apparatus of claim 8, wherein the control circuit is configured to detect, in the second processing mode, whether a given processing instruction can be executed by the first processing circuit or by the second processing circuit.

14. The apparatus of claim 8, wherein the apparatus comprises: Two or more instances of the first processing circuit; The instruction decoder of each instance of the first processing circuit is configured to selectively route processing instructions to a common second processing circuit.

15. The apparatus of claim 8, wherein the second processing circuit comprises a matrix processing circuit and one or more matrix registers; and The second instruction set includes one or more matrix processing instructions that are not available in the first instruction set.

16. The apparatus of claim 8, wherein the apparatus comprises: Data storage; and The address translation circuit is used to translate between the input memory address in the input memory address space and the output memory address in the output memory address space, so that the data memory can be accessed according to the output memory address space; In the second processing mode, the control circuit is configured to initiate the translation of an input memory address associated with a processing instruction to be executed by the second processing circuit, and to provide the translated output memory address to the second processing circuit.

17. A data processing method, the method comprising: Decode the processing instructions; In a first processing mode, a decoded processing instruction is executed, wherein the processing circuitry is configured to use one or more first registers to execute the decoded processing instruction. as well as The execution of the decoded instructions is selectively initiated in a second processing mode, wherein one or more second registers are used to selectively execute the decoded instructions; The decoding step includes: decoding a processing instruction selected from a first instruction set in the first processing mode and decoding a processing instruction selected from a second instruction set in the second processing mode, wherein one or both of the first instruction set and the second instruction set include at least one instruction that is not available in the other of the first instruction set and the second instruction set. The decoding step includes decoding one or more mode-changing instructions for switching between the first processing mode and the second processing mode; and The execution steps include: in response to the execution of a mode change instruction, changing the current processing mode between the first processing mode and the second processing mode. in: The processing instructions include vector processing instructions; The one or more first registers include one or more first vector registers having a first vector length; The first processing mode includes executing the decoded processing instruction using the one or more first vector registers according to a vector length not greater than the first vector length; and In the second processing mode, the execution of the decoded processing instruction is selectively initiated using one or more second vector registers having the second vector length, based on a vector length not greater than the second vector length.

18. A computer-readable storage medium storing a computer program for controlling a host data processing device to provide an instruction execution environment, the instruction execution environment comprising: An instruction decoder, which is used to decode processing instructions; One or more first registers; A first processing circuit is configured to execute a decoded processing instruction in a first processing mode, wherein the first processing circuit is configured to use the one or more first registers to execute the decoded processing instruction. and A control circuit for selectively initiating the execution of the decoded instructions in a second processing mode, wherein one or more second registers are used to selectively execute the decoded instructions; The instruction decoder is configured to decode processing instructions selected from a first instruction set in the first processing mode and to decode processing instructions selected from a second instruction set in the second processing mode, wherein one or both of the first instruction set and the second instruction set include at least one instruction that is not available in the other of the first instruction set and the second instruction set. The instruction decoder is configured to decode one or more mode-change instructions for switching between the first processing mode and the second processing mode; and The first processing circuit is configured to change the current processing mode between the first processing mode and the second processing mode in response to the execution of a mode change instruction. in: The processing instructions include vector processing instructions; The one or more first registers include one or more first vector registers having a first vector length; In the first processing mode, the first processing circuit is configured to: execute the decoded processing instruction using the one or more first vector registers according to a vector length not greater than the first vector length; and In the second processing mode, the decoded processing instructions are selectively executed using one or more second vector registers having the second vector length, based on a vector length not greater than the second vector length.

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