Wideband low phase noise digitally controlled oscillator using a switched inductor

Abstract

A digitally-controlled oscillator (DCO) is provided. In one aspect, the DCO includes a resonant tank that can include a plurality of inductors and a plurality of metal-oxide-semiconductor (MOS) transistors. The resonant tank can include a first circuit connected between a first pair of inductors, a second circuit connected between a second pair of inductors, a third circuit connected between a third pair of inductors, and a fourth circuit connected between a fourth pair of inductors. Each of the third and fourth circuits can include a capacitor and a switching element. Each of the first and second pairs of circuits includes an inductor arranged in parallel with a respective switching element. Each of the third and fourth pairs of inductors can include an inductor common to the first pair of inductors and another inductor common to the second pair of inductors. The fourth pair of inductors can be different from the third pair of inductors.

Description

Background Technology

[0001] In wireless / wired terminals such as mobile phones or Wi-Fi devices, a digitally-controlled oscillator (DCO) is part of a phase-locked loop (PLL), which provides the local oscillator signal for radio frequency (RF) transmission and reception. Summary of the Invention

[0002] By operating with low phase noise and a wide frequency range, the components providing the local oscillator signal enable such terminals to communicate over a wide spectrum of cellular frequencies. However, current DCO designs typically cannot cover the entire cellular frequency spectrum with a single DCO having sufficiently low phase noise. Therefore, to support communication across the entire cellular frequency spectrum, many terminals use two or more DCOs for each PLL. The inductors of each DCO occupy a relatively large bare die area and must typically be spaced relatively far apart to reduce magnetic coupling effects, which increases the cost of the integrated circuit (IC).

[0003] The subject matter described in this specification can be implemented in specific embodiments to achieve one or more of the following advantages. The purpose of one or more systems and techniques disclosed herein is to increase the frequency range of the DCO to allow it to cover a sufficient range that the PLL does not require a second DCO to cover all cellular frequencies. In this way, such systems and techniques can save on scale and cost.

[0004] Generally, an innovative aspect of the subject matter described in this specification can be embodied in a digitally-controlled oscillator (DCO) that may include a resonant tank, which may include a plurality of inductors; a plurality of metal-oxide-semiconductor (MOS) transistors, wherein the terminals of each of the plurality of MOS transistors are coupled to the tap point of a respective inductor among the plurality of inductors; a first circuit connecting a first pair of inductors among the plurality of inductors, wherein the first circuit includes a first inductor arranged in parallel with a first switching element; and a second circuit connecting a second pair of inductors among the plurality of inductors, the second circuit including a first inductor arranged in parallel with a first switching element. A second inductor with two switching elements arranged in parallel; a third circuit connected between a third pair of inductors among the plurality of inductors, the third pair of inductors having one inductor shared with the first pair of inductors and another inductor shared with the second pair of inductors, wherein the third circuit includes a capacitor and a switching element; and a fourth circuit connected between a fourth pair of inductors among the plurality of inductors, the fourth pair of inductors having one inductor shared with the first pair of inductors and another inductor shared with the second pair of inductors, wherein the fourth circuit includes a capacitor and a switching element, wherein the fourth pair of inductors is different from the third pair of inductors.

[0005] The above and other embodiments may optionally include one or more features described herein, individually or in combination. Specifically, one embodiment includes a combination of all of the following features.

[0006] In some implementations, each of the multiple inductors has the same inductance.

[0007] In some implementations, the DCO may include control circuitry communicatively coupled to each of the first and second circuits, the control circuitry being used to control switching between the first and second circuits between a first mode and a second mode. In the first mode, both the first and second switching elements are open-circuited, and in the second mode, both the first and second switching elements are open-circuited.

[0008] In some implementations, in a first mode, the resonant slot can be used to generate a signal within a first frequency range; in a second mode, the resonant slot can be used to generate a signal within a second frequency range that is different from the first frequency range.

[0009] In some implementations, the control circuit may be communicatively coupled to each of the third and fourth circuits, such that in a first mode, the control circuit is used to selectively control the switching elements in the third circuit, the switching elements in the fourth circuit, or both, to tune the resonant slot to a specific frequency in a first frequency range; and in a second mode, the control circuit is used to selectively control the switching elements in the third circuit, the switching elements in the fourth circuit, or both, to tune the resonant slot to a specific frequency in a second frequency range.

[0010] In some implementations, each of the first inductor and the second inductor may have the same inductance, and the inductance of each of the first inductor and the second inductor may be different from the inductance of each of the plurality of inductors.

[0011] In some implementations, a resonant trench can be formed on a single semiconductor substrate.

[0012] In some implementations, each of the third and fourth circuits may include multiple capacitors and multiple switching elements.

[0013] In some implementations, the terminals of each of the plurality of MOS transistors may include a drain terminal.

[0014] In some implementations, the gate terminal of each of the plurality of MOS transistors can be coupled to a corresponding point among a plurality of points within the resonant trench.

[0015] In some implementations, the multiple points within the resonant slot may include (i) a point between the first pair of inductors and the third circuit, (ii) a point between the first pair of inductors and the fourth circuit, (iii) a point between the second pair of inductors and the third circuit, and (iv) a point between the second pair of inductors and the fourth circuit.

[0016] Detailed description of one or more embodiments of the subject matter is set forth in the accompanying drawings and detailed description. Other features, aspects, and advantages of the subject matter will become apparent from the detailed description and the accompanying drawings. Attached Figure Description

[0017] Figure 1 This is a block diagram of an example wireless communication system.

[0018] Figure 2 This is a block diagram of an example wireless device that can implement the methods and teachings of the present invention.

[0019] Figures 3A to 3B This is a schematic diagram of an example DCO.

[0020] Figure 4 It is shown that, according to some implementation methods, Figure 3BExample DCO layout.

[0021] Figure 5 It is shown that, according to some implementation methods, Figure 3B A schematic diagram of an example DCO.

[0022] Figure 6 The specifications table is shown.

[0023] Figure 7A Figures B to B show various curves of the inductance as a function of the DCO resonant frequency. Detailed Implementation

[0024] Figure 1 A block diagram of an example wireless communication system 100 is shown, including a wireless device 110 capable of communicating with one or more wireless communication networks. The one or more wireless communication networks that the wireless device 110 can communicate with may include, but are not limited to, one or more cellular or wireless wide area networks (WWANs), one or more wireless local area networks (WLANs), one or more wireless personal area networks (WPANs), or combinations thereof.

[0025] exist Figure 1 In the example, wireless device 110 is described as being able to communicate with at least one WWAN via at least one base station 120 and with at least one WLAN via at least one access point 130. At least one base station 120 may support bidirectional communication with wireless devices within its respective coverage area 122. Similarly, at least one access point 130 may support bidirectional communication with wireless devices within its respective coverage area 132.

[0026] In some implementations, at least one WWAN associated with at least one base station 120 may be a fifth-generation (5G) network among other generations and types of networks. In these implementations, at least one base station 120 may be a 5G base station that uses orthogonal frequency-division multiplexing (OFDM) and / or non-OFDM and a transmission time interval (TTI) of less than 1 millisecond (e.g., 100 or 200 microseconds) to communicate with wireless devices, such as wireless device 110. For example, at least one base station 120 may take one of several device forms, such as a base transceiver station (BTS), Node-B (NodeB), evolved NodeB (eNB), next-generation (fifth) generation (5G) NodeB (gNB), home NodeB, home eNodeB, site controller, access point, or wireless router, or a server, router, switch, or other processing entity with wired or wireless networks. Furthermore, as Figure 1 As shown, wireless device 110 is used to communicate with one or more personal area network (PAN) devices / systems 130 (e.g., via one or more WPANs) Or communication with radio frequency identification (RFID) systems and devices.

[0027] System 100 can use multi-channel access functionality, including a scheme in which at least one base station 120 and wireless device 110 are used to implement Long Term Evolution (LTE), LTE Advanced (LTE-A), and / or LTE Multimedia Broadcast Multicast Service (MBMS). In other embodiments, at least one base station 120 and wireless device 110 are used to implement UMTS, HSPA, or HSPA+ standards and protocols. Of course, other multiple access schemes and wireless protocols can also be used. Wireless device 110 may include similar features as described in the following reference. Figure 2 Describes one or more transmitters and receivers to support multiple communications with different types of access points, base stations and other wireless communication devices.

[0028] The following reference Figures 2 to 6Examples of transmitter components and RF power amplifiers that can be used in wireless device 110 and other similar devices are described in further detail. Although Figure 1 An example of a communication system is shown, but it is possible to... Figure 1 Various modifications can be made. For example, the communication system 100 can be configured in any suitable way, including any number of wireless devices, base stations, access points, networks, or other components.

[0029] Figure 2 This is a block diagram of an example wireless device 110 that can implement the methods and teachings according to the present invention. The wireless device 110 can be a mobile phone or other devices, such as a desktop computer, laptop computer, tablet computer, handheld computing device, automotive computing device, and / or other computing device. Figure 2 As shown, the wireless device 110 includes at least one transmitter 210, at least one receiver 220, at least one memory 230, at least one processor 240, and at least one input / output device 260. Only one transmitter and one receiver are shown here, but in many embodiments, multiple transmitters and receivers may be included to simultaneously support multiple communications of different types. Each transmitter may incorporate innovations of the present invention.

[0030] Processor 240 can perform various processing operations of wireless device 110. For example, processor 240 can perform signal encoding, data processing, power control, input / output processing, or any other function that enables wireless device 110 to operate in system 100. Figure 1 The processor 240 may include any suitable processing or computing device for performing one or more operations. For example, the processor 240 may include a microprocessor, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, or a combination of these devices.

[0031] Transmitter 210 is used to modulate data or other content for transmission by at least one antenna 250A. Before the baseband or intermediate frequency signal is provided to the power amplifier and antenna 250A for transmission, transmitter 210 can also be used to amplify, filter, and up-convert to a radio frequency (RF) signal. Transmitter 210 may include any suitable structure for generating signals for wireless transmission. References are provided below. Figure 2 The components 212 to 218 shown further describe other aspects of the transmitter 210 in detail.

[0032] Receiver 220 can be used to demodulate data or other content received by at least one antenna 250B. Receiver 220 can also be used to amplify, filter, and frequency-convert RF signals received through said antenna 250B. Receiver 220 can include any suitable structure for processing wirelessly received signals.

[0033] Each of antennas 250A and 250B may include any suitable structure for transmitting and / or receiving wireless signals. In some embodiments, antennas 250A and 250B may be implemented as a single antenna, which can be used to transmit and receive RF signals.

[0034] It should be understood that one or more transmitters 210 may be used for wireless device 110, one or more receivers 220 may be used for wireless device 110, and one or more antennas 250 may be used for wireless device 110. Although shown as separate blocks or components, at least one transmitter 210 and at least one receiver 220 may be combined to form a transceiver. Therefore, a single block of transceiver is shown instead of a single unit. Figure 2 The transmitter 210 and the receiver 220 are separate blocks.

[0035] In addition, the wireless device 110 includes one or more input / output devices 260. The input / output devices 260 facilitate interaction with the user. Each input / output device 260 includes any suitable structure for providing or receiving information from the user, such as a speaker, microphone, keypad, keyboard, display, or touchscreen.

[0036] In addition, the wireless device 110 includes at least one memory 230. The memory 230 is used to store instructions and data used, generated, or collected by the wireless device 110. For example, the memory 230 may store software or firmware instructions executed by one or more processors 240, as well as data for reducing or eliminating interference in the input signal. Each memory 230 includes any suitable one or more volatile and / or non-volatile storage and retrieval devices. Any suitable type of memory can be used, such as random access memory (RAM), read-only memory (ROM), hard disk, optical disk, subscriber identity module (SIM) card, memory stick, secure digital (SD) memory card, etc.

[0037] In some embodiments, transmitter 210 may include signal processing circuitry 212, modulation circuitry 214, power amplifier 216, and at least one filter 218. Signal processing circuitry 212 may include one or more circuits for processing signals received as input (e.g., from processor 240). For example, signal processing circuitry 212 may include a digital-to-analog converter (D / A) that converts digital input (e.g., from processor 240) into an analog RF signal, provides the RF signal to a low-pass filter, filters the RF signal using the low-pass filter, and provides the filtered RF signal to modulation circuitry 214.

[0038] In addition to receiving the filtered RF signal from the signal processing circuit 212, the modulation circuit 214 also receives a signal from the local oscillator 215 and modulates or adjusts the frequency of the output signal, for example, from a first frequency such as a baseband or intermediate frequency (IF) signal to a second frequency higher than the first frequency used to upconvert the output signal to RF, and when downconverting the input RF signal to an IF or baseband frequency signal, to a third frequency lower than the first frequency. Furthermore, as... Figure 2 As shown, transmitter 210 includes RF front-end 217, which includes amplification and filtering circuitry to filter and amplify the RF signal before it is supplied to power amplifier 216.

[0039] The RF signal generated from RF front-end 217 is amplified by power amplifier 216 and filtered by at least one filter 218 before being provided as the output of transmitter 210 to at least one antenna 250A for wireless transmission. In some examples, transmitter 210 may also include a preamplifier or other circuitry connecting modulation circuitry 214 to power amplifier 216. Although Figure 2Filter 218 is shown downstream of power amplifier 216, but in some embodiments, filter 218 can be upstream of power amplifier 216. In this case, the RF signal from RF front-end 217 is first filtered by at least one filter 218, then amplified by power amplifier 216, and then provided as the output of transmitter 210 to at least one antenna 250A for wireless transmission. In some embodiments, local oscillator 215 includes phase-locked loop (PLL) 219 and / or digitally-controlled oscillator (DCO) 213, similar to one or more described further below. In some examples, local oscillator 215 can also provide a signal to modulation (or demodulation) circuitry of receiver 220. In other examples, a separate local oscillator similar to or equivalent to local oscillator 215 can be used at receiver 220 to provide such a signal to modulation (or demodulation) circuitry of receiver 220. Therefore, in some embodiments, the local oscillator that provides the signal to the modulation (or demodulation) circuitry of receiver 220 includes PLL219 and / or DCO213, similar to one or more described in further detail below. However, other configurations are also possible.

[0040] As described above, one or more systems and techniques disclosed herein can increase the frequency range of a DCO to allow it to cover a sufficient range so that a PLL does not require a second DCO to cover all cellular frequencies. In this way, such systems and techniques can save on scale and cost. Examples of such systems and techniques are provided below.

[0041] In some implementations, to extend the range of the DCO, additional inductors are added to the inductor / capacitor (LC) resonator of the DCO. In some examples, variable inductor sizes are used to increase the range of the DCO to more than one octave, thus eliminating the need for two DCOs per PLL.

[0042] Figure 3A and 3B These are schematic diagrams of example DCOs 300A and 300B, respectively. DCOs 300B and 300A represent DCOs with and without the aforementioned additional inductance, respectively.

[0043] The DCO 300A may include a single-value inductor resonator and a capacitive digital-to-analog converter (CAPDAC) for frequency adjustment. The DCO 300B, on the other hand, may include a resonator with switchable inductor values ​​and the same CAPDAC. The additional inductance in the LC resonator of the DCO 300B provides two different LC resonator frequency ranges, giving it two operating bands. Based on the average geometric frequency of the DCO, the frequency range of the DCO 300A is 40.8%, and that of the DCO 300B is 75.8%, with the 70.7% range representing one octave.

[0044] The frequency range of the DCO 300A can be expressed as:

[0045]

[0046] Where L is the inductance of the resonator loop, C is the fixed capacitance of the CAPDAC, and ΔC is the variable capacitance of the CAPDAC.

[0047] DCO 300B is a resonant tank comprising multiple inductors 302. Each of the multiple inductors 302 may have the same inductance.

[0048] The DCO 300B also includes multiple metal-oxide-semiconductor (MOS) transistors 304, wherein a terminal 306 of each of the multiple MOS transistors is coupled to a tap 308 of a corresponding inductor among the multiple inductors. The terminal 306 of each of the multiple MOS transistors 304 coupled to the tap 308 of the corresponding inductor is a drain terminal. The tap reduces the voltage seen by the transistor 304 and allows for a higher resonator voltage to maintain signal power. The gate terminal 310 of each of the multiple MOS transistors can be coupled to a corresponding point among a plurality of points within the resonant trench.

[0049] The center point of the inductors in multiple inductors 302 is a virtual AC ground. Smaller process technology offers a higher drain-to-source voltage Vd. ds Higher gate breakdown voltage v gs and v gd This allows for a larger voltage swing than the power rail. Since the nonlinearity of the MOS transistor dominates at the output rather than the input, the gate voltage swing does not significantly affect the up-conversion flicker noise level. This allows the tap voltage at the inverter input to be larger than the tap voltage at the output.

[0050] The DCO 300B includes a first circuit connected between a first pair of inductors among a plurality of inductors 302. The first circuit includes a first inductor 312 arranged in parallel with a first switching element 314.

[0051] In addition, the DCO 300B also includes a second circuit connected between a second pair of inductors among the plurality of inductors 302. This second circuit includes a second inductor 316 arranged in parallel with the second switching element 318.

[0052] When at least one of switching elements 314 and / or 318 is open, a second inductor L2 is added in series to the primary inductor L1 (given by a plurality of inductors 302). The second inductor includes a first inductor 312 and / or a second inductor 316. Both inductors affect the resonant frequency ω. o The mutual inductance changes. Besides mutual inductance, any parasitic capacitance C in switching element 314 and / or switching element 318 changes. s Both will generate a parasitic resonant frequency and L2, which increases its additional inductance with increasing frequency. The second resonance generates high impedance in the resonator loop, reducing Q. The size of the switching element is designed to balance the increased resistance in the primary inductor loop when open-circuited and the parasitic resonant frequency when open-circuited.

[0053] The lower frequency range can be represented as:

[0054]

[0055] Where L1 is the first fixed inductor, L2 is the second switchable inductor, and C p ΔC is the parasitic capacitance of the switching element, C is the fixed capacitance of the CAPDAC, and ΔC is the variable capacitance of the CAPDAC.

[0056] For DCO 300B, when the inductor is short-circuited by circuit breaker element 314 and / or switching element 318, the Q of the primary inductance L1 decreases due to the switching resistor, and the higher frequency band range can be expressed as:

[0057]

[0058] Where L1 is the first fixed inductor (the inductance of multiple inductors 302), C is the fixed capacitor of CAPDAC, and ΔC is the variable capacitor of CAPDAC.

[0059] A single DCO 300B is not affected by magnetic coupling with adjacent DCOs. When adjacent DCOs are not in operation, the frequency of the DCO can be changed when two DCOs are needed to cover the entire cellular spectrum.

[0060] In addition, the DCO 300B includes a third circuit 320 connected between a third pair of inductors among the plurality of inductors 302. The third pair of inductors has one inductor shared with the first pair of inductors and another inductor shared with the second pair of inductors. The third circuit includes capacitors and switching elements.

[0061] Furthermore, the DCO 300B also includes a fourth circuit 322 connected between a fourth pair of inductors among the plurality of inductors 302. The fourth pair of inductors has one inductor shared with the first pair and another inductor shared with the second pair. The fourth circuit includes a capacitor and a switching element. In some embodiments, the fourth pair of inductors differs from the third pair of inductors.

[0062] The gate terminal 310 of each MOS transistor (in the plurality of MOS transistors 304) may be coupled to a plurality of points within the resonant trench, including (i) a point between the first pair of inductors and the third circuit, (ii) a point between the first pair of inductors and the fourth circuit, (iii) a point between the second pair of inductors and the third circuit, and (iv) a point between the second pair of inductors and the fourth circuit. The plurality of MOS transistors may be powered by an AGC circuit (not shown) or a simple voltage or current source. In some embodiments, the plurality of MOS transistors are “self-biased,” meaning a low input voltage generates a high output voltage, and vice versa. The gate terminal of each of the plurality of MOS transistors is connected to the drain (output) via an inductor, which stabilizes the input and output at a minimum supply voltage. In this implementation, a bias circuit may not be implemented.

[0063] In some implementations, the plurality of MOS transistors 304 may be two pairs of cross-coupled CMOS inverters 324. The inverters 324 are connected across the inductor to maintain capacitance matching. The inverters 324 are self-biased via the inductor's DC connection for low noise. The inputs are located on opposite sides of the inductor's main loop to ensure correct phase. The inverters 324 are placed close to their gate connections, and the outputs are radially across the center of the inductor's main loop to minimize inductive coupling. The outputs can be connected to any point on the inductor after a dummy ground to form a tap inductor.

[0064] Each of the third circuit 320 and the fourth circuit 322 may include multiple capacitors and multiple switching elements. For illustrative purposes, the switching elements shown are depicted as open circuits in the figures, but may be open or open circuits. Each of the third circuit 320 and the fourth circuit 322 may include multiple capacitors and multiple switching elements, such as the CAPDAC described above. The third circuit 320 and the fourth circuit 322 may include multiple weighted capacitors. For example, each of the third circuit 320 and the fourth circuit 322 may include a 5-bit coarse-tuning CAPDAC; however, a 5-bit fine-tuning CAPDAC may also be used or optionally. The capacitor rows in the CAPDAC consist of unit capacitor cells. Active pull-up and pull-down resistors are used for DC bias and optimal switching resistance.

[0065] The distributed nature of capacitance results in differential discontinuity (DD), meaning that if all capacitors are weighted equally due to the additional inductance in the CAPDAC connection, the digitally controlled capacitance at the resonant frequency will vary progressively. The further the capacitors are from the multiple inductors, the larger the effective capacitance. These multiple capacitors can be binary-weighted capacitors. Binary-weighted capacitors can be distributed to minimize DD.

[0066] Figure 4 It is shown that, according to some implementation methods, Figure 3B Example DCO layout 400. That is, in some embodiments, DCO 300B employs an inductor layout 400 including a main inductor loop and side inductor lobes. The side lobes are connected to the main inductor loop at a virtual alternating current (AC) ground in the LC resonator to minimize capacitive coupling to ground.

[0067] By replacing the two DCOs with a single DCO similar to or equivalent to the DCO 300B, an area reduction of approximately 50% can be achieved. Given that DCOs typically occupy a considerable amount of transceiver IC area, and that a single chip can have up to two TX PLLs and five RX PLLs, this area reduction translates into a significant reduction in IC size and cost.

[0068] Figure 5 This is a schematic diagram of an exemplary DCO 500, which in some embodiments may represent Figure 3B A detailed schematic diagram of an exemplary DCO300B.

[0069] DCO 500 includes a resonant trench, which in turn includes a first circuit 510, a second circuit 520, a third circuit 530, a fourth circuit 540, and a plurality of inductors 551A to 551D. In some embodiments, the resonant trench can be formed on a single semiconductor substrate. The first circuit 510 is connected between a first pair of inductors, such as inductors 551A and 551B, and includes a first inductor arranged in parallel with a first switching element. The second circuit 520 is connected between a second pair of inductors, such as inductors 551C and 551D, and includes a second inductor arranged in parallel with a second switching element. The third circuit 530 is connected between a third pair of inductors, such as inductors 551B and 551C, and includes a capacitor and a switching element. The third pair of inductors has one inductor shared with the first pair of inductors, such as inductor 551B, and another inductor shared with the second pair of inductors, such as inductor 551C. A fourth circuit 540 is connected between a fourth pair of inductors, such as inductors 551D and 551A, and includes a capacitor and a switching element. The fourth pair of inductors has one inductor shared with the first pair, such as inductor 551A, and another inductor shared with the second pair, such as inductor 551D. In some embodiments, each of one or both of the first and second circuits may include a parasitic capacitor C. p Parasitic resistor R p Or both.

[0070] In some embodiments, the DCO 500 also includes a control circuit 570 communicatively coupled to each of the first circuit 510 and the second circuit 520. The control circuit can be used to control the first circuit 510 and the second circuit 520 to switch between (i) a first mode in which both the first and second switching elements are open and (ii) a second mode in which both the first and second switching elements are closed. In some examples, the first and second modes can cause the resonant tank to generate signals within a first frequency range and a second frequency range, respectively. For example, the first mode may correspond to a frequency in the aforementioned low-frequency band where the resonant tank is tuned, and the second mode may correspond to a frequency in the aforementioned high-frequency band where the resonant tank is tuned. In some examples, the control circuit is used to uniformly control the first and second switching elements such that the first and second switching elements remain in the same state.

[0071] In the first mode, the control circuit can be used to selectively control the switching elements in the third circuit 530, the switching elements in the fourth circuit 540, or both, to tune the resonant slot to a specific frequency within the first frequency range, such as the aforementioned low-frequency band range. Similarly, in the second mode, the control circuit can be used to selectively control the switching elements in the third circuit 530, the switching elements in the fourth circuit 540, or both, to tune the resonant slot to a specific frequency within the second frequency range, such as the aforementioned high-frequency band range.

[0072] In some embodiments, inductors 551A through 551D all have the same inductance. For example, the inductance of each inductor 551A through 551D may be 1 / 2L1, where L1 is the first fixed inductance described above. Similarly, in some embodiments, the first and second inductors of the first circuit 510 and the second circuit 520 have the same inductance. For example, the inductance of each of the first and second inductors may be L2, where L2 is the second switchable inductor described above. Furthermore, the values ​​of L2 and 1 / 2L1 may be different.

[0073] Figure 6 The computer simulation results of the DCO resonant frequency under different operating conditions are displayed. When the CAPDAC has maximum capacitance and the inductor switch is open, the Fmin band 0 is the lowest operating frequency. When the CAPDAC has minimum capacitance and the inductor switch is open, the Fmax band 0 is the highest operating frequency. When the CAPDAC has maximum capacitance and the inductor switch is open, the Fmin band 1 is the lowest operating frequency. When the CAPDAC has minimum capacitance and the inductor switch is open, the Fmax band 1 is the highest operating frequency. The range is the total frequency range of the DCO relative to its geometric mean frequency. The NOMINAL, FFH_RCMIN, and FFC_RCMIN columns represent different component tolerance values ​​and temperatures. FF represents a fast CMOS transistor, SS represents a slow CMOS transistor, H represents a hot temperature, C represents a cold temperature, RCMIN represents the minimum tolerance capacitor and resistor, and RCMAX represents the maximum tolerance capacitor and resistor. For example, FFH_RCMIN is a device in which manufacturing tolerances bias the transistor to be faster than its nominal speed. This device operates at thermal temperatures, and manufacturing tolerances bias the capacitor to be smaller than its nominal size. The table shows how frequency range bias occurs when manufacturing tolerances affect IC manufacturing.

[0074] In some implementations, the simulated DCO resonant frequency range is 4.517 GHz to 10.469 GHz. The low-frequency band (switching elements open) is 4.517 GHz to 7.448 GHz, and the high-frequency band (switching elements open) ranges from 5.791 GHz to 10.469 GHz. For example, a final split can be achieved at 6.732 GHz. 79.4% of the overall tuning range and 22.3% overlap between the low-frequency and high-frequency bands can be achieved.

[0075] Figure 7A and 7B The graphs show the inductance as a function of the DCO resonant frequency. These graphs collectively reflect the parasitic components of the switch (e.g., the capacitor C discussed above) when the switch is open and closed. p and / or resistor R p The effect of the switch on the inductor. The yellow curve shows the effect of the switch in the ideal case without parasitic components, and the red curve shows the effect with one or more parasitic components.

[0076] Figure 7A The curves show the inductance and Q values ​​when the switch is open. The top left corner shows the relatively constant inductance (yellow) without parasitic components, but exhibits resonance (red peaks and valleys) when parasitic capacitance is present. The bottom left corner shows the inductor's quality factor Q, which increases with frequency without parasitic components (yellow), but decreases as the frequency approaches resonance if one or more parasitic components are present (red).

[0077] Figure 7B The curves show the inductance and Q values ​​when the switch is open. The upper right corner shows the inductance, which does not change significantly in the absence of parasitic components (yellow) or one or more parasitic components (red). The lower right corner shows how the inductor Q decreases with and without parasitic resistance (yellow).

[0078] While this specification includes numerous specific implementation details, these details should not be construed as limiting the scope of any invention or the scope of the claimed protection, but rather as descriptions of features that may be characteristic of a particular embodiment of a particular invention. In the context of a single embodiment, certain features described herein may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually in multiple embodiments or in any suitable sub-combination. Furthermore, although features may be described above as acting in certain combinations, or even initially claimed, in some cases one or more features from the claimed combination may be removed from that combination, and the claimed combination may be for sub-combinations or variations thereof.

[0079] Similarly, although the accompanying drawings depict operations in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or sequentially, or requiring the execution of all the operations shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments. It should be understood that the described program components and systems can generally be integrated together into a single software product or packaged into multiple software products.

[0080] Furthermore, without departing from the scope of the invention, the technologies, systems, subsystems, and methods described and illustrated as discrete or separate in the various embodiments can be combined or integrated with other systems, modules, technologies, or methods. Other items shown or described as coupled to each other, or directly coupled, or communicating with each other, may be indirectly coupled or communicated through some interface, device, or intermediate component, electrically, mechanically, or otherwise. Other examples of variations, substitutions, and modifications can be determined by those skilled in the art and may be exemplified without departing from the spirit and scope disclosed herein.

[0081] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., through one or more other components). In some cases, when an element is said to be connected or coupled to another element, that element may be directly connected to the other element or indirectly connected to the other element through an intermediate element. When an element is said to be directly connected to another element, there is no intermediate element between that element and the other element. If two devices are directly or indirectly connected so that they can transmit electronic signals between them, then the two devices are in "communication".

[0082] Specific embodiments of this subject matter have been described. For example, the operations described in the embodiments can be performed in different orders and still achieve the desired results. For example, the processes depicted in the figures do not necessarily require execution in the specific order shown to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. A numerically controlled oscillator, comprising: The resonant groove includes: Multiple inductors; A plurality of metal-oxide-semiconductor transistors, wherein a terminal of each of the plurality of metal-oxide-semiconductor transistors is coupled to a tap of a corresponding inductor among the plurality of inductors; A first circuit is connected between a first pair of inductors in the plurality of inductors, wherein the first circuit includes a first inductor arranged in parallel with a first controllable switching element; A second circuit is connected between a second pair of inductors in the plurality of inductors, wherein the second circuit includes a second inductor arranged in parallel with a second controllable switching element; A third circuit is connected between a third pair of inductors in the plurality of inductors, the third pair of inductors having one inductor shared with the first pair of inductors and another inductor shared with the second pair of inductors, wherein the third circuit includes a capacitor and a switching element; A fourth circuit is connected between a fourth pair of inductors in the plurality of inductors, the fourth pair of inductors having one inductor shared with the first pair of inductors and another inductor shared with the second pair of inductors, wherein the fourth circuit includes a capacitor and a switching element, and wherein the fourth pair of inductors is different from the third pair of inductors.

2. The numerically controlled oscillator according to claim 1, wherein, Each of the plurality of inductors has the same inductance.

3. The numerically controlled oscillator according to claim 1, further comprising: A control circuit is communicatively coupled to each of the first and second circuits, the control circuit being used to control the switching of the first and second circuits between a first mode and a second mode, wherein: In the first mode, both the first and second switching elements are open-circuited; In the second mode, both the first and second switching elements are open-circuited.

4. The numerically controlled oscillator according to claim 3, wherein: In the first mode, the resonant groove is used to generate a signal within a first frequency range; In the second mode, the resonant groove is used to generate a signal in a second frequency range that is different from the first frequency range.

5. The numerically controlled oscillator according to claim 4, wherein the control circuit is communicatively coupled to each of the third circuit and the fourth circuit, wherein: In the first mode, the control circuit is used to selectively control the switching elements in the third circuit, the switching elements in the fourth circuit, or both, to tune the resonant slot to a specific frequency in the first frequency range. In the second mode, the control circuit is used to selectively control the switching elements in the third circuit, the switching elements in the fourth circuit, or both, to tune the resonant slot to a specific frequency within the second frequency range.

6. The numerically controlled oscillator according to any one of claims 1 to 5, wherein, Each of the first inductor and the second inductor has the same inductance, but the inductance of each of the first inductor and the second inductor is different from the inductance of each of the plurality of inductors.

7. The numerically controlled oscillator according to any one of claims 1 to 5, wherein, The resonant groove is formed on a single semiconductor substrate.

8. The numerically controlled oscillator according to any one of claims 1 to 5, wherein, Each of the third and fourth circuits includes multiple capacitors and multiple switching elements.

9. The numerically controlled oscillator according to any one of claims 1 to 5, wherein, Each of the plurality of metal-oxide-semiconductor transistors includes a drain terminal at its terminals.

10. The numerically controlled oscillator according to any one of claims 1 to 5, wherein, The gate terminal of each of the plurality of metal-oxide-semiconductor transistors is coupled to a corresponding point among the plurality of points within the resonant trench.

11. The numerically controlled oscillator according to claim 10, wherein, The multiple points within the resonant slot include (i) the point between the first pair of inductors and the third circuit, (ii) the point between the first pair of inductors and the fourth circuit, (iii) the point between the second pair of inductors and the third circuit, and (iv) the point between the second pair of inductors and the fourth circuit.

12. A wireless device, comprising: At least one processor; antenna; A communication circuit coupled to the at least one processor and the antenna, wherein the communication circuit includes a local oscillator, the local oscillator including a numerically controlled oscillator according to any one of claims 1 to 11.

13. The wireless device according to claim 12, wherein, The local oscillator is a phase-locked loop.

14. The wireless device according to claim 12 or 13, wherein, The communication circuit includes a transmitter, a receiver, or both.

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