Display panel and manufacturing method thereof, and display device

Abstract

A display panel (1100) comprises a substrate (100), a first flat layer (270), a conductive pattern layer (250), a second flat layer (280) and an anode conductive layer (310). The first flat layer (270) is arranged on one side of the substrate (100), and a plurality of first grooves (271) are provided on the side of the first flat layer (270) away from the substrate (100). The conductive pattern layer (250) is arranged on the side of the first flat layer (270) away from the substrate (100), and comprises a plurality of conductive patterns (251), parts of the plurality of conductive patterns (251) are located in the plurality of first grooves (271), and parts of the plurality of conductive patterns (251) located in the first grooves (271) are away from the surface of the substrate (100) and are substantially flush with the surface of the first flat layer (270) away from the substrate (100). The second flat layer (280) is arranged on the side of the conductive pattern layer (250) away from the substrate (100). The anode conductive layer (310) is arranged on a side of the second flat layer (280) away from the substrate (100), and comprises a plurality of anodes, wherein a vertical projection of the anode on the substrate (100) overlaps a vertical projection of at least one first groove (271) on the substrate (100).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) display panels have the advantages of active luminescence, wide viewing angle, high contrast, fast response speed, low power consumption, and ultra-lightness, and therefore have attracted widespread attention. Summary of the invention

[0003] On the one hand, a display panel is provided. The display panel includes a substrate, a first flat layer, a conductive pattern layer, a second flat layer and an anode conductive layer. The first flat layer is arranged on one side of the substrate, and a plurality of first grooves are provided on the side of the first flat layer away from the substrate. The conductive pattern layer is arranged on the side of the first flat layer away from the substrate, and includes a plurality of conductive patterns. At least part of the plurality of conductive patterns is located in the plurality of first grooves, and the part of the plurality of conductive patterns located in the first grooves is away from the surface of the substrate and is substantially flush with the surface of the first flat layer away from the substrate. The second flat layer is arranged on the side of the conductive pattern layer away from the substrate. The anode conductive layer is arranged on the side of the second flat layer away from the substrate, and includes a plurality of anodes, and the vertical projection of the anode on the substrate overlaps with the vertical projection of at least one first groove on the substrate.

[0004] In some embodiments, the display panel is provided with a plurality of thin film transistors. The display panel further comprises a source-drain conductive layer. The source-drain conductive layer is provided between the substrate and the first planar layer, and comprises at least a plurality of voltage signal lines, a plurality of data signal lines, and one of the source-drain electrode patterns of the thin film transistor. The plurality of conductive patterns comprises a plurality of signal lines, and at least a portion of the plurality of signal lines is located in at least one of the first grooves.

[0005] In some embodiments, the signal line has the same line width at each location; and along the extension direction of the signal line, the vertical projection of the first groove on the substrate passes through the vertical projection of the anode on the substrate.

[0006] In some embodiments, the display panel further comprises a pixel defining layer, the pixel defining layer is disposed on a side of the anode layer away from the substrate, and the pixel defining layer is provided with a plurality of first openings. The anode comprises a main body, and a vertical projection of one of the first openings on the substrate is located within a range of a vertical projection of one of the main bodies on the substrate. The vertical projection of the main body of the anode on the substrate is located within a range of a vertical projection of the first groove on the substrate.

[0007] In some embodiments, the first groove is a frame-shaped groove connected end to end, and the line width of the portion of the signal line located in the first groove is smaller than the line width of the remaining portion of the signal line.

[0008] In some embodiments, the display panel further comprises a pixel defining layer, the pixel defining layer being disposed on a side of the anode layer away from the substrate, the pixel defining layer having a plurality of first openings. The anode comprises a main body, a vertical projection of one first opening on the substrate being located within a range of a vertical projection of the main body on the substrate. An outer boundary of a vertical projection of one first groove on the substrate coincides with a boundary of a vertical projection of one main body on the substrate.

[0009] In some embodiments, a surface of the first flat layer away from the substrate is further provided with a plurality of second grooves, one second groove is located between two adjacent first grooves and connects the two adjacent first grooves. A portion of the same signal line located between two adjacent first grooves is located in one second groove, and a surface of the portion of the signal line located in the second groove away from the substrate is substantially flush with a surface of the first flat layer away from the substrate.

[0010] In some embodiments, the plurality of signal lines include at least one of a plurality of auxiliary data signal lines and a plurality of auxiliary voltage signal lines.

[0011] In some embodiments, the voltage signal line extends along a first direction, and the plurality of voltage signal lines are arranged at intervals along a second direction. The plurality of signal lines include a plurality of auxiliary voltage signal lines, and the plurality of auxiliary voltage signal lines are electrically connected to the plurality of voltage signal lines. The plurality of auxiliary voltage signal lines include a plurality of first auxiliary voltage signal lines and a plurality of second auxiliary voltage signal lines. The first auxiliary voltage signal line extends along the first direction, and the plurality of first auxiliary voltage signal lines are arranged at intervals along the second direction. The first flat layer also includes a plurality of first vias, an auxiliary voltage signal line is opposite to a voltage signal line, and the first auxiliary voltage signal line is electrically connected to the voltage signal line opposite thereto through at least one of the first vias. The second auxiliary voltage signal line extends along the second direction, and the plurality of second auxiliary voltage signal lines are arranged at intervals along the first direction; the plurality of second auxiliary voltage signal lines are configured to electrically connect the plurality of first auxiliary voltage signal lines.

[0012] In some embodiments, the display panel further includes a color filter layer, which is disposed on a side of the anode conductive layer away from the substrate and includes a plurality of filter portions disposed at intervals. A plurality of third grooves are also provided on the surface of the first flat layer away from the substrate, and the vertical projection of the third grooves on the substrate overlaps with the vertical projection of the filter portion on the substrate. The conductive pattern layer further includes a plurality of adapter blocks, and one adapter block is configured to electrically connect one of the anodes to a source-drain electrode pattern of a thin film transistor. At least a portion of the adapter block is located in at least one of the third grooves, and the portion of the adapter block located in the third groove is away from the surface of the substrate and is substantially flush with the surface of the first flat layer away from the substrate.

[0013] In some embodiments, the adapter block includes a first part, a vertical projection of the first part of the adapter block on the substrate is located within the range of a vertical projection of the filter part on the substrate, and the first part of the adapter block is located in one of the third grooves.

[0014] In some embodiments, an adapter block is located in one of the third grooves.

[0015] In some embodiments, when the anode includes a main body, the anode also includes a connection portion connected to the main body; a plurality of third via holes are provided in the second flat layer, and the connection portion is electrically connected to one of the adapter blocks through at least one of the third via holes. A plurality of second via holes are provided in the first flat layer, and the adapter block is electrically connected to one of the source-drain electrode patterns through at least one of the second via holes.

[0016] In some embodiments, the third groove has a depth of 0.6 μm to 0.7 μm.

[0017] In some embodiments, the thickness of the first planar layer is 1.5 μm to 3.0 μm, and the depth of the first groove is 0.6 μm to 0.7 μm.

[0018] In some embodiments, the display panel is provided with a plurality of thin film transistors, and the plurality of conductive patterns at least include a plurality of voltage signal lines, a plurality of data signal lines, and one of the source and drain electrode patterns of the thin film transistors.

[0019] The plurality of source-drain electrode patterns of the plurality of thin film transistors include a first source-drain electrode pattern, a vertical projection of the first source-drain electrode pattern on the substrate overlaps with a vertical projection of the anode on the substrate. The first source-drain electrode pattern includes a second portion, a vertical projection of the second portion on the substrate is located within the range of a vertical projection of the anode on the substrate, and one second portion is located in one of the first grooves.

[0020] In some embodiments, the first source-drain electrode pattern also includes a third portion, a vertical projection of the third portion on the substrate is outside the range of the vertical projection of the anode on the substrate; the second portion and the third portion of the same first source-drain electrode pattern are located in one of the first grooves.

[0021] In some embodiments, an overlapping portion of a vertical projection of at least one of the plurality of voltage signal lines and the plurality of data signal lines on the substrate and a vertical projection of one of the anodes on the substrate is located within one of the first grooves.

[0022] In some embodiments, at least one of the plurality of voltage signal lines and the plurality of data signal lines is located in one of the first grooves.

[0023] In some embodiments, the display panel further includes a semiconductor layer, a first gate conductive layer, and a second gate conductive layer. The semiconductor layer is disposed between the substrate and the first planar layer, and includes an active layer pattern of the thin film transistor. The first gate conductive layer is disposed between the semiconductor layer and the first planar layer, and includes a gate pattern of the thin film transistor. The second gate conductive layer is disposed between the first gate conductive layer and the first planar layer; a capacitor is formed between a portion of the second gate conductive layer and a portion of the first gate conductive layer. A side of the first planar layer close to the substrate is in direct contact with the second gate conductive layer.

[0024] In some embodiments, a material of the first planar layer includes an organic material.

[0025] In another aspect, a display device is provided, comprising: a display panel as described in any one of the above embodiments.

[0026] On the other hand, a method for manufacturing a display panel is provided, comprising: manufacturing an insulating material film on one side of a substrate; manufacturing a plurality of first grooves on the insulating material film to form a first flat layer; manufacturing a conductive pattern layer on a side of the first flat layer away from the substrate; manufacturing a second flat layer on a side of the conductive pattern layer away from the substrate; and manufacturing an anode conductive layer on a side of the second flat layer away from the substrate. The conductive pattern layer comprises a plurality of conductive patterns, at least part of the plurality of conductive patterns is located in at least one of the first grooves, and the thickness of the conductive pattern is equal to the depth of the first groove. The anode conductive layer comprises a plurality of anodes, and the vertical projection of one anode on the substrate overlaps with the vertical projection of at least one of the first grooves on the substrate.

[0027] In some embodiments, the plurality of conductive patterns include a plurality of auxiliary voltage signal lines and a plurality of transfer blocks. Before the insulating material film is formed on one side of the substrate, the method further includes: forming a source-drain conductive layer on the substrate. The source-drain conductive layer includes at least one of a plurality of voltage signal lines, a plurality of data signal lines, and a source-drain electrode pattern of a thin film transistor.

[0028] While making a plurality of first grooves on the insulating material film, the method further includes: making a plurality of first vias and a plurality of second vias on the insulating material film. A first via exposes a portion of a voltage signal line at one end close to the substrate, and a portion of an auxiliary voltage signal line is located in at least one first via and electrically connected to a voltage signal line. A second via exposes a portion of a source-drain electrode pattern at one end close to the substrate, and a portion of a transfer block is located in at least one third via and electrically connected to a display circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0030] Figure 1 is a schematic diagram of a display device according to some embodiments;

[0031] Figure 2A For along Figure 1 A sectional view with the center section line AA;

[0032] Figure 2B For along Figure 1 Another section view of the middle section line AA;

[0033] Figure 3 for Figure 1 A partial enlarged view of middle B;

[0034] Figure 4 for Figure 3 A partial enlarged view of C1 in the middle;

[0035] Figure 5 for Figure 4 A cross-sectional view along section line E1-E1;

[0036] Figure 6 for Figure 3Another partial enlarged view of C1;

[0037] Figure 7 for Figure 6 A cross-sectional view along section line E2-E2;

[0038] Figure 8 for Figure 3 A partial enlarged view of C2 in the middle;

[0039] Fig. 9 for Figure 8 A cross-sectional view along section line F1-F1;

[0040] Fig.10 for Figure 3 Another partial enlarged view of C2 in the middle;

[0041] Fig.11 for Fig.10 A cross-sectional view along section line F2-F2;

[0042] Fig.12 for Figure 3 A cross-sectional view along section line DD;

[0043] Fig.13 for Figure 1 Another partial enlarged view of B;

[0044] Fig.14A for Fig.13 A cross-sectional view along section line GG;

[0045] Fig. 14B for Fig.13 Another cross-sectional view along section line GG;

[0046] Fig.15A for Fig.13 A cross-sectional view along section line HH;

[0047] Fig. 15B for Fig.13 Another cross-sectional view along section line HH;

[0048] Fig.16 is a schematic diagram of steps for manufacturing a display panel according to some embodiments. DETAILED DESCRIPTION

[0049] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0050] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0051] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0052] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0053] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0054] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0055] As used herein, "substantially" or "approximately" includes the stated values ​​and averages that are within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0056] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0057] In this article, "the vertical projection of A overlaps with the vertical projection of B" includes "the vertical projection of A completely overlaps with the vertical projection of B" and "the vertical projection of A partially overlaps with the vertical projection of B". "The vertical projection of A completely overlaps with the vertical projection of B" means: the boundary of the vertical projection of A roughly coincides with the boundary of the vertical projection of B. "The vertical projection of A partially overlaps with the vertical projection of B" means: the vertical projection of A partially overlaps with the vertical projection of B, and partly separates from each other; or, the boundary of the vertical projection of A is within the boundary of the vertical projection of B; or, the boundary of the vertical projection of B is within the boundary of the vertical projection of A.

[0058] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0059] Some embodiments of the present disclosure provide a display device 1000, referring to Figure 1 , Figure 11 is a structural diagram of a display device; the display device 1000 can be a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, or any other product or component with a display function.

[0060] The display device 1000 may be an electroluminescent display device or a photoluminescent display device. When the display device 1000 is an electroluminescent display device, the electroluminescent display device may be an organic electroluminescent display device or a quantum dot electroluminescent (QLED) display device. When the display device 1000 is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0061] The display device 1000 includes a display panel 1100. Figure 2A , Figure 2A for Figure 1 A cross-sectional view of the display panel 1100 along the section line AA; the display panel 1100 includes a pixel circuit layer 200, a light emitting device 300 and an encapsulation layer 400 stacked on a substrate 100.

[0062] The substrate 100 may be a flexible substrate, such as a substrate 100 made of resin, so that the display panel 1100 may be a flexible display panel (capable of being bent or folded). Alternatively, the substrate 100 may be a rigid substrate, such as a glass substrate, so that the display panel 1100 may be a rigid display panel (not capable of being bent or folded).

[0063] The substrate 100 may be a composite film structure in which a multi-layer film structure is stacked. For example, the substrate 100 is a rigid substrate. Figure 2A , the substrate 100 includes a glass base 110 , a resin layer 120 , and a buffer layer 130 which are stacked.

[0064] The pixel circuit layer 200 refers to a film layer where a plurality of pixel circuit arrays are located. Each pixel circuit in the pixel circuit layer 200 is configured to control a light emitting device 300 electrically connected to the pixel circuit to emit light. The pixel circuit may include a plurality of switch devices and at least one capacitor Cst.

[0065] Exemplarily, the switch device may be a thin film transistor (Thin Film Transistor, referred to as TFT) or a field effect transistor (metal oxide semiconductor, referred to as MOS). In the embodiment of the present disclosure, the switch device is described as a thin film transistor, that is, the pixel circuit includes a plurality of thin film transistors ( Figure 2A Only one thin film transistor electrically connected to the light emitting device 300 is shown as an example. The thin film transistor may be a P-type transistor or an N-type transistor. The P-type transistor is turned on under a low potential and is turned off under a high potential. The N-type transistor is turned on under a high potential and is turned off under a low potential.

[0066] The pixel circuit layer 200 includes a plurality of patterned conductive layers stacked together. The structure of the patterned conductive layer is described below by way of example.

[0067] In some embodiments of the present disclosure, the plurality of patterned conductive layers include a stacked arrangement of Figure 2A The active layer 210, the first gate conductive layer 220, the second gate conductive layer 230, the source-drain conductive layer 240 and the conductive pattern layer 250 are shown. In this case, the thin film transistor includes an active layer pattern 11 located in the active layer 210, a gate pattern 12 located in the first gate conductive layer 220, and a source electrode 13 and a drain electrode 14 located in the source-drain conductive layer 240. The capacitor Cst includes a first electrode plate 15 located in the first gate conductive layer 220 and a second electrode plate 16 located in the second gate conductive layer 230.

[0068] Alternatively, in some other embodiments of the present disclosure, the plurality of patterned conductive layers include a stacked arrangement of Figure 2B The active layer 210, the first gate conductive layer 220, the second gate conductive layer 230 and the conductive pattern layer 250 are shown. In this case, the thin film transistor includes an active layer pattern 11 located in the active layer 210, a gate pattern 12 located in the first gate conductive layer 220, and a source electrode 13 and a drain electrode 14 located in the conductive pattern layer 250. The capacitor Cst includes a first electrode plate 15 located in the first gate conductive layer 220 and a second electrode plate 16 located in the second gate conductive layer 230.

[0069] In the embodiment of the present disclosure, among the multiple patterned conductive layers, the patterned conductive layer farthest from the substrate 100 is the conductive pattern layer 250. Thus, in different embodiments, the conductive pattern layer 250 may refer to different film layers.

[0070] For example, in Figure 2AIn the embodiment shown, the source-drain conductive layer 240 is configured to arrange the signal line of the pixel circuit and the source-drain pattern of the thin film transistor, and the conductive pattern layer 250 is configured to arrange the auxiliary signal line of the pixel circuit, and the auxiliary signal line is configured to be electrically connected to the signal line, thereby connecting the auxiliary signal line in parallel with the signal line to reduce the resistance of the signal line. Figure 2B In the illustrated embodiment, the conductive pattern layer 250 is configured to arrange wiring of the pixel circuit and source and drain patterns of the thin film transistor.

[0071] The pixel circuit layer 200 also includes an insulating layer disposed between two adjacent patterned conductive layers, and two flat layers located on both sides of the conductive pattern layer 250 (on opposite sides along the thickness direction of the conductive pattern layer 250). The material of the insulating layer includes an inorganic material. During the manufacturing process of the display panel, the insulating layer can be manufactured by vapor deposition. The thickness of the insulating layer thus formed is roughly uniform, and its surface rises and falls with the rise and fall of the surface of the substrate on which it is located. The material of the flat layer includes an organic material. During the manufacturing process of the display panel, the flat layer can be manufactured by a coating process, thereby forming a flat layer with a roughly flat surface. Among them, the organic material of the flat layer is also an electrically insulating material. In this way, the flat layer located on the side of the conductive pattern layer 250 close to the substrate 100 can be reused as an insulating layer between the conductive pattern layer 250 and the patterned conductive layer adjacent to the conductive pattern layer 250, which is conducive to reducing the number of film layers of the display panel 100 and making the display panel 1100 thinner.

[0072] Since each patterned conductive layer is provided with a different conductive pattern, and the insulating layer is usually a film layer structure with uniform thickness, the surface of the film layer close to the flat layer in the pixel circuit layer 200 has undulations (unevenness).

[0073] During the manufacturing process of the display panel 1100, the flat layer is manufactured by a coating process. Due to the viscosity of the material of the flat layer, the surface of the flat layer away from the substrate 100 has fluctuations along with the fluctuations of the surface of the base on which it is located. Among them, the fluctuation degree of the flat layer is smaller than the fluctuation degree of the surface of the base on which it is located. The base surface where the flat layer is located refers to: a surface located on the side of the flat layer close to the substrate and in direct contact with the flat layer.

[0074] For example, see Figure 2AIn the case where the plurality of patterned conductive layers include an active layer 210, a first gate conductive layer 220, a second gate conductive layer 230, a source-drain conductive layer 240 and a conductive pattern layer 250 that are stacked, the pixel circuit layer 200 further includes a first gate insulating layer 261 between the active layer 210 and the first gate conductive layer 220, a second gate insulating layer 262 between the first gate conductive layer 220 and the second gate conductive layer 230, an interlayer dielectric layer 263 between the second gate conductive layer 230 and the source-drain conductive layer 240, a first planarizing layer 270 between the source-drain conductive layer 240 and the conductive pattern layer 250, and a second planarizing layer 280 located on the side of the conductive pattern layer 250 away from the substrate 100.

[0075] In this way, the first planar layer 270 is away from the surface of the substrate 100, and rises and falls with the rise and fall of the surface formed by the interlayer dielectric layer 263 and the source-drain conductive layer 240 away from the substrate 100. The second planar layer 280 is away from the surface of the substrate 100, and rises and falls with the rise and fall of the surface formed by the first planar layer 270 and the conductive pattern layer 250 away from the substrate 100.

[0076] For example, see Figure 2B In the case where the plurality of patterned conductive layers include an active layer 210, a first gate conductive layer 220, a second gate conductive layer 230 and a conductive pattern layer 250 that are stacked, the pixel circuit layer 200 further includes a first gate insulating layer 261 between the active layer 210 and the first gate conductive layer 220, a second gate insulating layer 262 between the first gate conductive layer 220 and the second gate conductive layer 230, a first planarizing layer 270 between the second gate conductive layer 230 and the conductive pattern layer 250, and a second planarizing layer 280 on the side of the conductive pattern layer 250 away from the substrate 100.

[0077] In this way, the first planar layer 270 is away from the surface of the substrate 100, and rises and falls with the rise and fall of the surface formed by the second gate insulating layer 262 and the second gate conductive layer 230 away from the substrate 100. The second planar layer 280 is away from the surface of the substrate 100, and rises and falls with the rise and fall of the surface formed by the first planar layer 270 and the conductive pattern layer 250 away from the substrate 100.

[0078] The light emitting device 300 is disposed on a side of the pixel circuit layer 200 away from the substrate 100. In some embodiments, the light emitting device 300 includes an anode layer 310, a pixel defining layer 320, a light emitting function layer 330, and a cathode layer 340 which are stacked.

[0079] The anode layer 310 includes a plurality of mutually separated anodes 31 ( Figure 2AOnly one anode 31 is shown exemplarily. The pixel defining layer 320 has a plurality of first openings 32, each of which is opposite to an anode 31, and the boundary of the first opening 32 is located within the boundary of the anode 31 opposite to it, and each first opening 32 defines an effective light-emitting area of ​​a sub-pixel. At least a portion of the light-emitting functional layer 330 is located within the first opening 32. The cathode layer 340 is located on the side of the light-emitting functional layer 133 away from the substrate 100. Exemplarily, the cathode layer 340 can be a whole film structure.

[0080] In some embodiments, the light-emitting functional layer 330 includes a light-emitting layer. In other embodiments, the light-emitting functional layer 330 includes, in addition to the light-emitting layer, at least one of an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL).

[0081] During the manufacturing process of the display panel 1100 , the anode layer 310 is manufactured by a sputtering process, so that the thickness of the formed anode 31 is uniform. Based on this, the surface of the anode 31 away from the substrate 100 fluctuates with the fluctuation of the surface of the base on which it is located.

[0082] Exemplarily, the anode layer 320 is directly disposed on the surface of the second flat layer 280, and the anode 31 included in the anode layer 320 has fluctuations as the surface of the region where the anode 31 is located on the second flat layer 280 changes. That is, when the surface of the region on the second flat layer 280 configured to be provided with the anode 31 changes, the anode 31 located in the region also has fluctuations adapted to the above fluctuations; when the surface of the region on the second flat layer 280 configured to be provided with the anode 31 is a flat surface, the anode 31 located in the region is also flat.

[0083] The encapsulation layer 400 may be an encapsulation film or an encapsulation substrate, which is not specifically limited in the embodiments of the present disclosure.

[0084] In some embodiments, the display panel 1100 further includes a color filter layer 500 disposed on a side of the encapsulation layer 400 away from the substrate 100. The color filter layer 500 includes a black matrix 510 and a plurality of filter portions 520. The black matrix 510 has a plurality of second openings 511, and at least a portion of a filter portion 520 is located in a second opening 511.

[0085] A first opening 32 is opposite to a second opening 511, and the boundary of the vertical projection of the first opening 32 on the substrate 100 is located within the boundary of the vertical projection of the second opening 511 on the substrate 100 opposite to it; so that the light emitted by a light-emitting device 300 can pass through the filter part 520 of an opening 511 and be emitted.

[0086] The filter portion 520 is configured to color the light emitted from the light emitting device 300. For example, the filter portion 520 may include a red filter portion 520, a green filter portion 520, and a blue filter portion 520.

[0087] The black matrix 510 of the color film layer 500 can weaken the reflection of ambient light by the display panel 1100. Based on this, compared with weakening the reflection of ambient light by the display panel 1100 by setting a polarizer, when the display panel 1100 includes the color film layer 500, the display device 1000 can reduce one polarizer, making the display device 1000 thinner and lighter, while reducing the production cost of the display device 1000.

[0088] In the related art, in the pixel circuit layer, the surface of the film layer close to the flat layer away from the substrate has an undulating change, resulting in an undulating change in the surface of the flat layer away from the substrate. The anode layer is directly arranged on the flat layer, so that the surface of the anode contained in the anode layer may also have an undulating change. In addition, the display panel replaces the polarizer with a color filter layer to achieve the function of reducing the reflection of ambient light, so that the ambient light incident on the anode layer can be emitted from the opening of the black matrix through the filter part after being reflected by the anode layer. Since the surface of the anode layer has an undulating change, the light reflected by the anode layer will undergo a color separation phenomenon, that is, the light reflected by the anode layer will form a color halo. And the greater the undulation of the anode layer (the worse the flatness), the more serious the color separation phenomenon of the light reflected by the anode layer, and the more obvious the color halo generated. After the above-mentioned color-separated light is emitted by the filter part, a color halo can be formed on the light-emitting surface of the display panel, especially when the display panel is in a dark state (no image information is displayed), the color halo formed on the display panel is more obvious, and the color halo is easy to cause dazzle.

[0089] Some embodiments of the present disclosure provide a display panel 1100, referring to Figure 2A and Figure 2B A first planar layer 270 is provided with a plurality of first grooves 271 (where Figure 2A and Figure 2BOnly one first groove 271 is shown exemplarily. The depth of the first groove 271 is less than the thickness of the first flat layer 270, so that the first groove 271 has a bottom wall substantially parallel to the substrate 100, thereby preventing the patterned conductive layers on both sides of the first flat layer 270 from being electrically connected through the first groove 271. The depth of the first groove 271 refers to: the first groove 271 is perpendicular to the substrate 100 ( Figure 2A The thickness of the first planar layer 270 refers to the size of the first planar layer 270 along a direction perpendicular to the substrate 100.

[0090] The vertical projection of the anode 31 on the substrate 100 overlaps with the vertical projection of at least one first groove 271 on the substrate 100. Exemplarily, the vertical projection of one anode 31 on the substrate 100 overlaps with the vertical projection of one first groove 271 on the substrate 100.

[0091] It should be noted that the vertical projection of the first groove 271 on the substrate 100 overlaps with the vertical projection of the anode 31 on the substrate, including that the vertical projections of the two (the first groove 271 and the anode 31) on the substrate 100 completely overlap, and that the vertical projections of the two on the substrate 100 partially overlap.

[0092] The vertical projections of the two on the substrate 100 completely overlap, which means that the boundaries of the vertical projections of the two on the substrate 100 roughly overlap. The vertical projections of the two on the substrate 100 partially overlap, which means that the vertical projections of the two on the substrate 100 partially overlap each other and partially separate from each other (do not overlap); or, the boundary of the vertical projection of one of the two on the substrate 100 is located within the boundary of the vertical projection of the other on the substrate 100, and the boundaries of the vertical projections of the two on the substrate 100 at least partially do not overlap.

[0093] The conductive pattern layer 250 is located between the first flat layer 270 and the second flat layer 280, and includes a plurality of conductive patterns 251. At least part of the plurality of conductive patterns 251 is located in the first groove 271, so that each first groove 271 is filled with a conductive pattern 251. The part of the plurality of conductive patterns 251 located in the first groove 271 is away from the surface of the substrate 100 and is substantially flush with the surface of the first flat layer 270 away from the substrate 100. The flatness of the surface formed by the first flat layer 270 and the conductive patterns 251 located in the first groove 271 is improved, and the flatness of the substrate surface where the second flat layer 280 is located is improved.

[0094] The portion of the conductive pattern 251 located in the first groove 271 is away from the surface of the substrate 100 and is roughly flush with the surface of the first planar layer 270 away from the substrate 100, which means that the thickness of the portion of the conductive pattern 251 located in the first groove 271 is roughly equal to the depth of the first groove 271.

[0095] Due to the precision limitation of the manufacturing process and the error of the measurement system, it is difficult to make the depth of the first groove 271 and the thickness of the conductive pattern 251 absolutely equal in the actual production process. In the embodiment of the present disclosure, the thickness of the portion of the conductive pattern 251 located in the first groove 271 is approximately equal to the depth of the first groove 271, which means that the difference between the thickness of the conductive pattern 251 (the portion located in the first groove 271) and the depth of the first groove 271 is within an acceptable deviation range. Exemplarily, the above acceptable deviation range can be 5%, that is, the ratio of the difference between the thickness of the conductive pattern 251 and the depth of the first groove 271 to the preset value is less than or equal to 5% of the preset value; the preset value refers to the design value of the thickness of the conductive pattern 251 and the depth of the first groove 271. Of course, the above acceptable deviation range can also be 3%, 8%, etc., and the embodiment of the present disclosure is not specifically limited here.

[0096] It should be understood that, since the first groove 271 is filled with the conductive pattern 251, the boundary of the first groove 271 completely coincides with the boundary of the conductive pattern 251 located in the first groove 271. In the drawings of the present disclosure, the portion indicated by the first groove 271 is the boundary of the conductive pattern 251 located in the first groove 271. For example, see Figure 2A The portion indicated by the first groove 271 is the boundary where the conductive pattern 251 (signal line 17 ) and the first planar layer 270 intersect.

[0097] The display panel 1100 provided in the embodiment of the present disclosure includes a first flat layer 270, a second flat layer 280, and a conductive pattern layer 250 located between the first flat layer 270 and the second flat layer 280, and the anode layer 310 is disposed on the surface of the second flat layer 280 away from the substrate 100. By providing two flat layers (the first flat layer 270 and the second flat layer 280), the flatness of the substrate surface where the second flat layer 280 is located can be improved.

[0098] At the same time, part of the conductive pattern 251 is embedded in the first groove 271, and the vertical projection of the first groove 271 on the substrate 100 overlaps with the vertical projection of the anode 31 on the substrate 100. Based on this, the vertical projection of at least part of the conductive pattern 251 located in the first groove 271 on the substrate 100 overlaps with the vertical projection of the anode 31 on the substrate 100, that is, at least part of the conductive pattern 251 opposite to the anode 31 is embedded in the first groove 271. The conductive pattern 251 located in the first groove 271 is away from the surface of the substrate 100 and is substantially flush with the surface of the first flat layer 270 away from the substrate 100. In this way, the flatness of the area on the second flat layer 280 for setting the anode 31 can be improved, and then the flatness of the anode 31 can be improved, the degree of color separation caused by the ambient light reflected by the anode 31 can be reduced, the possibility of forming a color halo on the light-emitting surface of the display panel 1100 can be reduced, the risk of glare to the human eye can be reduced, and the user experience can be improved.

[0099] See also Figure 2A In the case where the patterned conductive layer of the pixel circuit layer 200 includes an active layer 210, a first gate conductive layer 220, a second gate conductive layer 230, a source-drain conductive layer 240 and a conductive pattern layer 250 that are stacked, the source-drain conductive layer 240 is arranged between the substrate 100 and the first planarizing layer 270, and is in direct contact with the first planarizing layer 270.

[0100] See also Figure 3 , Figure 3 for Figure 1 A partial enlarged view of B in the figure, where Figure 3 The source-drain conductive layer 240, the conductive pattern layer 250 and the anode layer 310 of the display panel 1100 are only exemplarily shown; the source-drain conductive layer 240 at least includes a plurality of voltage signal lines VDD, a plurality of data signal lines DATA, and a source-drain electrode pattern 19 of a thin film transistor. The plurality of conductive patterns 251 include a plurality of signal lines 17 ( Figure 3 At least part of the plurality of signal lines 17 is located in at least one first groove 271 , which reduces the influence of the signal lines 17 on the flatness of the second flat layer 280 and improves the flatness of the anode 31 .

[0101] According to the flatness of the surface of the first flat layer 270 away from the substrate 100, the surface of the signal line 17 away from the substrate 100 may have a convexity or a concaveness; that is, the surface of the signal line 17 away from the substrate 100 may not be absolutely flat. Exemplarily, the surface of the portion of the signal line 17 located in the first groove 271 away from the substrate 100 may not be absolutely flat. Exemplarily, the surface of the portion of the signal line 17 located outside the first groove 271 away from the substrate 100 may not be absolutely flat.

[0102] In some embodiments, see Figure 4 , Figure 4 yes Figure 3 An anode 31 ( Figure 3 In the anode 31 of the region shown in C1 in FIG. 2 , the line widths of the signal line 17 are substantially equal at various locations; that is, the line width of the portion of the signal line 17 located in the first groove 271 is substantially equal to the line width of the portion located outside the first groove 271. In this way, the changes to the line width and routing direction of the signal line 17 can be reduced, which is beneficial to the spatial arrangement of the signal line 17, and avoids the generation of parasitic capacitance between the signal line 17 and other conductive patterns, while not changing the resistivity of the portion of the signal line 17 located in the first groove 271.

[0103] For example, see Figure 4 , the extension direction of the portion of the signal line 17 located in the first groove 271 is substantially the same as the extension direction of the portion located outside the first groove 271. This is beneficial to the spatial arrangement of the plurality of signal lines 17.

[0104] It should be noted that due to the accuracy of the manufacturing process and the error of the measurement system, it is difficult for the line widths of the signal line 17 to be completely equal at various locations. The "line widths of the signal line 17 at various locations are approximately equal" in the embodiment of the present disclosure means that the difference in the line widths of the signal line 17 at various locations is within an acceptable deviation range. Exemplarily, the acceptable deviation range is 5%, that is, the difference between the actual value of the line width of the signal line 17 and the design value is less than or equal to 5% of the ratio of the design value. Of course, the acceptable deviation range can also be 2%, 7%, etc., and the embodiment of the present disclosure does not specifically limit this.

[0105] In the drawings provided by the present disclosure, in order to distinguish the first groove 271 from the conductive pattern 251 in the drawings, there is a gap between the boundary of the first groove 271 and the boundary of the signal line 17. However, in actual production, the boundary of the signal line 17 and the boundary of the first groove 271 can be closely fitted, that is, the first groove 271 is filled with the signal line. For example, see Figure 4 There is a gap between the boundary of the signal line 17 along its extension direction and the boundary of the first groove 271 along the extension direction of the signal line 17. However, in the actual production process, the boundary of the signal line 17 along its extension direction coincides with the boundary of the first groove 271 along the extension direction of the signal line 17, that is, the signal line 17 is completely fitted with the side wall of the first groove 271.

[0106] See also Figure 5 , Figure 5 for Figure 4 The sectional view along the section line E1-E1, Figure 5 Zhongzai Figure 4On the basis of the film layer shown, other film layers of the display panel 1100 are added. The surface of the portion of the signal line 17 located in the first groove 271 away from the substrate 100 is roughly flush with the surface of the first flat layer 270 away from the substrate 100, which can reduce or avoid the fluctuation between the first area of ​​the second flat layer 280 and its surrounding area. The first area refers to the area on the second flat layer 280 that contacts the signal line in the first groove 271. The flatness of the substrate surface where the area on the second flat layer 280 configured to set the anode 31 is located can be improved, thereby improving the flatness of the anode 31.

[0107] See also Figure 4 , along the extension direction of the signal line 17, the vertical projection of the first groove 271 on the substrate 100 passes through the vertical projection of the anode 31 on the substrate 100. That is, along the extension direction of the signal line 17, both ends of the vertical projection of the first groove 271 on the substrate 100 roughly coincide with the boundaries of the vertical projection of the anode 31 on the substrate 100, or at least one end of the vertical projection of the first groove 271 on the substrate 100 exceeds the boundary of the vertical projection of the anode 31 on the substrate 100. In this way, the portion of the signal line 271 opposite to one anode 31 can be completely located in one first groove 271, which can further reduce the influence of the portion of the signal line 271 opposite to the anode 31 on the flatness of the anode 31. Among them, the vertical projection of the portion of the signal line 271 opposite to the anode 31 on the substrate 100 completely overlaps with the vertical projection of the anode 31 on the substrate 100.

[0108] Exemplarily, there are multiple signal lines 17, and the portion of any signal line 17 that is opposite to an anode 31 is located in a first groove 271. In this way, the influence of the signal line 271 on the flatness of the anode 31 can be minimized, the flatness of all the anodes 31 included in the anode layer 310 can be improved, and the possibility of forming a color halo on the light-emitting surface of the display panel 1100 can be reduced.

[0109] See also Figure 8 , Figure 8 yes Figure 3 An anode 31 ( Figure 3 A local enlarged view of the anode 31 in the area shown in C2; the anode 31 includes a main body 311 and a connecting portion 312 connected to the main body 311, such as Figure 8 As shown, the anode 31 is divided into a main body 311 and a connecting portion 312 with the dotted line L1 as the boundary. Fig. 9 , Fig. 9 for Figure 8 A sectional view taken along section line F1-F1 in FIG. Fig. 9 exist Figure 8 On the basis of the film layers shown, other film layers of the display panel 1100 are added.

[0110] The vertical projection of the first opening 32 of the pixel defining layer 320 on the substrate 100 is located within the vertical projection range of the main body 311 of the anode 31 opposite thereto on the substrate 100. The connecting portion 312 is electrically connected to the main body 311 and is configured to electrically connect the main body 311 to the pixel circuit so that the pixel circuit can control the light emitting device 300 to emit light.

[0111] Due to the errors in manufacturing precision and measurement system, in the actual production process, it is difficult to make the portion of the signal line 17 located in the first groove 271 away from the surface of the substrate 100 and completely flush with the surface of the first flat layer 270, that is, there may still be unevenness at the junction between the signal line 17 located in the first groove 271 and the first flat layer 270.

[0112] In order to overcome the above problems, in some embodiments, refer to Figure 8 and Fig. 9 , when the vertical projection of the main body 312 of the anode 31 on the substrate 100 is separated from the vertical projection of the adapter block 18 on the substrate 100; the vertical projection of the main body 311 of the anode 31 on the substrate 100 can be located within the range of the vertical projection of the first groove 271 on the substrate 100. So that the vertical projection of the main body 311 on the substrate 100 is located within the range of the vertical projection of the portion of the signal line 17 located in the first groove 271 on the substrate 100. In this way, the area on the second flat layer 280 configured to carry the anode 31 can be completely located on the signal line 17 in a first groove 271. Even if there are undulations at the junction between the signal line 17 in the first groove 271 and the first flat layer 270, the flatness of the area where the anode 31 is located on the second flat layer 280 can still be ensured, that is, the flatness of the anode 31 can be ensured, thereby reducing the color separation phenomenon of the light reflected by the anode 31.

[0113] It should be understood that the vertical projection of the main body 311 on the substrate 100 is located within the range of the vertical projection of the first groove 271 on the substrate 100, and the boundaries of the vertical projections of the two (the main body 311 and the first groove 271) on the substrate 100 may coincide with each other; or the boundary of the vertical projection of the main body 311 on the substrate 100 is located within the boundary of the vertical projection of the first groove 271 on the substrate 100, and there is a gap between the boundaries of the vertical projections of the two on the substrate 100; or a part of the boundary of the vertical projection of the main body 311 on the substrate 100 has a certain gap with the boundary of the vertical projection of the first groove 271 on the substrate 100, and the other part coincides with the boundary of the vertical projection of the first groove 271 on the substrate 100.

[0114] Exemplarily, the boundary of the vertical projection of the main body 311 on the substrate 100 is located within the boundary of the vertical projection of the first groove 271 on the substrate 100, and there is a gap between the boundaries of the vertical projections of the two on the substrate 100. In this way, the requirements for the alignment accuracy between the first groove 271 and the anode 31 during the manufacturing process of the display panel 1100 can be reduced, and the manufacturing difficulty of the display panel 1100 can be reduced.

[0115] It should be understood that in some embodiments, when the display panel 1100 is not required to be thin and light, it is also possible not to set a groove on the surface of the first flat layer 270 away from the substrate 100, and the positive projection of the anode 31 on the substrate 100 can be directly located within the range of the vertical projection of the signal line 17 on the substrate 100. In this way, the flatness of the anode 31 can still be increased.

[0116] In some embodiments, see Fig.10 , Fig.10 yes Figure 3 An anode 31 ( Figure 3 Another partial enlarged view of the anode 31 in the area shown in C2 in FIG. 2 ; the first groove 271 is a frame-shaped groove connected end to end, and the line width of the portion of the signal line 17 located in the first groove 271 is smaller than the line width of the remaining portion of the signal line 17; that is, the width of the first groove 271 is smaller than the width of the portion of the signal line 17 located outside the first groove 271. By reducing the line width of the signal line 17, the influence of the signal line 17 on the flatness of the second flat layer 280 can be reduced, and the flatness of the second flat layer 280 can be improved. The first groove 271 is a frame-shaped groove connected end to end, so that the portion of the signal line 17 located in the first groove 271 forms two parallel sub-lines, so that the problem of increasing the resistance of the signal line 17 due to reducing the line width of the signal line 17 can be prevented.

[0117] It should be understood that the first groove 271 may also include multiple sub-grooves arranged side by side, so that the portion of the signal line 17 located in the first groove 271 includes multiple sub-lines arranged in parallel to reduce the line width of a single sub-line. There may be gaps between the multiple sub-lines to reduce the impact of each sub-line on the flatness of the second flat layer 280, while reducing the resistance of the signal line 17.

[0118] See also Fig.10 and Fig.11 , Fig.11 is a cross-sectional view along the section line F2-F2 in 10, and Fig.11 exist Figure 4On the basis of the film layer shown, other film layers of the display panel 1100 are added. The outer boundary of the vertical projection of a first groove 271 on the substrate 100 roughly coincides with the boundary of the vertical projection of the main body 311 of an anode 31 on the substrate 100, that is, the vertical projection of the first groove 271 on the substrate 100 is located within the projection range of the main body 311 and is located at the edge of the vertical projection of the main body 311. In this way, the flatness of the middle area of ​​the main body 311 can be improved, and the color separation phenomenon of the light reflected from the central area of ​​the main body 311 can be reduced. At the same time, since part of the ambient light reflected by the edge area of ​​the main body 311 will be emitted to the area where the black matrix 510 is located, the first groove 271 is arranged around the edge of the main body 271 of the anode 31. Even if there are fluctuations in the edge area of ​​the main body 311, the light emitted from the filter 520 that undergoes color separation can be reduced, and the color halo formed on the light-emitting surface of the display panel 1100 can be weakened.

[0119] It should be understood that the first groove 271 is a frame-shaped groove, and the vertical projection of the first groove 271 on the substrate 100 is annular, and the annular projection encloses a closed area. The annular projection includes an inner boundary and an outer boundary; the inner boundary refers to the boundary enclosing the closed area; the outer boundary refers to the boundary away from the closed area.

[0120] Due to the wiring space limitation of the conductive pattern layer 250, the vertical projection of the signal line 17 on the substrate 100 usually overlaps with the vertical projection of the anode 31 on the substrate 100. That is, the vertical projection of the signal line 17 on the substrate 100 is unlikely to be separated from the vertical projection of the anode 31 on the substrate 100. Therefore, in some embodiments, when the wiring space of the conductive pattern layer 250 is limited, the outer boundary of the first groove 271 on the substrate 100 can be located within the projection range of the anode 31 on the substrate 100.

[0121] In some embodiments, see Fig.12 , Fig.12 for Figure 3 A sectional view along section line DD, wherein: Fig.12 101 shown in FIG. 1 is a base substrate 101 , and the base substrate 101 is a set of all film layers including the substrate 100 and between the substrate 100 and the first planar layer 270 .

[0122] The surface of the first flat layer 270 away from the substrate 100 is also provided with a plurality of second grooves 272, one second groove 272 is located between two adjacent first grooves 271, and connects the two adjacent first grooves 271; the portion of the same signal line 17 located between two adjacent first grooves 271 is located in one second groove 272. The portion of the signal line 17 located in the second groove 272 is substantially flush with the surface of the first flat layer away from the substrate. In this way, the signal line 17 can be completely arranged in the groove, and the depths of the first groove 271 and the second groove 272 are substantially the same, thereby reducing the fluctuation of the signal line 17 in the thickness direction of the display panel 1100, and making the resistance of the signal line 17 more uniform at various locations. Moreover, the flatness of the surface formed by the first flat layer 270 and the conductive pattern layer 250 away from the substrate 100 can be further improved, and the flatness of the second flat layer 280 and the anode layer 310 can be improved, thereby reducing the risk of the signal line 17 being broken due to fluctuations.

[0123] In some embodiments, the source-drain electrode layer 240 includes a plurality of voltage signal lines VDD extending along the first direction M1 and arranged at intervals along the second direction M2. The plurality of signal lines 17 may include at least one of a plurality of auxiliary data signal lines Data1 and a plurality of auxiliary voltage signal lines Vdd.

[0124] Exemplarily, the plurality of signal lines 17 may include a plurality of auxiliary data signal lines Data, the auxiliary data signal lines Data extend along the first direction M1, and the plurality of auxiliary data signal lines Data are arranged at intervals along the second direction M2, so that the plurality of auxiliary data signal lines Data are electrically insulated from each other. One auxiliary data signal line Data is opposite to one data signal line DATA of the source-drain conductive layer 240, and the auxiliary data signal line Data is electrically connected to the data signal line DATA opposite thereto through a connecting via hole arranged on the first planar layer 270, thereby connecting one auxiliary data signal line Data in parallel with one data signal line DATA, thereby reducing the resistance of the data signal line DATA.

[0125] Exemplarily, the plurality of signal lines 17 may also include a plurality of auxiliary data signal lines Data and a plurality of auxiliary voltage signal lines Vdd. The plurality of auxiliary data signal lines Data and the plurality of auxiliary voltage signal lines Vdd all extend along the first direction M1, and any two adjacent signal lines 17 are spaced apart to electrically insulate the two adjacent signal lines 17. An auxiliary data signal line Data is opposite to a data signal line DATA, and the auxiliary data signal line Data is arranged in parallel with the data signal line DATA opposite thereto to reduce the resistance of the data signal line DATA. An auxiliary voltage signal line Vdd is opposite to a voltage signal line VDD, and the auxiliary voltage signal line Vdd is electrically connected to the voltage signal line VDD opposite thereto, that is, the auxiliary voltage signal line Vdd is arranged in parallel with the voltage signal line VDD opposite thereto to reduce the resistance of the voltage signal line VDD. Exemplarily, limited by the wiring space of the conductive pattern layer 250, in order to facilitate the arrangement of the plurality of signal lines 17, the line widths of the same signal line 17 are roughly equal at various locations.

[0126] For example, see Figure 3 The plurality of signal lines 17 include a plurality of auxiliary voltage signal lines Vdd, and the plurality of auxiliary voltage signal lines Vdd are electrically connected to the plurality of voltage signal lines VDD, so as to connect the plurality of auxiliary voltage signal lines Vdd in parallel with the plurality of voltage signal lines VDD, thereby reducing the resistance of the plurality of voltage signal lines VDD. The voltage signal line VDD of the source-drain electrode layer 240 is used to provide a common voltage signal for the pixel circuit. Since the common voltage signal provided for each pixel circuit can be the same, based on this, the plurality of auxiliary voltage signal lines Vdd can transmit signals of the same voltage value, and the plurality of auxiliary voltage signal lines Vdd can be set in parallel, thereby further reducing the resistance of the auxiliary voltage signal line Vdd.

[0127] In the case where the plurality of signal lines 17 include a plurality of auxiliary voltage signal lines Vdd, see Figure 3 The plurality of auxiliary voltage signal lines Vdd may include a plurality of first auxiliary voltage signal lines Vdd1 and a plurality of second auxiliary voltage signal lines Vdd2. The plurality of first auxiliary voltage signal lines Vdd1 and the plurality of second auxiliary voltage signal lines Vdd2 intersect each other to form a mesh structure to reduce the overall resistance of the plurality of auxiliary voltage signal lines Vdd.

[0128] The first auxiliary voltage signal line Vdd1 extends along the first direction M1, and a plurality of first auxiliary voltage signal lines Vdd1 are arranged at intervals along the second direction M2; one auxiliary voltage signal line Vdd is opposite to one voltage signal line VDD; Fig.13The first planar layer 270 further includes a plurality of first vias 273, and a first auxiliary voltage signal line Vdd1 is electrically connected to a voltage signal line VDD opposite thereto through at least one first via 273. The second auxiliary voltage signal line Vdd2 extends along the second direction M2, and a plurality of second auxiliary voltage signal lines Vdd2 are arranged at intervals along the first direction M1; the plurality of second auxiliary voltage signal lines Vdd2 are configured to electrically connect a plurality of first auxiliary voltage signal lines Vdd1.

[0129] In some embodiments, see Figure 2A , the multiple conductive patterns 251 of the conductive pattern layer 250 also include multiple adapter blocks 18. An adapter block 18 is configured to electrically connect an anode 31 to a source-drain electrode pattern 19 of a thin film transistor (the drain 14 of the thin film transistor). A plurality of second vias 274 are provided in the first flat layer 270, and the adapter block 18 is electrically connected to a source-drain electrode pattern 19 through at least one second via 274. A plurality of third vias 281 are provided in the second flat layer 280, and the connecting portion 312 of the anode 31 is electrically connected to an adapter block 18 through at least one third via 281. The vertical projection of the second via 274 on the substrate 100 is separated from the vertical projection of the third via 281 on the substrate 100, which is conducive to improving the stability of the connection between the anode 31 and the adapter block 18.

[0130] For example, see Figure 2A Each adapter block 18 is electrically connected to a source-drain electrode pattern 19 through a second via hole 274. And the connecting portion 312 of each anode 31 is electrically connected to a adapter block 18 through a third via hole 281. The source-drain electrode pattern 19 includes a drain electrode 14 of a thin film transistor, such as Figure 2A As shown, the adapter block 18 is electrically connected to a source-drain electrode pattern 19 through a second via hole 274 , that is, the adapter block 18 is electrically connected to a drain electrode 14 of a thin film transistor through a second via hole 274 .

[0131] The anode 31 needs to be electrically connected to a source-drain electrode pattern 19. The anode layer 310 and the source-drain electrode pattern 19 include at least a first flat layer 270 and a second flat layer 280. The spacing between the anode layer 310 and the source-drain electrode pattern 19 is relatively large. The adapter block 18 can prevent the connecting via between the connecting portion 312 of the anode 31 and the source-drain electrode pattern 19 from being too deep, thereby improving the reliability of the connection between the anode 31 and the source-drain electrode pattern 19.

[0132] See also Figure 4 , a vertical projection of the connection portion 312 on the substrate 100 overlaps with a vertical projection of the adapter block 18 on the substrate 100 , so that the connection portion 312 can be electrically connected to the adapter block 18 through at least one third via hole.

[0133] In some embodiments, see Figure 5 , the vertical projection of the adapter block 18 on the substrate 100 overlaps with the vertical projection of the filter portion 520 on the substrate 100. The adapter block 18 includes a first portion 181, and the vertical projection of the first portion 181 on the substrate 100 is located within the range of the vertical projection of the filter portion 520 on the substrate 100. And because the vertical projection of the filter portion 520 on the substrate 100 is located within the range of the vertical projection of the anode 31 on the substrate 100, the vertical projection of the first portion 181 of the adapter block 18 on the substrate 100 is located within the range of the vertical projection of the anode 31 on the substrate 100.

[0134] In this way, the surface formed by the first portion 181 and the first flat layer 270 affects the flatness of the anode 31. Moreover, the ambient light reflected by the portion of the anode 31 opposite to the first portion 181 can be emitted from the filter portion 520. The higher the flatness of the surface formed by the first portion 181 and the first flat layer 270, the smaller the degree of color separation of the ambient light reflected by the portion of the anode 31 opposite to the first portion 181.

[0135] Based on this, in order to improve the flatness of the portion of the anode 31 opposite to the first portion 181. Figure 4 and Figure 5 The surface of the first flat layer 270 away from the substrate 100 is also provided with a plurality of third grooves 275; wherein, Figure 4 and Figure 5 Only one third groove 275 is shown as an example. At least part of the adapter block 18 is located in at least one third groove 275, and the vertical projection of the third groove 275 on the substrate 100 overlaps with the vertical projection of the filter part 520 on the substrate 100; that is, the vertical projection of the part of the adapter block 18 located in the third groove 275 on the substrate 100 overlaps with the vertical projection of the filter part 520 on the substrate 100. Based on this, at least part of the first part 181 of the adapter block 18 is located in at least one third groove 275.

[0136] At least part of the first portion 181 is located in at least one third groove 275, and the portion of the adapter block 18 located in the third groove 275 is away from the surface of the substrate 100 and is substantially flush with the surface of the first flat layer 270 away from the substrate 100. In this way, the flatness of the portion of the anode 31 opposite to the first portion 181 can be improved, the color separation degree of the ambient light reflected by the portion of the anode 31 opposite to the first portion 181 can be reduced, the possibility of color halo formed on the light-emitting surface of the display panel 1100 can be reduced, the risk of glare to the human eye can be reduced, and the user experience can be improved.

[0137] For example, see Figure 4 and Figure 5The first part 181 of each adapter block 18 is entirely located in a third groove 275. In this way, the color separation degree of the ambient light reflected by the part of the anode 31 opposite to the first part 181 can be minimized, thereby reducing the possibility of a color halo forming on the light-emitting surface of the display panel 1100.

[0138] It should be understood that among the multiple adapter blocks 18 included in the conductive pattern layer 250, the vertical projections of some adapter blocks 18 on the substrate 100 may overlap with the vertical projections of the filter unit 520 on the substrate 100, that is, some adapter blocks 18 may have the first portion 181. Alternatively, the vertical projections of all adapter blocks 18 on the substrate 100 may overlap with the vertical projections of the filter unit 520 on the substrate 100, that is, all adapter blocks 18 may have the first portion 181.

[0139] For example, see Figure 3 , the vertical projection of some of the plurality of adapter blocks 18 on the substrate 100 overlaps with the vertical projection of the filter portion 520 on the substrate 100, that is, only some of the adapter blocks 18 have the first portion 181. Figure 4 The vertical projection of the adapter block 18 on the substrate 100 overlaps with the vertical projection of the filter portion 520 on the substrate 100. In this case, the adapter block 18 includes a first portion 181. Figure 8 The vertical projection of the adapter block 18 shown on the substrate 100 is separated from the vertical projection of the main body 311 of the anode 31 on the substrate 100, that is, the vertical projection of the adapter block 18 on the substrate 100 is separated from the vertical projection of the filter part 520 on the substrate 100. At this time, the adapter block 18 does not have the first part 181.

[0140] In some embodiments, see Figure 6 and Figure 7 , each adapter block 18 can also be set in a third groove 275. In this way, the fluctuation of the adapter block 18 in the thickness direction of the display panel 1100 can be reduced, the problem of uneven resistance of the adapter block 18 (the junction between the first part 181 and the rest of the parts) can be avoided, and the risk of the adapter block 18 breaking at the junction between the first part 181 and the rest of the parts can be avoided; the alignment accuracy between the first part 181 and the filter part 520 during the manufacturing process of the display panel 1100 can also be reduced, that is, the accuracy of the setting position of the third groove 275 during the manufacturing process of the display panel 1100 can be reduced, the alignment accuracy between the conductive pattern layer 250, the anode layer 310 and the color filter layer 500 can be reduced, and the manufacturing difficulty of the display panel 1100 can be reduced.

[0141] In some embodiments, Figure 8In the case where the vertical projection of the adapter block 18 on the substrate 100 is separated from the vertical projection of the main body 311 on the substrate 100, refer to Fig. 9 , the third groove 275 may not be provided, that is, the adapter block 18 is directly provided on the surface of the first planar layer 170 away from the substrate 100 .

[0142] In some embodiments, the conductive pattern layer 250 is generally formed by a sputtering process, and the thickness of the conductive pattern 251 formed by the conductive pattern layer 250 is generally 0.6 μm to 0.7 μm. For example, the thickness of the conductive pattern 251 can be 0.6 μm, 0.65 μm, or 0.7 μm, etc., which are not listed here one by one.

[0143] The depths of the first groove 271, the second groove 272 and the third groove 275 can be 0.6 μm to 0.7 μm, which is suitable for the thickness of the conductive pattern 251. For example, the depths of the first groove 271, the second groove 272 and the third groove 275 can be 0.6 μm, 0.65 μm, or 0.7 μm, etc., which are not listed here one by one.

[0144] The thickness of the conductive pattern 251, the depth of the first groove 271, the depth of the second groove 272 and the depth of the third groove 275 are approximately equal, so that the portion of the conductive pattern 251 located in the first groove 271, the portion of the conductive pattern 251 located in the second groove 272, and the portion of the conductive pattern 251 located in the third groove 275 are approximately flush with the surface of the first flat layer 270 away from the substrate 100, so that the surface formed by the first flat layer 270 and the conductive pattern layer 250 away from the substrate 100 is approximately flat, thereby improving the overall flatness of the second flat layer 280 and the flatness of the anode layer 310.

[0145] In some embodiments, the thickness of the first planar layer 270 is 1.5 μm to 3.0 μm. If the thickness of the first planar layer 270 is too thin, it is not conducive to forming a substantially flat surface of the first planar layer 270. Therefore, the thickness of the first planar layer 270 is greater than or equal to 1.5 μm.

[0146] In some embodiments, the greater the thickness of the first planar layer 270 , the flatter the first planar layer 270 is away from the surface of the substrate 100 , but this is not conducive to thinning the display panel 1100 . Therefore, the first planar layer 270 is generally less than or equal to 3.0 μm.

[0147] Thus, the thickness of the first planar layer is 1.5 μm to 3.0 μm. For example, the thickness of the first planar layer 270 may be 1.5 μm, 2.0 μm, 2.4 μm or 3.0 μm, etc., which are not listed here one by one.

[0148] In some embodiments, the thickness of the second planar layer 280 is 1.0 μm to 2.0 μm. For example, the thickness of the second planar layer 280 may be 1.5 μm, 2.0 μm, 2.4 μm or 3.0 μm, etc., which are not listed here one by one.

[0149] In some embodiments, see Figure 2B , in the case where the patterned conductive layer of the pixel circuit layer 200 includes an active layer 210, a first gate conductive layer 220, a second gate conductive layer 230, and a conductive pattern layer 250 that are stacked. The first planar layer 270 is located between the second gate conductive layer 230 and the conductive pattern layer 250, and the first planar layer 270 is in direct contact with the second gate conductive layer 230 on a side close to the substrate 100. In this way, the first planar layer 270 is also configured to separate the region between the second gate conductive layer 230 and the conductive pattern layer 250 where electrical connection is not required.

[0150] See also Fig.13 , Fig.13 When the patterned conductive layer includes an active layer 210, a first gate conductive layer 220, a second gate conductive layer 230 and a conductive pattern layer 250 which are stacked, Figure 1 The enlarged view of B in the figure, Fig.13 2 and 3. Only the conductive pattern layer 250 and the anode layer 310 are shown exemplarily. The conductive pattern layer 250 includes at least a plurality of voltage signal lines VDD, a plurality of data signal lines DATA, and one of the source-drain electrode patterns 19 of the thin film transistors. The plurality of source-drain electrode patterns 19 of the plurality of thin film transistors include a first source-drain electrode pattern 191 and a second source-drain electrode pattern 192.

[0151] See also Fig.13 , the vertical projection of the first source-drain electrode pattern 191 on the substrate 100 overlaps with the vertical projection of the anode 31 on the substrate 100. And part of the first source-drain electrode pattern 191 ( Fig.13 The vertical projection of the first source-drain electrode pattern 191A on the substrate 100 is located within the vertical projection of the anode 31 on the substrate 100. Part of the first source-drain electrode pattern 191 ( Fig.13 The vertical projection of the first source-drain electrode pattern 191B) on the substrate 100 partially overlaps with the vertical projection of the anode 31 on the substrate 100, and are partially separated from each other.

[0152] See also Fig.14A The first source-drain electrode pattern 191 includes a second portion 1911 , a vertical projection of the second portion 1911 on the substrate 100 is located within the range of a vertical projection of the anode 31 on the substrate 100 , and one second portion 1911 is located in one first groove 271 .

[0153] In which, when the vertical projection of the first source-drain electrode pattern 191A on the substrate 100 is located within the range of the vertical projection of the anode 31 on the substrate 100, the second part 1911 of the first source-drain electrode pattern 191 includes the entire first source-drain electrode pattern 191, so that a first source-drain electrode pattern 191 is located in a first groove 271.

[0154] When the vertical projection of the first source-drain electrode pattern 191B on the substrate 100 partially overlaps with the vertical projection of the anode 31 on the substrate 100 and is partially separated from each other, the first source-drain electrode pattern 191 further includes a third portion 1912, and the vertical projection of the third portion 1912 on the substrate 100 is outside the vertical projection range of the anode 31 on the substrate 100. For example, see Figure 4 A, the second portion 1911 is located in one of the first grooves 271 , and the third portion 1912 may be located on the surface of the first planar layer 270 away from the substrate 100 .

[0155] See also Fig.13 , the vertical projection of the second source-drain electrode pattern 192 on the substrate 100 is separated from the vertical projection of the anode 31 on the substrate 100. The second source-drain electrode pattern 192 can be disposed in the groove; or directly disposed on the surface of the first planar layer 270 away from the substrate 100; or partially disposed in the groove and partially disposed on the surface of the first planar layer 270 away from the substrate 100; the embodiments of the present disclosure are not specifically limited.

[0156] In the display panel 1100 provided by the embodiment of the present disclosure, the second portion 1911 of the source-drain electrode pattern 19 is disposed in the first groove 271, and the surface of the second portion 1911 away from the substrate 100 is substantially flush with the surface of the first flat layer 270 away from the substrate 100. In this way, the surface away from the substrate 100 formed by the first flat layer 270 and the second portion 1911 is substantially flat, which can improve the flatness of the area on the second flat layer 280 that contacts the second portion 1911, thereby improving the flatness of the portion on the anode 31 that is opposite to the second portion 1911, reducing the degree of color separation caused by the ambient light reflected by the anode 31, reducing the possibility of forming a color halo on the light-emitting surface of the display panel 1100, reducing the risk of glare to the human eye, and improving the user experience.

[0157] In some embodiments, see Fig. 14B, the second portion 1911 and the third portion 1912 of the same first source-drain electrode pattern 191 are located in a first groove 271. In this way, the fluctuation of the first source-drain electrode pattern 191 in the thickness direction of the display panel 1100 can be reduced, the problem of sudden resistance change in the first source-drain electrode pattern 191 (at the junction of the second portion 191 and the remaining portions) can be avoided, and the risk of the first source-drain electrode pattern 191B being broken at the junction of the second portion 191 and the remaining portions can be reduced; at the same time, the alignment accuracy requirement between the first groove 271 and the anode 31 during the manufacturing process of the display panel 1100 can be reduced, thereby reducing the manufacturing difficulty of the display panel 1100.

[0158] In some embodiments, see Fig.15A , Fig.15A The data signal line DATA is taken as an example for demonstration, which can also be a voltage signal line VDD; at least one of the multiple voltage signal lines VDD and the multiple data signal lines DATA included in the conductive pattern layer 250 has an overlapping part of a vertical projection on the substrate 100 and a vertical projection of an anode 31 on the substrate 100, which is located in a first groove 271.

[0159] Exemplarily, each voltage signal line VDD includes at least one first subsegment, and the vertical projection of each first subsegment on the substrate 100 is located within the range of the vertical projection of an anode 31 on the substrate 100; and one first subsegment is located in one first groove 271. Each data signal line DATA includes at least one second subsegment, and the vertical projection of one second subsegment on the substrate 100 is located within the range of the vertical projection of one anode 31 on the substrate 100; and one second subsegment is located in one first groove 271.

[0160] In this way, the flatness of the area on the second flat layer 280 that contacts the voltage signal line VDD and the data signal line DATA and is configured to set the anode 31 can be improved, thereby improving the flatness of the portion of the anode 31 that is opposite to the voltage signal line VDD and the data signal line DATA, and reducing the degree of color separation caused by the ambient light reflected by the anode 31.

[0161] In some embodiments, see Fig. 15B , at least one of the plurality of voltage signal lines VDD and the plurality of data signal lines DATA may be disposed in one first groove 271, that is, at least one of the entire voltage signal line VDD and the entire data signal line DATA may be disposed in one first groove 271. Fig. 15B In the figure, a data signal line DATA is located in a first groove 271 as an example for description.

[0162] Exemplarily, each voltage signal line VDD is located in a first groove 271, and each data signal line DATA is located in a first groove 271, so that the fluctuation of the voltage signal line VDD and the data signal line DATA in the thickness direction of the display panel 1100 can be reduced, so that the resistance of each part of the voltage signal line VDD and the data signal line DATA extending along the length direction is more uniform, and the risk of the voltage signal line VDD and the data signal line DATA being broken can be reduced. The requirements for the alignment accuracy between the first groove 271 and the anode 31 can also be reduced.

[0163] In some embodiments, the material of the first flat layer 270 includes an organic material, so that the first flat layer 270 with a substantially flat surface can be formed by a coating process. The material of the second flat layer 280 can also include an organic material, so that the second flat layer 280 with a substantially flat surface can be formed by a coating process. Exemplarily, the material of the first flat layer 270 is the same as the material of the second flat layer 280.

[0164] Some embodiments of the present disclosure also provide a method for manufacturing a display panel, see Fig.16 , the preparation method comprises:

[0165] S100, such as Fig.16 (a) An insulating material film 270A is formed on one side of the base substrate 101.

[0166] The base substrate 101 refers to all film layers between the substrate 100 and the first planar layer 270 in the display panel 1100 .

[0167] Exemplarily, a plurality of patterned conductive layers include an active layer 210, a first gate conductive layer 220, a second gate conductive layer 230, a source-drain conductive layer 240, and a conductive pattern layer 250 that are stacked. The substrate 101 further includes a first gate insulating layer 261 between the active layer 210 and the first gate conductive layer 220, a second gate insulating layer 262 between the first gate conductive layer 220 and the second gate conductive layer 230, an interlayer dielectric layer 263 between the second gate conductive layer 230 and the source-drain conductive layer 240, and a conductive pattern layer 250 between the source-drain conductive layer 240.

[0168] Exemplarily, the insulating material used in the insulating material film 270A includes an organic material, so that the insulating material can be formed into the insulating material film 270A by a coating process, and the surface of the insulating material film 270A away from the base substrate 101 is substantially flat. The thickness of the insulating material film 270A can be 1.5 μm to 3.0 μm.

[0169] S200, such as Fig.16 (b) A plurality of first grooves 271 are made on the insulating material film 270A to form a first planar layer 270 .

[0170] For example, a plurality of first grooves 271 may be formed by a photolithography process (including exposure, etching, and development, etc.) The depth of the first grooves 271 may be 0.6 μm to 0.7 μm.

[0171] S300, such as Fig.16 (c) A conductive pattern layer 250 is formed on a side of the first planar layer 270 away from the substrate 100 .

[0172] The conductive pattern layer 250 includes a plurality of conductive patterns 251, at least part of which is located in the first groove 271, and the thickness of the conductive pattern 251 is substantially equal to the depth of the first groove 271, so that the portion of the conductive pattern 251 located in the first groove 271 is away from the surface of the base substrate 101 and is substantially flush with the surface of the first flat layer 270 away from the base substrate 101. In accordance with the depth of the first groove 271, the thickness of the conductive pattern 251 may be 0.6 μm to 0.7 μm.

[0173] S400, such as Fig.16 (d) A second planarization layer 280 is formed on a side of the conductive pattern layer 250 away from the substrate 100 .

[0174] Exemplarily, the insulating material used for the second planar layer 280 includes an organic material, so that the insulating material can be formed into the second planar layer 280 by a coating process, and the surface of the second planar layer 280 away from the base substrate 101 is substantially flat. The thickness of the second planar layer 280 can be 1.0 μm to 2.0 μm.

[0175] S500, such as Fig.16 (e) An anode conductive layer 310 is formed on a side of the second planar layer 280 away from the substrate 100 .

[0176] The anode conductive layer 310 includes a plurality of mutually separated anodes 31 , and a vertical projection of one anode 31 on the substrate 100 overlaps with a vertical projection of at least one first groove 271 on the substrate 100 .

[0177] The display panel 1100 obtained by the manufacturing method provided by the embodiment of the present disclosure has the same beneficial effects as the display panel 1100 described in any of the above embodiments, which will not be described in detail here.

[0178] In some embodiments, the plurality of conductive patterns 251 include a plurality of auxiliary voltage signal lines Vdd and a plurality of transfer blocks 18 .

[0179] Before forming the insulating material film 270A on one side of the base substrate 101 in S100, the method further includes:

[0180] S001 , manufacturing a source-drain conductive layer on a substrate to form a substrate base plate 101 .

[0181] The source-drain conductive layer 240 at least includes a plurality of voltage signal lines VDD, a plurality of data signal lines DATA, and source-drain electrode patterns of thin film transistors.

[0182] See also Fig.16 , S200, while forming a plurality of first grooves 271 on the insulating material film 270A, the manufacturing method further includes:

[0183] A plurality of first via holes 273 and a plurality of second via holes 274 are formed on the insulating material film 270A. That is, S200 includes: forming a plurality of first grooves 271 , a plurality of first via holes 273 and a plurality of second via holes 274 on the insulating material film 270A.

[0184] For example, a half-tone mask may be used to simultaneously etch the insulating material film 270A through a photolithography process to obtain a plurality of first grooves 271 , a plurality of first via holes 273 , and a plurality of second via holes 274 .

[0185] One end of a first via hole 273 close to the base substrate 101 exposes a portion of a voltage signal line VDD (not shown in the figure), and a portion of an auxiliary voltage signal line Vdd is located in at least one first via hole 273 and is electrically connected to a voltage signal line VDD.

[0186] One end of a second via hole 274 close to the substrate 100 exposes a portion of a source-drain electrode pattern (not shown in the figure), and a portion of a transfer block 18 is located in at least one second via hole 274 and is electrically connected to the source-drain electrode pattern of a thin film transistor.

[0187] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: The display panel is provided with a plurality of thin film transistors; the display panel comprises: substrate; A source-drain conductive layer, disposed on one side of the substrate, at least comprising a plurality of voltage signal lines, a plurality of data signal lines, and one of the source-drain electrode patterns of the thin film transistor; A first flat layer is arranged on a side of the source-drain conductive layer away from the substrate, and a plurality of first grooves are arranged on the side of the first flat layer away from the substrate; the first grooves are frame-shaped grooves connected end to end; a conductive pattern layer, disposed on a side of the first flat layer away from the substrate, comprising a plurality of conductive patterns, at least parts of the plurality of conductive patterns being located in the plurality of first grooves, and parts of the plurality of conductive patterns located in the first grooves being away from the surface of the substrate and being substantially flush with the surface of the first flat layer away from the substrate; A second planar layer is disposed on a side of the conductive pattern layer away from the substrate; an anode conductive layer, disposed on a side of the second flat layer away from the substrate, comprising a plurality of anodes, wherein the anodes include a main body, and a vertical projection of the plurality of anodes on the substrate overlaps a vertical projection of at least one first groove on the substrate; a pixel defining layer, arranged on a side of the anode conductive layer away from the substrate, the pixel defining layer having a plurality of first openings; a vertical projection of one of the first openings on the substrate is located within the range of a vertical projection of the main body on the substrate; an outer boundary of a vertical projection of one of the first grooves on the substrate substantially coincides with a boundary of a vertical projection of the main body on the substrate; The plurality of conductive patterns include a plurality of signal lines, at least part of which is located in at least one of the first grooves; and the line width of the portion of the signal line located in the first groove is smaller than the line width of the remaining portion of the signal line.

2. The display panel according to claim 1, characterized in that: A plurality of second grooves are further provided on the surface of the first flat layer away from the substrate, wherein one second groove is located between two adjacent first grooves and connects the two adjacent first grooves; a portion of the same signal line located between two adjacent first grooves is located in one second groove, and a portion of the signal line located in the second groove is substantially flush with a surface of the first flat layer away from the substrate away from the substrate.

3. The display panel according to claim 1 or 2, characterized in that: The plurality of signal lines include at least one of a plurality of auxiliary data signal lines and a plurality of auxiliary voltage signal lines.

4. The display panel according to claim 3, characterized in that: The voltage signal line extends along a first direction, and the plurality of voltage signal lines are arranged at intervals along a second direction; The plurality of signal lines include a plurality of auxiliary voltage signal lines, and the plurality of auxiliary voltage signal lines are electrically connected to the plurality of voltage signal lines; the plurality of auxiliary voltage signal lines include: A plurality of first auxiliary voltage signal lines, the first auxiliary voltage signal lines extending along a first direction, and the plurality of first auxiliary voltage signal lines being arranged at intervals along a second direction; one auxiliary voltage signal line being opposite to one voltage signal line; a plurality of second auxiliary voltage signal lines, the second auxiliary voltage signal lines extending along the second direction, and the plurality of second auxiliary voltage signal lines being arranged at intervals along the first direction; the plurality of second auxiliary voltage signal lines being configured to electrically connect the plurality of first auxiliary voltage signal lines; The first planar layer further includes a plurality of first via holes, and the first auxiliary voltage signal line is electrically connected to the voltage signal line opposite thereto through at least one of the first via holes.

5. The display panel according to claim 1, characterized in that: The display panel further comprises a color filter layer, which is arranged on a side of the anode conductive layer away from the substrate and comprises a plurality of filter portions arranged at intervals; A plurality of third grooves are further provided on the surface of the first flat layer away from the substrate, and a vertical projection of the third grooves on the substrate overlaps with a vertical projection of the filter portion on the substrate; The conductive pattern layer also includes a plurality of adapter blocks, one adapter block being configured to electrically connect one of the anodes to a source-drain electrode pattern of a thin film transistor; at least a portion of the adapter block is located in at least one of the third grooves, and the portion of the adapter block located in the third groove is away from the surface of the substrate and is substantially flush with the surface of the first planar layer away from the substrate.

6. The display panel according to claim 5, characterized in that: The adapter block includes a first part, a vertical projection of the first part of the adapter block on the substrate is located within the range of a vertical projection of the filter part on the substrate, and the first part of the adapter block is located in one of the third grooves.

7. The display panel according to claim 5, characterized in that: A transfer block is located in one of the third grooves.

8. The display panel according to claim 5, characterized in that: In the case where the anode includes a main body, the anode further includes a connecting portion connected to the main body; A plurality of second via holes are provided in the first planar layer, and the adapter block is electrically connected to one of the source-drain electrode patterns through at least one second via hole; A plurality of third via holes are provided in the second planar layer, and the connecting portion is electrically connected to one of the transfer blocks through at least one third via hole.

9. The display panel according to claim 5, characterized in that: The depth of the third groove is 0.6 μm to 0.7 μm.

10. The display panel according to claim 1, characterized in that: The thickness of the first flat layer is 1.5 μm to 3.0 μm; The depth of the first groove is 0.6 μm to 0.7 μm.

Images