Superconducting structures and devices with alloy surface termination

Abstract

A method of manufacturing a superconductor device includes providing a first metal layer on top of a substrate. Oxidation of a top surface of the first metal layer is rejected. A second metal layer is deposited on top of the first metal layer. A superconducting alloy of the first metal layer and the second metal layer is created between the first metal layer and the second metal layer. There is no oxide layer between the superconducting alloy and the first metal layer.

Description

Technical Field

[0001] This disclosure relates generally to quantum computing, and more specifically to superconducting structures and methods for their generation. Background Technology

[0002] Superconducting quantum computing is the realization of a quantum computer within superconducting electronic circuits. Quantum computing studies the application of quantum phenomena in information processing and communication. Different models of quantum computing exist, with the most popular models including the concepts of qubits and quantum gates. A qubit is a generalization of a bit having two possible states, but can be in a quantum superposition of both states. A quantum gate is a generalization of logic gates; however, it describes the transformation that one or more qubits will undergo after the gate is applied to them, given their initial states. Different quantum phenomena (such as superposition and entanglement) have no analogues in the world of classical computing and therefore may involve special structures, techniques, and materials. Summary of the Invention

[0003] According to an embodiment, the superconducting device includes a first metal layer on top of a substrate. A second metal layer is located on top of the first metal layer. A superconducting alloy of the first and second metal layers is located between the first and second metal layers. There is no oxide layer between the superconducting alloy and the first metal layer.

[0004] In one embodiment, the first metal layer is niobium (Nb), the second metal layer is aluminum (Al), and the superconducting alloy is Al3Nb.

[0005] In one embodiment, the grains of the superconducting alloy are oriented generally with a plane (002) parallel to the surface of the substrate metal layer.

[0006] In one embodiment, an electrode is present on top of the second metal layer.

[0007] In one embodiment, the electrode is a Josephson junction electrode.

[0008] In one embodiment, the superconducting alloy is operable to protect the first metal layer from oxidation or contamination that could affect the performance of the superconducting device.

[0009] According to an embodiment, a method of manufacturing a superconducting device includes providing a first metal layer on top of a substrate. Oxidation of the top surface of the first metal layer is prevented. A second metal layer is deposited on top of the second metal layer. A superconducting alloy of the first and second metal layers is formed between the first and second metal layers. No oxide layer exists between the superconducting alloy and the first metal layer.

[0010] In one embodiment, preventing oxidation of the top surface of the first metal layer includes placing the second metal layer on top of the first metal layer after the deposition of the first metal layer and before the top surface of the first metal layer is exposed to air.

[0011] In one embodiment, preventing oxidation of the top surface of the first metal layer also includes keeping the superconducting device in a vacuum between the deposition of the first metal layer and the deposition of the second metal layer.

[0012] In one embodiment, preventing oxidation of the top surface of the first metal layer includes depositing the second metal layer on top of the first metal layer after the top surface of the first metal layer has been exposed to air and after cleaning the top surface of the first superconductor metal, in order to remove any oxidation therefrom.

[0013] In one embodiment, the second metal layer is etched away after the superconducting alloy is produced.

[0014] In one embodiment, the second metal layer is etched away after the superconducting alloy is produced.

[0015] In one embodiment, the superconducting alloy is produced by annealing the first metal layer and the second superconducting metal at a predetermined temperature.

[0016] In one embodiment, the superconducting alloy creates an electrical path from the first metal layer to the second metal layer.

[0017] In one embodiment, depending on the annealing temperatures of the first and second metal layers, the lattice orientation of the superconducting alloy is (002), (112), or (101) to produce the superconducting alloy.

[0018] In one embodiment, an electrode is deposited on top of the second metal layer.

[0019] In one embodiment, the electrode is a Josephson junction electrode.

[0020] In one embodiment, the second metal layer is removed and an electrode is deposited on top of the superconducting alloy.

[0021] According to an embodiment, a method of manufacturing a superconducting device includes providing a first metal layer on top of a substrate. An initial oxide layer is formed on the top surface of the first metal layer. A second metal layer is deposited on top of the second metal layer. A superconducting alloy of the first and second metal layers is formed between the first and second metal layers. During the formation of the superconducting alloy, the initial oxide layer is moved to the top surface of the superconducting alloy.

[0022] In one embodiment, the initial oxide and the second metal layer on the top surface of the superconducting alloy are removed. An electrode is deposited on top of the superconducting alloy.

[0023] These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which will be read in conjunction with the accompanying drawings. Attached Figure Description

[0024] The accompanying drawings are illustrative embodiments. They do not show all embodiments. Other embodiments may be used alternatively or as an alternative. Details that may be obvious or unnecessary may be omitted to save space or for more efficient illustration. Some embodiments may be practiced with additional components or steps and / or without all components or steps shown. When the same number appears in different drawings, it refers to the same or similar parts or steps.

[0025] Figure 1A The first superconductor layer on top of the substrate is shown.

[0026] Figure 1B A residual oxide layer is shown on top of the first superconductor layer.

[0027] Figure 2 This is a simplified cross-sectional view of the superconducting structure consistent with the illustrative embodiment.

[0028] Figure 3A A semiconductor structure prior to the formation of a superconducting alloy between metal layers is shown according to an illustrative embodiment.

[0029] Figure 3B A semiconductor structure is shown after a superconducting alloy is formed between the first metal layer and the second metal layer, consistent with the illustrative embodiment.

[0030] Figure 3C A semiconductor structure including an electrode on top of a second metal layer is shown according to an illustrative embodiment.

[0031] Figure 3D A semiconductor structure including electrodes directly on a superconducting alloy is shown, consistent with the illustrative embodiment.

[0032] Figure 4 The formation of superconducting alloys with different orientations based on annealing temperature is shown according to an illustrative embodiment.

[0033] Figures 5A to 5D Different processing steps for producing a superconducting structure, consistent with the illustrative embodiment, are shown, which includes an initial oxide layer between first and second metal layers. Detailed Implementation

[0034] Overview

[0035] In the following detailed description, numerous specific details are illustrated by way of examples to provide a thorough understanding of the relevant teachings. However, it should be clear that the teachings can be practiced without such details. In other cases, well-known methods, processes, components, and / or circuits have been described at a relatively high level without detail to avoid unnecessarily obscuring aspects of this teaching.

[0036] In one aspect, spatially relative terms such as “front,” “rear,” “top,” “bottom,” “below,” “under,” “lower,” “above,” “upper,” “side,” “left,” and “right” are used with reference to the orientations in the described figures. Since components of embodiments of this disclosure can be positioned in multiple different orientations, directional terms are used for illustrative purposes and are by no means limiting. Therefore, it should be understood that spatially relative terms are intended to include different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features would be oriented “above” other elements or features. Thus, for example, the term “below” can include orientations above and below. The device may be oriented in other ways (rotated 90 degrees or viewed or referenced in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0037] As used herein, the terms “lateral” and “horizontal” describe the orientation parallel to the first surface of the chip.

[0038] As used herein, the term "vertical" describes an orientation that is arranged perpendicular to a first surface of a chip, chip carrier, or semiconductor body.

[0039] As used herein, the terms “coupled” and / or “electrically coupled” do not mean that components must be directly coupled together; an intermediate component may be provided between “coupled” or “electrically coupled” components. Conversely, if a component is referred to as “directly connected” or “directly coupled” to another component, no intermediate component is present. The term “electrically connected” refers to a low-ohm electrical connection between components that are electrically connected together.

[0040] While the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] This document describes exemplary embodiments with reference to cross-sectional views as schematic diagrams of idealized or simplified implementations (and intermediate structures). Therefore, variations in the shapes illustrated are expected due to factors such as manufacturing techniques and / or tolerances. Consequently, the areas shown in the figures are schematic in nature, and their shapes do not necessarily represent the actual shapes of the areas of the device, and are not limited in scope.

[0042] It should be understood that other embodiments may be used and structural or logical changes may be made without departing from the spirit and scope defined by the claims. The description of the embodiments is not restrictive. In particular, elements of the embodiments described below may be combined with elements of different embodiments.

[0043] As used herein, certain terms are used to indicate what can be considered idealized behavior, such as “lossless,” “superconductor,” or “superconducting.” These terms are intended to cover functionality that may not be perfectly ideal but is within an acceptable margin for a given application. For example, a certain level of loss or tolerance may be acceptable so that the resulting material and structure can still be referred to using these “idealized” terms.

[0044] The concepts in this article relate to quantum technologies and quantum chips. Regarding quantum technologies, the electromagnetic energy associated with a qubit can be stored, for example, in a so-called Josephson junction and in capacitive and inductive elements used to form that qubit. Other examples include spin qubits coupled to resonators or topological qubits, microfabricated ion traps, etc. This teaching also supports other types of superconducting components, including (but not limited to) circulators, isolators, amplifiers, filters, active control electronics (such as fast single-flux quantum (RSFQ)), etc.

[0045] In one example, to read out the state of a qubit, a microwave signal is applied to a microwave readout cavity coupled to the qubit at that cavity frequency. The emitted (or reflected) microwave signal passes through multiple thermal isolation stages and low-noise amplifiers, which are used to block or reduce noise and improve the signal-to-noise ratio. The amplitude and / or phase of the returned / output microwave signal carry information about the qubit state, such as whether the qubit has shifted to the ground or excited state. The microwave signal carrying quantum information about the qubit state is typically weak (e.g., on the order of a few microwave photons). This weak signal can be measured using different circuits and techniques. For example, low-noise quantum limiting amplifiers (QLAs), such as Josephson amplifiers and traveling-wave parametric amplifiers (TWPAs), can be used as preamplifiers at the output of a quantum system to amplify the quantum signal while adding a minimum amount of noise specified by quantum mechanics to improve the signal-to-noise ratio of the output chain. Besides Josephson amplifiers, certain Josephson microwave components using Josephson amplifiers or Josephson mixers (such as Josephson circulators, Josephson isolators, and Josephson mixers) can be used in scalable quantum processors. Therefore, the Josephson junction is a significant circuit element in superconducting quantum computers. A Josephson junction can comprise a thin layer of insulating material between two superconducting layers, sometimes referred to as a barrier or tunneling barrier. This Josephson junction acts as a superconducting tunnel junction.

[0046] A qubit system may include one or more readout resonators coupled to the qubit. The readout resonator may be a transmission line that includes a capacitive connection to ground on one side and is shorted to ground on the other side (as in a quarter-wavelength resonator), or it may have a capacitive connection to ground (as in a half-wavelength resonator), resulting in oscillations within the transmission line, where the resonant frequency of these oscillations is close to the frequency of the qubit. For example, the readout resonator affects pulses from control / measuring instruments at the readout resonator frequency. This pulse acts as a measurement that decoheres with the qubit and collapses it into a "one" or "zero" state, thereby imparting a phase shift to the measurement pulse.

[0047] Coupled resonators can exist between qubits, allowing different qubits to be coupled together to implement quantum logic gates. Coupled resonators are typically structurally similar to readout resonators because they include transmission lines with capacitive connections to ground on both sides, which also leads to oscillations within the coupled resonator. When a qubit is implemented as a transmon, each side of the coupled resonator is coupled (e.g., capacitively or inductively) to the corresponding qubit by being sufficiently close to it (e.g., its capacitor). Since each side of the coupled resonator has coupling with a corresponding different qubit, the two qubits are coupled together through the coupled resonator. In this way, there is interdependence in the states between the coupled qubits, allowing the coupled resonator to control the state of another qubit using the state of the first qubit. Entanglement occurs when the interaction between two qubits is such that the states of the two qubits cannot be specified independently, but only for the entire system. In this way, the states of the two qubits are linked together, such that a measurement of one of these qubits causes the state of the other qubit to collapse.

[0048] Typical materials for fabricating interconnects include, but are not limited to, niobium (Nb), aluminum (Al), niobium nitride (NbN), titanium nitride (TiN), and niobium titanium nitride (NbTiN), which are sometimes referred to herein as superconductors. It will be understood that other suitable materials with superconducting properties may also be used.

[0049] The applicant has recognized that improvements can be made to the structure and fabrication of superconducting devices to enhance the overall computational power and reliability of quantum computers, and particularly to improve superconducting structures. Among other things, achieving low error rates and better reliability is related to accurately manipulating qubit states and performing sequential operations that provide consistent results rather than simply unreliable data. Quantum technologies remain an area of ​​development, and providing structures with highly predictable and more desirable performance remains a challenge.

[0050] In one respect, the teaching herein is based on the applicant's understanding that protecting specific interfaces of superconductors used in superconducting quantum circuits from oxidation can improve the decoherence and signal integrity of superconducting qubits. The applicant has further recognized that directly applying conventional integrated circuit techniques to protect materials from oxidation in superconducting quantum circuits may be ineffective due to the unique challenges posed by quantum circuits, which are not present in classical computing architectures. Therefore, the embodiments disclosed herein are further based on the understanding that the unique problems of quantum circuits have been considered when evaluating the suitability of conventional integrated circuit techniques for constructing superconducting quantum circuits, and particularly for selecting materials and processes for protecting superconducting materials from oxidation in such circuits.

[0051] The surface of superconductors in quantum circuits contains potentially lossy materials due to oxide growth or surface contamination that degrade resonator quality. In response, Figure 1A A first superconductor layer 104 is shown on substrate 102. Surface oxide 106 can be grown naturally and is therefore sometimes referred to herein as native oxide. Figure 1B As shown, when another superconductor layer 108 is placed on top (e.g., in the formation of a Josephson junction), there is a residual oxide 107.

[0052] Contact between superconducting elements (e.g., capacitor pads and Josephson junction electrodes, which can be implemented by superconducting layers 104 and 108) is significant for good qubit performance. However, residual oxides or surface contamination 107 in this contact region can reduce qubit coherence. For example, semiconductor processes often involve different chambers for different depositions, and vacuum is often broken, which can immediately produce the native oxide 107 described herein. One way to remove the native oxide 107 is by in-situ cleaning (e.g., ion milling, sputtering cleaning, vacuum baking, vapor HF, etc.). However, there are limitations on the level of cleanliness that can be achieved. For example, vapor HF is typically not done in a vacuum (but can be), so the oxides are removed in air for a period of time before being loaded into the deposition chamber. Therefore, oxide formation can be limited but not eliminated. As for ion milling, it is performed in a vacuum, but since it is a sputtering removal of oxides, it may also lead to some redeposition.

[0053] Therefore, the teachings herein provide methods and systems for mitigating losses in contact superconductors of quantum circuits. The techniques described herein can be implemented in several ways. Exemplary implementations are provided below with reference to the accompanying figures.

[0054] Example superconducting structure

[0055] See now Figure 2 The figure is a simplified cross-sectional view of the superconducting structure 200 consistent with the illustrative embodiment. The superconducting structure 200 can be used to implement various superconducting circuits, including but not limited to Josephson junctions (JJs), superconducting capacitors, circulators, isolators, amplifiers, filters, etc. For the sake of clarity in this discussion, the superconducting structure will sometimes be discussed in the context of a JJ, while it will be understood that other superconducting structures are also supported.

[0056] The superconductor structure 200 may include a substrate 202. In various embodiments, the substrate 202 may include any suitable material or combination of materials, such as doped or undoped silicon, glass, dielectric, etc. For example, the substrate may include, for instance, a silicon-on-insulator (SOI) structure with a buried insulating layer, or, for instance, a bulk material substrate with appropriately doped regions, commonly referred to as a well. In another embodiment, the substrate may be silicon, with silicon oxide, nitride, or any other insulating film on top.

[0057] Other materials that can be used as substrates include, but are not limited to, sapphire, alumina, germanium, gallium arsenide (GaAs) or any other III-V periodic table compound, indium phosphide (InP), silicon carbide (SiC), superconducting alloys of silicon and germanium, quartz, etc. Thus, as used herein, the term substrate 202 refers to a base on which different superconducting structures can be constructed.

[0058] A first superconducting metal 204 is present on top of a substrate 202. In one embodiment, the first metal layer 204 is niobium (Nb). A second metal layer 208 is present on top of the first metal layer 204. In one embodiment, the second metal layer 208 is aluminum (Al). A superconducting alloy 206 of the first and second metal layers exists between the first metal layer 204 and the second metal layer 208. For example, this superconducting alloy may be niobium aluminide (Al3Nb). As used herein, the term niobium aluminide includes all stable aluminides present in the Nb-Al diagram. Niobium aluminide refers to any alloy of Al and Nb. Three phases are possible here: Al3Nb, AlNb2, and Nb3Al (i.e., only three niobium aluminide phases present in the binary Nb-Al equilibrium phase diagram). Note that in embodiments with very thin films, it is possible to form an unstable Al-Nb phase with a crystal structure and composition not found in the bulk phase.

[0059] In various embodiments, different grain orientations of Al3Nb can be provided based on temperature and time conditions, which will be discussed in more detail later. Notably, there is no oxide layer between the superconducting alloy and the first metal layer 204 and the superconducting alloy 206. Furthermore, in one embodiment, there is no oxide layer between the second metal layer 208 and the superconducting alloy 206.

[0060] Superconducting circuit elements (e.g., but not limited to, JJs, resonators, coupling pads, capacitors, gate electrodes, etc.) are typically covered with a second conductor. In one embodiment, the second conductor (i.e., the second metal layer 208) is deposited on the first conductor (i.e., the first metal layer 204) before the first metal layer 204 is exposed to air to prevent oxidation on the first conductor (i.e., the first metal layer 204).

[0061] Alternatively or additionally, the top surface of the first metal layer 204 is thoroughly cleaned before depositing the second metal layer 208. The two conductive layers, comprising the first metal layer 204 and the second metal layer 208, are alloyed at their interface to create an electrical path from the substrate conductor (i.e., the first metal layer 204) through the superconducting alloy 206 and into the JJ electrode. Figure 2 The interface alloy 206 is represented by a second metal layer 208. Because there is no oxide layer between metal layers 204 and 208, and between the superconducting alloy 206, the quality of the contact is improved (e.g., the contact between the capacitor pad (represented by the second metal layer 208) and the JJ 208 lead to reduce losses), resulting in a more desirable JJ. In different embodiments, metal layer 208 may be a metal used only to form the interface alloy 206, in which case the electrode is deposited later. Alternatively, metal layer 208 may also be one (or even one double-layer electrode) that is later annealed to form the superconducting alloy 206. In some embodiments, the superconducting circuit is established prior to annealing to form the interface alloy 206.

[0062] Exemplary methods for superconducting structures

[0063] Based on the preceding description of example superconductor structure 200, it may be helpful to discuss its fabrication process. Therefore, Figures 3A to 3D The various steps involved in fabricating the superconductor structure, consistent with the illustrative embodiments, are shown. More precisely, Figure 3A A semiconductor structure 300A is shown prior to the formation of a superconducting alloy between the metal layers, consistent with the illustrative embodiment. In various embodiments, (i) before air exposure or (ii) after air exposure, the substrate first metal layer 304 is covered with a second metal layer 308, thereafter, native metal oxides are sufficiently removed before the second metal layer 308 is placed on top, collectively referred to herein as native metal oxide rejection. For example, in various embodiments, the second metal layer 308 is placed on top of the first metal layer 304 before oxidation occurs (e.g., when the chip is in a controlled environment (such as a vacuum), or even when moving from one deposition chamber to another) or by sufficiently cleaning the top surface of the first metal layer 304 to remove any oxidation on the first metal layer 304 before the second metal layer 308 is placed on top of the first metal layer 304.

[0064] In various embodiments, this cleaning of the oxide from the top surface of the first metal layer 304 can be performed by wet cleaning or dry cleaning (preferably). Such dry cleaning may include, but is not limited to, ion milling, pre-sputtering, or other suitable techniques to remove the oxide from the top of the first metal layer 304. This results in an oxide-free interface. Consequently, the interface between the first metal layer 304 and the second metal layer 308 is substantially oxide-free. A superconducting alloy is then formed between these two metal layers 304 and 308, as discussed in more detail below.

[0065] Figure 3B A semiconductor structure 300B is shown, consistent with the illustrative embodiment, after a superconducting alloy 306 is formed between a first metal layer 304 and a second metal layer 308. In one embodiment, the superconducting alloy is formed by annealing. Other methods of generating the superconducting alloy 306 between the first metal layer 304 and the second metal layer 308 include (but are not limited to) a predetermined amount of pressure, and / or an increase in bias voltage during the deposition process of the second metal layer 308.

[0066] In one embodiment, the first metal layer 304 is niobium (Nb), the second metal layer 308 is aluminum (Al), and the alloy 306 formed between the two metals is niobium aluminide Al3Nb(002), wherein (002) is the 110 plane of the superconducting alloy 306 relative to the Nb and in this case is the lattice orientation of the surface of the substrate.

[0067] In different embodiments, depending on the different superconducting structures to be generated, the second metal layer 308 can be retained or etched away by wet or dry (plasma) etching. Thus, the unreacted second metal layer 308 can be retained or removed, selectively leaving the metal alloy 306 exposed, which protects the first metal layer 304 from reacting with the surrounding environment. By generating the metal alloy 306, the first metal layer 304 is protected from oxidation or other elements that could affect the performance of the superconducting device, thereby improving device performance.

[0068] Figure 3C and 3DSemiconductor structures 300C and 300D, consistent with illustrative embodiments, are shown. These semiconductor structures include electrodes 320 on top of a second metal layer 308 and electrodes 320 directly on a superconducting alloy 306. For example, the junction electrode 320 may belong to a junction junction (JJ). The JJ can be formed on a capacitor (i.e., by subtractive etching) or on a substrate connected to the capacitor via the junction electrode (i.e., a Dolan shadow structure). For example, a three-layer junction process can be used to fabricate JJ logic devices and integrated circuits. For example, the junction electrode 320 will have a thin oxide layer on top, which will be covered by another metal layer to provide a three-layer configuration (e.g., a JJ on a capacitor).

[0069] Now for reference Figure 4 , Figure 4 The formation of a superconducting alloy 406 with different orientations based on annealing temperature, consistent with the illustrative embodiments, is illustrated. For purposes of discussion and not limitation, the original semiconductor structure 400A has a first metal layer 404 containing niobium (Nb) and a second metal layer 408 containing aluminum (Al) disposed on top of a substrate 402. X-ray diffraction intensity patterns 400C and 400D (reference structure 400B) show that superconducting alloy 406 is formed at the interface between the niobium layer 404 and the aluminum layer 408 at a temperature of approximately 500°C. The superconducting alloy 406 (i.e., Al3Nb) has a lattice structure that can be oriented differently from the substrate based on different annealing temperatures. The desired orientation for optimal contact can be controlled by the annealing conditions.

[0070] Different temperatures result in different alloy thicknesses. For example, thin layers of Al3Nb(002) are formed below 400°C with long annealing times and will grow over time. As the temperature increases (e.g., 650°C), the superconducting alloy 406 begins to include grains exhibiting different orientations (Al3Nb(112) and (101)) as the grains in the film become more randomly oriented. In some embodiments, similar results can be achieved with different combinations of temperature and time. For example, lower temperatures but longer annealing times (sometimes referred to herein as isothermal annealing) can also be used to achieve the superconducting alloy Al3Nb(002). The applicant has determined that annealing temperatures at the Nb / Al interface from 350°C to 500°C produce superconducting alloy Al3Nb with 002 alignment relative to the underlying Nb110 plane.

[0071] Note that Nb 404 and Al 408, when in direct contact, form a superconducting alloy 406 at temperatures above 350°C. Alloying Nb 404 and Al 408 will create an electrical path from Nb to Al through the Nb-Al alloy 406. In one embodiment, oxygen is absent at the interface between Nb 404 and the Nb-Al alloy 406, and only some oxygen is present on the surface of the Al layer 408. Therefore, no residual Nb oxide causes descaling, significantly increasing the performance of the superconducting device.

[0072] The foregoing discussion generally concerns avoiding an oxide layer between the first metal layer (e.g., Nb) and the second metal layer (e.g., Al). It should be noted that superconducting alloys can still form under certain conditions when native niobium oxide is present between these two metal layers, but not as rapidly. For this, see [link to relevant documentation]. Figures 5A to 5D This provides different processing steps consistent with the illustrative embodiments for generating a superconducting structure, which includes an initial oxide layer between first and second metal layers 504 and 508. For example... Figure 5A As shown, a first metal layer 504 (e.g., Nb) is present on top of the substrate 502. A second metal layer (e.g., Al) 508 is present on top of the first metal layer 504. A native oxide layer (e.g., niobium oxide) 505 is present between the metal layers 508 and 504.

[0073] Figure 5B The diagram shows the migration of native oxide 505 from the niobium surface to the surface of the superconducting alloy 506 during alloy formation (e.g., by annealing), represented by oxide layer 507.

[0074] Figure 5C Selective etching is shown, and the second metal layer 508 and oxide layer 510 can be removed. In various embodiments, both the second metal layer 508 and oxide layer 507 can be removed simultaneously or separately by different etching steps. An electrode (e.g., Josephson) 520 can then be deposited on top of the superconducting alloy 506. For example, selective etching and aluminum JJ fabrication result in an electrical path from Nb to Al via the Nb and Al alloy without niobium oxide defects.

[0075] Therefore, the applicant has determined that while it is possible to achieve a superconducting alloy between these metal layers without an oxide (e.g., niobium oxide) layer between them, and without corrosive protection and / or removal of the oxide layer between the first and second metal layers 504 and 508, such a process requires significantly more manufacturing time and / or temperature to produce the protective alloy 506. While the discussion herein may refer to the idealized term "without oxides," it should be understood that it includes the meaning that it is essentially oxygen-free, making detection with known tools extremely difficult.

[0076] in conclusion

[0077] Various embodiments of this teaching have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0078] While the content considered to be the best state and / or other instances has been described above, it should be understood that various modifications may be made therein, and the subject matter disclosed herein can be implemented in different forms and instances, and the teachings can be applied to many applications, of which only some have been described herein. The appended claims are intended to claim protection for any and all applications, modifications, and variations falling within the true scope of the teachings herein.

[0079] The components, steps, features, purposes, benefits, and advantages discussed herein are illustrative only. They, and the discussions associated with them, are not intended to limit the scope of protection. While various advantages have been discussed herein, it will be understood that not all embodiments are necessarily required to include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, amplitudes, sizes, and other specifications set forth in this specification (including in the following claims) are approximate and imprecise. They are intended to have a reasonable range of functionality associated with them and consistent with functionality customary in the art to which they pertain.

[0080] Many other embodiments are also conceived. These include embodiments with fewer, additional, and / or different components, steps, features, purposes, benefits, and advantages. These also include embodiments in which components and / or steps are arranged and / or ordered differently.

[0081] Although the foregoing has been described in conjunction with exemplary embodiments, it should be understood that the term "exemplary" means only as an example, and not the best or optimal. Nothing stated or shown beyond what is immediately stated above is intended or should be construed as causing any contribution or public equivalent of any component, step, feature, object, benefit, advantage, or advantage, whether or not it is stated in the claims.

[0082] It should be understood that the terms and expressions used herein have their general meanings as assigned to their respective corresponding queries and fields of study, unless otherwise specified herein. Relational terms such as "first" and "second" may be used merely to distinguish one entity or action from another, without necessarily requiring or implying any actual such relationship or order between these entities or actions. The terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but may also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element beginning with "an" or "a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes that element.

[0083] An abstract of this disclosure is provided to allow the reader to quickly determine the nature of this technical disclosure. It is submitted under the understanding that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, as can be seen from the detailed description above, various features are combined in various embodiments for the purpose of simplification. The method of this disclosure should not be construed as reflecting an intention to have more features than expressly recited in each claim of the claimed embodiments. Rather, as reflected in the following claims, the inventive subject matter lies in fewer than all features of a single disclosed embodiment. Therefore, the following claims are thereby incorporated into the detailed description, wherein each claim is independently claimed as a separate subject matter.

Claims

1. A superconducting device, comprising: Substrate; A first metal layer is placed on top of the substrate; A second metal layer is placed on top of the first metal layer; as well as A superconducting alloy between the first metal layer and the second metal layer, wherein the superconducting alloy is located between the first metal layer and the second metal layer. The superconducting alloy is in direct contact with the first metal layer. in: The first metal layer is niobium (Nb); The second metal layer is aluminum (Al); and The superconducting alloy is Al3Nb.

2. The superconducting device according to claim 1, wherein, The grain orientation of the superconducting alloy is aligned with the (002) plane parallel to the surface of the substrate.

3. The superconducting device according to claim 1 or 2, further comprising an electrode on top of the second metal layer.

4. The superconducting device according to claim 3, wherein the electrode is a Josephson junction electrode.

5. The superconducting device according to any one of claims 1, 2 and 4, wherein the superconducting alloy is operable to protect the first metal layer from oxidation or contamination that could affect the performance of the superconducting device.

6. A method for manufacturing a superconducting device, comprising: Provide substrate; A first metal layer is provided on top of the substrate; Reject oxidation of the top of the first metal layer; A second metal layer is deposited on top of the first metal layer; as well as A superconducting alloy of the first metal layer and the second metal layer is formed between the first metal layer and the second metal layer, wherein the superconducting alloy is in direct contact with the first metal layer. in: The first metal layer is niobium (Nb); The second metal layer is aluminum (Al); and The superconducting alloy is Al3Nb.

7. The method according to claim 6, wherein, Rejecting oxidation of the top surface of the first metal layer includes placing the second metal layer on top of the first metal layer after depositing the first metal layer and before exposing the top surface of the first metal layer to air.

8. The method according to claim 7, wherein, Rejecting oxidation of the top surface of the first metal layer further includes: maintaining the superconducting device in a vacuum between the deposition of the first metal layer and the deposition of the second metal layer.

9. The method according to any one of claims 6 to 8, wherein rejecting oxidation of the top surface of the first metal layer comprises: After cleaning the top surface of the first metal layer, the second metal layer is deposited on top of the first metal layer to remove any oxidation therefrom.

10. The method according to any one of claims 6 to 8, further comprising etching away the second metal layer after the superconducting alloy is produced.

11. The method according to any one of claims 6 to 8, wherein the production of the superconducting alloy comprises annealing the first metal layer and the second metal layer at a predetermined temperature.

12. The method according to any one of claims 6 to 8, wherein the superconducting alloy creates an electrical path from the first metal layer to the second metal layer.

13. The method according to any one of claims 6 to 8, wherein, Depending on the annealing temperature of the first metal layer and the second metal layer, the orientation of the superconducting alloy lattice is (002), (112) or (101).

14. The method according to any one of claims 6 to 8, further comprising depositing an electrode on top of the second metal layer.

15. The method of claim 14, wherein the electrode is a Josephson junction electrode.

16. The method according to any one of claims 6 to 8 and 15, further comprising: Remove the second metal layer; as well as An electrode is deposited on top of the superconducting alloy.

17. A method for manufacturing a superconducting device, comprising: Provide substrate; A first metal layer is provided on top of the substrate; An initial oxide layer is provided on the top surface of the first metal layer; A second metal layer is deposited on top of the first metal layer; A superconducting alloy of the first metal layer and the second metal layer is formed between the first metal layer and the second metal layer; as well as During the formation of the superconducting alloy, the initial oxide layer is moved to the top surface of the superconducting alloy. in: The first metal layer is niobium (Nb); The second metal layer is aluminum (Al); and The superconducting alloy is Al3Nb.

18. The method of claim 17, further comprising: Remove the initial oxide and the second metal layer from the top surface of the superconducting alloy; as well as An electrode is deposited on top of the superconducting alloy.

Images