A power supply current detection device

Abstract

This invention proposes a power supply current detection device, relating to the field of current detection modules. The module includes a sampling circuit and a detection circuit. The sampling circuit includes an input terminal, a first output terminal, and a second output terminal. Power is output from the first output terminal and connected to the detection circuit. The second output terminal outputs a load voltage and is connected to the device under test (DUT). The detection circuit outputs a judgment logic value based on the input differential voltage. This judgment logic value characterizes the path state of the DUT, which can be a short circuit, an open circuit, or a normal state. By obtaining the path state of the DUT, corresponding protection measures can be taken promptly. This avoids the influence of current noise on the detection process. Furthermore, the load voltage output from the second output terminal of the sampling circuit can power different DUTs, and the power supply can be adjusted according to the rated voltage of the DUT, increasing the voltage range and flexibility in load application.

Description

Technical Field

[0001] This invention relates to the field of current detection modules, and more specifically, to a power supply current detection device for detecting short circuits, normal operation, and open circuits in antennas, low-noise amplifiers, etc., used in the radio frequency field. Background Technology

[0002] In the field of radio frequency circuit applications, devices such as antennas and low-noise amplifiers need to be able to detect the power supply current state when they are open-circuited, short-circuited, or operating normally. Existing technologies cannot detect the power supply current because current noise can affect the detection results. Summary of the Invention

[0003] The purpose of this invention is to provide a power supply current detection device to solve the problems existing in the background art.

[0004] The embodiments of the present invention are implemented as follows:

[0005] This application provides a power supply current detection device, including a sampling circuit and a detection circuit, which are connected together;

[0006] The sampling circuit includes an input terminal, a first output terminal, and a second output terminal. The input terminal is used to connect to the power supply and receive the power supply voltage. The power supply voltage output by the power supply is converted into a differential input voltage by the sampling circuit and output from the first output terminal, which is connected to the detection circuit. The second output terminal outputs the load voltage and is connected to the device under test (DUT) to supply power to the DUT.

[0007] The detection circuit is used to output a logic value based on the input differential voltage. The logic value represents the circuit state of the component under test, which can be a short circuit, an open circuit, or a normal state.

[0008] The beneficial effects of this invention are as follows: the differential input voltage generated by the sampling circuit is connected to the detection circuit. The detection circuit obtains the circuit status of the device under test by detecting and judging the differential input voltage, thereby taking corresponding protective measures for the device under test in a timely manner; it avoids the influence of current noise on the detection when detecting current; and the load voltage output by the second output terminal of the sampling circuit can supply power to different devices under test, and the power supply can be adjusted according to the rated voltage of the device under test, increasing the voltage range and the flexibility of load application.

[0009] Based on the above technical solution, the present invention can be further improved as follows.

[0010] Furthermore, the sampling circuit also includes a protection switch and a resistor. One end of the protection switch is connected to the power supply, and the other end of the protection switch is connected to one end of the resistor. The other end of the resistor serves as the second output terminal, and the two ends of the resistor together form the first output terminal.

[0011] The beneficial effect of adopting the above-mentioned further solution is that it connects the component under test with the detection circuit, that is, it connects the power supply through the same sampling circuit, so as to achieve the purpose of detecting the circuit status of the component under test.

[0012] Furthermore, the aforementioned detection circuit includes an adjustment network, multiple MOSFETs, and a logic module;

[0013] The regulating network includes at least two resistor networks. The input terminals of the regulating network include an input P terminal and an input N terminal. One end of the input P terminal and one end of the input N terminal are respectively connected to the two ends of the first output terminal. The other end of the input P terminal and the other end of the input N terminal are respectively connected to the input terminals of the two resistor networks.

[0014] Furthermore, for each resistor network described above, the resistor network includes resistors R1, R2, and R3. Resistor R1 is connected to a switching transistor M1, and the switching transistor M1 is connected to resistor R1. Resistor R2 is connected to a switching transistor M2, and the switching transistor M2 is connected to resistor R2. Resistor R3 is connected to a switching transistor M3, and the switching transistor M3 is connected to resistor R3. Resistors R1, R2, and R3 are connected in series.

[0015] Furthermore, the aforementioned plurality of MOS transistors includes at least four PMOS transistors and at least four NMOS transistors. The at least four PMOS transistors include PMOS transistor S1, PMOS transistor S2, PMOS transistor S3 and PMOS transistor S4, and the at least four NMOS transistors include NMOS transistor S1, NMOS transistor S2, NMOS transistor S3 and NMOS transistor S4.

[0016] The source (S) terminals of PMOS transistors S1 and S2 are each connected to the output terminals of at least two resistor networks. The drain (D) terminal of PMOS transistor S1 is connected to the source terminal of PMOS transistor S3, and the drain terminal of PMOS transistor S2 is connected to the source terminal of PMOS transistor S4. Similarly, the source terminal of NMOS transistor S1 is connected to the drain terminal of PMOS transistor S3, the source terminal of NMOS transistor S2 is connected to the drain terminal of PMOS transistor S4, and the drain terminal of NMOS transistor S1 is connected to the source terminal of NMOS transistor S3. The source (S) of NMOS transistor S4 is connected, and the drain (D) of NMOS transistor S3 is connected to the drain of NMOS transistor S4. The gates (G) of PMOS transistors S1 and S2 are both connected to the source (S) of NMOS transistor S1, and the gates (G) of PMOS transistors S3 and S4 are both connected to the bias voltage. The gates (G) of NMOS transistors S1, S2, S3, and S4 are all connected to the bias voltage. The drain (D) of PMOS transistor S4 is connected to the logic module.

[0017] Furthermore, the above logic module includes a buffer, a level shifter, and a logic circuit connected in sequence; the input terminal of the buffer is connected to the drain of the PMOS transistor S4, and the output terminal of the buffer is connected to the level shifter.

[0018] A buffer is used to convert the voltage signal of the differential input voltage into a digital signal and transmit the digital signal to a level converter;

[0019] A level converter is used to receive digital signals transmitted through a buffer and convert the voltage value of the digital signal into a voltage value that meets the requirements of the logic circuit.

[0020] A logic circuit is used to receive voltage values ​​that meet the requirements of the logic circuit, perform logical judgments on the voltage values ​​to obtain judgment results, and generate judgment logic values ​​based on the judgment results.

[0021] The beneficial effect of adopting the above-mentioned further solution is that it can obtain the circuit status of the component under test, thereby taking corresponding protective measures for the component under test in a timely manner. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a connection diagram of the power supply current detection module in an embodiment of the present invention;

[0024] Figure 2This is a schematic diagram of the connection of the sampling circuit in an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of the resistor network connection in an embodiment of the present invention;

[0026] Figure 4 This is a schematic diagram of the connection of the detection circuit in an embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0028] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0029] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0030] Example

[0031] This embodiment provides a power supply current detection device, including a sampling circuit and a detection circuit, which are connected together;

[0032] The sampling circuit includes an input terminal, a first output terminal, and a second output terminal. The input terminal is used to connect to the power supply and receive the power supply voltage. The power supply voltage output by the power supply is converted into a differential input voltage by the sampling circuit and output from the first output terminal, which is connected to the detection circuit. The second output terminal outputs the load voltage and is connected to the device under test (DUT) to supply power to the DUT.

[0033] The sampling circuit provides power to the device under test and converts the power supply voltage into a differential input voltage, which is then input to the detection circuit. The detection circuit outputs a judgment logic value based on the input differential input voltage.

[0034] Optionally, the above sampling circuit also includes a protection switch and a resistor. One end of the protection switch is connected to the power supply, and the other end of the protection switch is connected to one end of the resistor. The other end of the resistor serves as the second output terminal, and the two ends of the resistor together form the first output terminal.

[0035] The power supply voltage output from the power supply is connected to the input terminal of the sampling circuit, see [link / reference]. Figure 2 The power supply voltage is connected to the left side of the protection switch. The power supply voltage passes through the protection switch and enters the resistor. The power supply voltage through the resistor is output to the device under test to power the device under test. The two ends of the resistor can form a differential input voltage and be connected to the detection circuit.

[0036] The detection circuit is used to output a logic value based on the input differential voltage. The logic value represents the circuit state of the component under test, which can be a short circuit, an open circuit, or a normal state.

[0037] Optionally, the above detection circuit includes a regulating network, multiple MOSFETs, and a logic module;

[0038] The regulating network includes at least two resistor networks. The input terminals of the regulating network include an input P terminal and an input N terminal. One end of the input P terminal and one end of the input N terminal are respectively connected to the two ends of the first output terminal. The other end of the input P terminal and the other end of the input N terminal are respectively connected to the input terminals of the two resistor networks.

[0039] In this configuration, the input P and input N terminals of the regulating network are connected to the two ends of the resistor in the sampling circuit, thus enabling the differential input voltage to be applied to the input P and input N terminals of the regulating network. (See [link to relevant documentation]). Figure 3 .

[0040] Specifically, the regulating network may include two resistor networks, and the input terminals of the two resistor networks are respectively connected to the input P terminal and the input N terminal, thereby realizing the differential input voltage being connected to the two resistor networks.

[0041] Optionally, for each resistor network described above, the resistor network includes resistors R1, R2, and R3. Resistor R1 is connected to a switching transistor M1, and the switching transistor M1 is connected to resistor R1. Resistor R2 is connected to a switching transistor M2, and the switching transistor M2 is connected to resistor R2. Resistor R3 is connected to a switching transistor M3, and the switching transistor M3 is connected to resistor R3. Resistors R1, R2, and R3 are connected in series.

[0042] The connection diagram of the resistor network is shown below. Figure 3 As shown, Figure 3The IN terminal in the circuit connects to the input P terminal and the input N terminal, meaning that the two IN terminals of the two resistor networks are respectively connected to the input P terminal and the input N terminal of the regulating network; the OUT terminal is the output terminal of the regulating network or the two resistor networks.

[0043] Optionally, the plurality of MOSFETs includes at least four PMOS transistors and at least four NMOS transistors. The at least four PMOS transistors include PMOS transistor S1, PMOS transistor S2, PMOS transistor S3, and PMOS transistor S4, and the at least four NMOS transistors include NMOS transistor S1, NMOS transistor S2, NMOS transistor S3, and NMOS transistor S4. The connections between the four PMOS transistors and the four NMOS transistors and the regulation network are as follows: Figure 4 As shown;

[0044] The source (S) terminals of PMOS transistors S1 and S2 are each connected to the output terminals of at least two resistor networks. The drain (D) terminal of PMOS transistor S1 is connected to the source terminal of PMOS transistor S3, and the drain terminal of PMOS transistor S2 is connected to the source terminal of PMOS transistor S4. Similarly, the source terminal of NMOS transistor S1 is connected to the drain terminal of PMOS transistor S3, the source terminal of NMOS transistor S2 is connected to the drain terminal of PMOS transistor S4, and the drain terminal of NMOS transistor S1 is connected to the source terminal of NMOS transistor S3. The source (S) of NMOS transistor S4 is connected, and the drain (D) of NMOS transistor S3 is connected to the drain of NMOS transistor S4. The gates (G) of PMOS transistors S1 and S2 are both connected to the source (S) of NMOS transistor S1, and the gates (G) of PMOS transistors S3 and S4 are both connected to the bias voltage. The gates (G) of NMOS transistors S1, S2, S3, and S4 are all connected to the bias voltage. The drain (D) of PMOS transistor S4 is connected to the logic module.

[0045] The adjustment network can be composed of two resistor networks, with the out terminals of the two resistor networks connected to the source (S) terminals of PMOS transistors S1 and S2, respectively. (See [link to relevant documentation]). Figure 4 The part of the regulating network that connects to the source (S) of PMOS transistor S1 and the source (S) of PMOS transistor S2 is the output terminal of the regulating network, and the output terminal of the regulating network can include the out terminals of two resistor networks.

[0046] Specifically, of the four PMOS transistors and four NMOS transistors, two PMOS transistors and two NMOS transistors are connected to two resistor networks respectively, and the four PMOS transistors and four NMOS transistors are powered by a bias voltage; the drain of PMOS transistor S4 or the drain of NMOS transistor S2 serves as the output terminal of the four PMOS transistors and four NMOS transistors and is connected to the logic module.

[0047] Optionally, the logic module includes a buffer, a level shifter, and a logic circuit connected in sequence; the input terminal of the buffer is connected to the drain of the PMOS transistor S4, and the output terminal of the buffer is connected to the level shifter.

[0048] A buffer is used to convert the voltage signal of the differential input voltage into a digital signal and transmit the digital signal to a level converter;

[0049] The buffer is a voltage buffer, specifically used in the analog-to-digital converter to provide a reference voltage with driving capability and to realize the analog-to-digital conversion process, that is, to convert analog quantities into digital quantities. In this application, it is manifested as converting the voltage signal of the differential input voltage into a digital signal; its performance requirement is to have a stable voltage output while providing current output and input.

[0050] A level converter is used to receive digital signals transmitted through a buffer and convert the voltage value of the digital signal into a voltage value that meets the requirements of the logic circuit.

[0051] The level converter can be a voltage conversion device. Level conversion is divided into unidirectional and bidirectional conversion, and also into single-supply and dual-supply conversion. Dual-supply conversion uses a dual-rail scheme to meet the performance requirements in various aspects. With the introduction of low-voltage logic, the input / output logic inconsistency often occurs in the system, thus increasing the complexity of system design. In this application, the level converter is specifically used to convert the voltage value of digital signals into a voltage value that meets the requirements of the logic circuit. For example, when a 1.8V digital circuit communicates with an analog circuit operating at 3.3V, the conversion between the two levels needs to be solved first, which requires a level converter.

[0052] A logic circuit is used to receive voltage values ​​that meet the requirements of the logic circuit, perform logical judgments on the voltage values ​​to obtain judgment results, and generate judgment logic values ​​based on the judgment results.

[0053] The logic circuit can include multiple digital circuits for logical judgment. After receiving a voltage value that meets the requirements of the logic circuit, the logic circuit performs logical judgment on the voltage value to obtain a judgment result and generates a judgment logic value based on the judgment result. For example, generating a judgment logic value of 0 indicates that the circuit under test is in a short circuit state; generating a judgment logic value of 1 indicates that the circuit under test is in a normal state; generating a judgment logic value of x indicates that the circuit under test is in an open circuit state. In this way, the circuit status of the component under test can be obtained, so as to take corresponding protection measures for the component under test in a timely manner.

[0054] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A power supply current detecting device, characterized by comprising: It includes a sampling circuit and a detection circuit, wherein the sampling circuit and the detection circuit are connected. The sampling circuit includes an input terminal, a first output terminal, and a second output terminal. The input terminal is used to connect to a power supply and receive the power supply voltage. The power supply voltage output by the power supply is converted into a differential input voltage by the sampling circuit and output from the first output terminal, which is connected to the detection circuit. The second output terminal outputs the load voltage and is connected to the device under test (DUT) to supply power to the DUT. The detection circuit is used to output a judgment logic value based on the input differential voltage. The judgment logic value represents the circuit state of the component under test, which is a short circuit state, an open circuit state, or a normal state. The sampling circuit also includes a protection switch and a resistor. One end of the protection switch is connected to the power supply, and the other end of the protection switch is connected to one end of the resistor. The other end of the resistor serves as the second output terminal, and the two ends of the resistor together form the first output terminal. The detection circuit includes an adjustment network, multiple MOSFETs, and a logic module connected in sequence. The regulating network includes at least two resistor networks. The input terminals of the regulating network include an input P terminal and an input N terminal. One end of the input P terminal and one end of the input N terminal are respectively connected to the two ends of the first output terminal. The other end of the input P terminal and the other end of the input N terminal are respectively connected to the input terminals of the two resistor networks. The logic module includes a buffer, a level converter, and a logic circuit connected in sequence; the output of the buffer is connected to the level converter. The buffer is used to convert the voltage signals output by the plurality of MOS transistors into digital signals and transmit the digital signals to the level converter; The level converter is used to receive the digital signal transmitted by the buffer and convert the voltage value of the digital signal into a voltage value that meets the requirements of the logic circuit. The logic circuit is used to receive a voltage value that meets the requirements of the logic circuit, perform a logical judgment on the voltage value to obtain a judgment result, and generate a judgment logic value based on the judgment result.

2. The power supply current detection apparatus according to claim 1, wherein For each of the resistor networks, the resistor network includes resistors R1, R2 and R3, resistor R1 is connected in parallel with a switching transistor M1, resistor R2 is connected in parallel with a switching transistor M2, resistor R3 is connected in parallel with a switching transistor M3, and resistors R1, R2 and R3 are connected in series.

3. The power current detection device of claim 1, wherein The plurality of MOS transistors include at least four PMOS transistors and at least four NMOS transistors, wherein the at least four PMOS transistors include PMOS transistor S1, PMOS transistor S2, PMOS transistor S3 and PMOS transistor S4, and the at least four NMOS transistors include NMOS transistor S1, NMOS transistor S2, NMOS transistor S3 and NMOS transistor S4; The source (S) terminals of PMOS transistors S1 and S2 are respectively connected to the output terminals of at least two of the resistor networks. The drain (D) terminal of PMOS transistor S1 is connected to the source (S) terminal of PMOS transistor S3, and the drain (D) terminal of PMOS transistor S2 is connected to the source (S) terminal of PMOS transistor S4. Similarly, the source (S) terminal of NMOS transistor S1 is connected to the drain (D) terminal of PMOS transistor S3, the source (S) terminal of NMOS transistor S2 is connected to the drain (D) terminal of PMOS transistor S4, and the drain (D) terminal of NMOS transistor S1 is connected to the source (S) terminal of NMOS transistor S3. The source (S) terminal of NMOS transistor S4 is connected, and the drain (D) terminal of NMOS transistor S3 is connected to the drain terminal of NMOS transistor S4. The gate (G) terminals of PMOS transistors S1 and S2 are both connected to the source (S) terminal of NMOS transistor S1, and the gate (G) terminals of PMOS transistors S3 and S4 are both connected to a bias voltage. The gate (G) terminals of NMOS transistors S1, S2, S3, and S4 are all connected to a bias voltage. The drain (D) terminal of PMOS transistor S4 is connected to the logic module.

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