An airborne radar signal processing system architecture

Abstract

The application discloses an airborne radar signal processing system architecture, comprising a radio frequency processing skin unit, a network exchange unit and a signal processing unit; a combination of a multi-core general-purpose CPU and a GPU is used as an embedded supercomputing unit in the radar signal processing system, replaces a traditional airborne DSP array, and provides computing power support for a radar processing algorithm; an Ethernet RDMA communication mode is applied, the transmission bandwidth of the radar signal processing platform is increased, multi-channel and multi-pulse subarray data are all sent to the signal processing unit with the CPU+GPU as the core through the network exchange unit, a pingpong transmission-operation pipeline is designed based on the RDMA mode, and the high-performance operation advantages of the platform are exerted under the condition that the CPU resource occupation in the embedded supercomputing unit is low; based on a standard middleware interface, airborne radar signal processing algorithm components are formed, cross-platform implementation, transplantation and acceleration of the radar algorithm by designers are facilitated, and acceleration of radar signal processing algorithm operator components based on heterogeneous computing resources in the embedded supercomputing unit is carried out.

Description

Technical Field

[0001] This invention relates to the field of embedded signal processing computing, and more specifically to an airborne radar signal processing system architecture. Background Technology

[0002] Airborne radar signal processing involves the conversion, filtering, and information extraction of numerous radio frequency (RF) array subarray signals. The radar signal processing platform needs to provide network resources for data transmission during signal processing and computing resources for algorithm implementation. Traditional airborne radar signal processing systems use an FPGA+DSP core, based on an SRIO network-based resource platform architecture. Due to the large data volume of the multi-channel subarray signals acquired from RF signal sampling, it is difficult to transmit them to the DSP via a traditional SRIO network. Therefore, radar signal preprocessing processes such as digital signal format conversion, down-conversion, baseband signal extraction, and digital beamforming are implemented in the FPGA, ultimately synthesizing a single-channel, low-data-volume signal, which is then transmitted to the DSP in the signal processing unit for radar algorithm processing steps such as anti-interference processing, pulse compression, and moving target detection.

[0003] With the increasing integration of digital circuits, the existing architecture of the traditional high-performance DSP C6678 is no longer suitable for further upgrades, and TI has essentially abandoned its DSP upgrade strategy. On the other hand, traditional airborne radar signal processing systems use SRIO networks to transmit signal data from RF front-end sampling to the preprocessing platform and then to the signal processing computing platform. FPGA preprocessing devices and DSP arrays both have SRIO interfaces. Currently, the development of SRIO networks has reached a bottleneck; the highest single-channel SRIO differential signal transmission rate per lane in industry applications is only 6.25 GHz, far lower than the differential signal transmission rate of up to 25 GHz per lane based on Ethernet channels.

[0004] Currently, the performance requirements of airborne radar detection are gradually increasing, with higher baseband signal frequencies, carrier frequencies, and sampling frequencies. The number of radio frequency components in radar arrays is also gradually increasing, and the system is evolving from a traditional centralized system to a new distributed system. At the same time, new-generation radar anti-jamming algorithms based on space-time adaptive algorithms and adaptive digital beamforming are gradually being applied in new-generation airborne radars. Various new radar systems and new radar signal processing algorithms are further increasing the computing power requirements of airborne radar signal processing systems. Most new algorithms need to directly extract information from multi-channel subarray signals to achieve anti-jamming calculations, rather than just calculating the single-channel signal of the entire array after multi-channel synthesis. Such complex, multi-array, multi-waveform large-scale parallel computing places high demands on the data transmission and computing capabilities of radar signal processing platforms. The traditional airborne radar processing architecture based on SRIO networks and FPGA+DSP is no longer sufficient to meet the needs of next-generation airborne radar models. Summary of the Invention

[0005] The purpose of this invention is to provide an airborne radar signal processing system architecture to overcome the problem that existing technologies cannot meet practical application requirements.

[0006] To achieve the above objectives, the present invention employs the following technical solution:

[0007] An airborne radar signal processing system architecture includes a radio frequency processing skin unit, a network switching unit, and a signal processing unit, wherein:

[0008] The radio frequency (RF) processing skin unit consists of an RF subarray composed of multiple RF elements and an RFSoC connected to the subarray. Multiple elements in the subarray acquire RF signals from the corresponding radar band and send them to the RFSoC for processing as electrical signals. The RF circuitry in the RFSoC performs RF processing and synthesis on the RF signals from different elements of the subarray, and performs digital sampling to form a single-channel subarray digital signal. Then, according to the radar signal processing requirements, the subarray signal preprocessing and down-conversion operations are implemented in the programmable logic unit of the RFSoC, ultimately generating a radar subarray-level single-channel baseband signal, which is sent to the network switching unit via the SerDes network interface.

[0009] The network switching unit uses an FPGA to provide a SerDes network interface that corresponds one-to-one with the RF processing skin unit. It receives and aggregates the single-channel baseband signals of the radar subarray level output by all RF processing skin units. The FPGA is used to package the baseband signal data of each channel received into a multi-channel radar subarray baseband signal data packet, which is then sent to the signal processing unit via Ethernet RDMA according to the multi-pulse processing cycle.

[0010] The signal processing unit uses a general-purpose CPU and GPU to form a computing unit. The CPU, in conjunction with an Ethernet network card that supports high-speed RDMA transmission, receives multi-pulse, multi-channel radar subarray baseband signal data for one coherent cycle according to the radar signal processing frame rate. The radar signal processing algorithm is deployed in the CPU and GPU. The CPU manages and schedules the radar signal processing algorithm, while the GPU's high-performance parallel computing capability performs high-speed parallel processing on the multi-pulse, multi-channel radar subarray baseband signal data to realize the radar signal processing process. Finally, it generates target point information detected by the radar and sends it to the airborne back-end data processing platform through the airborne FC network.

[0011] Furthermore, the CPU and GPU are connected via PCIe. The CPU handles data storage, distribution, and ping-pong pipelined operations, sending the entire baseband signal data packet to the GPU for radar signal processing calculations. The GPU supports the OpenCL toolchain, and the radar signal processing algorithm is written according to the OpenCL programming framework and stored in the CPU memory as a .cl file. When performing radar signal calculations, the CPU compiles the calculation process contained in the .cl file online and deploys it to the GPU. The CPU then completes instruction and data interaction with the GPU via the PCIe bus, implementing the radar signal processing calculations on the GPU.

[0012] Furthermore, the data transmission of radar data signals from the network switching unit to the signal processing unit that performs radar signal processing is realized by using Ethernet RDMA technology. A transmission-computation ping-pong pipelined processing mode is designed and deployed on the CPU of the signal processing unit to realize the parallel transmission and computation of radar signal processing algorithms in the CPU-GPU signal processing unit.

[0013] Furthermore, the ping-pong streaming processing method includes:

[0014] RDMA initialization is performed, registering the memory of the transmit and receive areas and informing the communication peer to achieve memory mapping. The network switching unit samples and preprocesses the baseband signal data of all subarray channels within each CPI time period, packages it into a frame of data of several hundred MB in size, and continuously sends it to the corresponding memory area of ​​the signal processing unit CPU. The CPU of the signal processing unit registers two memory areas for data reception. Since the RDMA communication process does not require explicit CPU process occupation, the CPU does not need to wait for the communication process. While receiving signal data packets from the network switching unit in one memory area, the CPU performs radar signal processing algorithm calculations on the data packets already received in the other area. After the single calculation and transmission process are completed, the two memory areas are switched to continue processing the next frame of signal data packets, realizing continuous ping-pong pipeline operation.

[0015] Furthermore, CPU and GPU accelerated computing components based on the open-source standard library VSIPL are deployed in the signal processing unit.

[0016] Furthermore, based on the computational flow of radar signal processing algorithms, different VSIPL operator functions are designed to construct a VSIPL operator library function set, which covers the computational functions required in the implementation of airborne radar signal processing algorithms. These functions include: one-dimensional floating-point FFT of vector groups, one-dimensional floating-point FFT of a single vector, conjugate inner product of complex vectors, element-wise conjugate floating-point multiplication between complex vectors / matrices, matrix floating-point multiplication, Hermitian floating-point multiplication between complex matrices, conjugate floating-point multiplication between matrices, FIR filtering, calculation of vector convolution, and calculation of vector vectors. Quantity correlation, element-wise product of scalars and vectors / matrices, QR decomposition of a matrix, sum of squares of vector / matrix elements, element-wise product between vectors / matrices, element-wise summation between vectors / matrices, element-wise summation within a vector / matrix, complex summation of two scalars, element-wise difference between vectors / matrices, element-wise summation between vectors / matrices, finding the conjugate transpose of a matrix, finding the Kronecker tensor product of a matrix, LU decomposition of a matrix, solving linear covariance or linear least squares problems, finding the index of the maximum value of a matrix / vector, finding the sum of squares of a complex scalar.

[0017] Furthermore, when implementing the radar signal processing algorithm, the data format of the radar signal processing algorithm and the main steps in the operation are represented in the CPU of the signal processing unit according to the data format and operator function interface of the VSIPL operator library function set, forming a radar algorithm program framework that conforms to the VSIPL standard.

[0018] Furthermore, the radar signal processing steps include matrix correlation operations, matched filtering, pulse compression, moving target detection, and space-time adaptive anti-interference.

[0019] Furthermore, hardware acceleration is performed on typical radar signal processing operators in the VSIPL operator library function set based on OpenCL-GPU, OpenMP-multi-core CPU, and NEON instruction set. Specifically, the hardware-accelerated operators implemented based on OpenMP-multi-core CPU and NEON instruction set are accelerated and implemented in the CPU of the signal processing unit, while the operators implemented based on OpenCL-GPU are accelerated and implemented in the GPU of the signal processing platform.

[0020] Furthermore, extended parameters are added to the interface of each operator function to specify the hardware acceleration method used when the main program calls the function for computation. When programming in this architecture, designers only need to specify the hardware acceleration method of the VSIPL operator to be called, and the implementation of the algorithm is encapsulated inside the operator.

[0021] Compared with the prior art, the present invention has the following technical features:

[0022] 1. This invention uses an Ethernet RDMA-based network and a general-purpose CPU+GPU as the signal processing unit in an airborne radar signal processing platform to replace the traditional architecture based on SRIO network and FPGA+DSP. By introducing advanced technologies from the civilian and commercial markets, it improves the transmission and computing performance of the airborne computing platform, acquires the digital signals of all sub-array channels of the radar array in the signal processing unit, provides powerful computing power to meet the deployment and implementation requirements of the next-generation radar signal processing algorithms, and solves the problem that traditional DSPs have no next-generation technology roadmap.

[0023] 2. The application of Ethernet-based RDMA network communication technology to replace the traditional SRIO network in the airborne radar signal processing system increases the communication bandwidth while freeing up the CPU from the communication process, enabling the CPU to achieve uninterrupted signal processing through the transmission-computation pipeline.

[0024] 3. The radar algorithm is decomposed and uniformly represented using the VSIPL standard library function interface and data structure, decoupling the algorithm function design from the underlying implementation based on heterogeneous computing resources. This makes it easier for designers to port and implement the algorithm on different platforms, reducing the difficulty of hardware acceleration. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the system architecture of the present invention;

[0026] Figure 2 This describes a pingpong pipeline processing flow for radar signal transmission and computation based on RDMA. Detailed Implementation

[0027] Referring to the accompanying drawings, the airborne radar signal processing system architecture proposed in this invention includes a radio frequency processing skin unit, a network switching unit, and a signal processing unit, wherein:

[0028] 1. Radio Frequency Processing Skin Unit

[0029] The radio frequency (RF) processing skin unit consists of an RF subarray composed of multiple RF elements and an RFSoC (Radio Frequency System-on-Chip) connected to the subarray. Multiple elements in the subarray acquire RF signals from the corresponding radar band and send them to the RFSoC for processing as electrical signals. The RF circuitry in the RFSoC performs RF processing and synthesis on the RF signals from different elements of the subarray, and performs digital sampling to form a single-channel subarray digital signal. Then, according to the radar signal processing requirements, subarray signal preprocessing, down-conversion, and other operations are implemented in the programmable logic unit of the RFSoC, ultimately generating a radar subarray-level single-channel baseband signal, which is sent to the network switching unit via the SerDes network interface. The airborne radar architecture of this invention is typically composed of 16 to 64 RF subarrays.

[0030] 2. Network switching unit

[0031] The network switching unit uses a large-scale FPGA to provide a SerDes network interface corresponding to each RF processing skin unit, receiving and aggregating the single-channel baseband signals output by all RF processing skin units at the radar subarray level. In addition, according to the requirements of the overall radar algorithm design process, the FPGA is used to package the baseband signal data of each channel received into a multi-channel radar subarray baseband signal data packet, which is then sent to the signal processing unit via Ethernet RDMA according to the multi-pulse processing cycle.

[0032] 3. Signal Processing Unit

[0033] The signal processing unit uses a general-purpose CPU and GPU to form a computing unit. The CPU is equipped with an Ethernet network card that supports high-speed (4*25Gbps) RDMA transmission mode to receive multi-pulse multi-channel radar subarray baseband signal data of one coherent cycle according to the radar signal processing frame rate. The radar signal processing algorithm is deployed in the CPU and GPU. The CPU is used to manage and schedule the radar signal processing algorithm, and the high-performance parallel computing capability of the GPU is used to perform high-speed parallel operation on the multi-pulse multi-channel radar subarray baseband signal data to realize the radar signal processing process. Finally, the target point information detected by the radar is generated and sent to the airborne back-end data processing platform through the airborne FC network.

[0034] The CPU and GPU are connected via PCIe. The CPU handles data storage, distribution, and ping-pong pipelined computation, sending the entire baseband signal data packet to the GPU for radar signal processing calculations. The GPU supports the OpenCL toolchain. The radar signal processing algorithm is written according to the OpenCL programming framework and stored in the CPU memory as a .cl file. When performing radar signal calculations, the CPU compiles the calculation process contained in the .cl file online and deploys it to the GPU. Instruction and data interaction between the CPU and GPU is completed via the PCIe bus, and the radar signal processing calculations are implemented in the GPU.

[0035] In this embodiment, the CPU of the signal processing unit is selected as the Phytium D2000 processor, which is designed based on the ARMv8 general instruction set, adapted to the Linux kernel-based operating system, compiles application development toolchain, and supports Ethernet network cards with RDMA function; the independently controllable JH920 model GPU is used as the heterogeneous computing resource of this architecture.

[0036] 4. Streamlined processing of radar signals ping-pong based on RDMA network communication

[0037] This invention uses Ethernet RDMA (Remote Direct Memory Access) technology to realize the data transmission of radar data signals from the network switching unit to the signal processing unit that performs radar signal processing. It also designs and deploys a transmission-computation ping-pong pipelined processing mode on the CPU of the signal processing unit to realize the parallel transmission and computation of radar signal processing algorithms in the CPU-GPU signal processing unit, ensuring the continuity and integrity of signal processing and the high utilization of the platform.

[0038] Devices using RDMA communication only need to complete RDMA communication memory registration on the host side to initialize the network card. During high-speed transmission, data transmission, reception, transfer, mapping, and Ethernet protocol implementation are all completed in the network card that supports RDMA, freeing up the host CPU resources occupied by network transmission.

[0039] The airborne radar system platform's network switching unit and signal processing unit are physically connected via Ethernet. RDMA initialization is performed, and each registers its transmit and receive memory areas and informs the communication peer, achieving memory mapping. The signal front-end samples and preprocesses the baseband signal data from all subarray channels within each CPI (Coherent Phase Processing Interval), packaging it into a single frame of several hundred MB in size, and continuously sends it to the corresponding memory area of ​​the signal processing unit's CPU. The signal processing unit's CPU registers two memory areas for data reception. Since RDMA communication does not require explicit CPU process usage, the CPU does not need to wait for the communication process. While receiving signal data packets from the network switching unit in one memory area, it performs radar signal processing algorithm calculations on data packets already received in the other area. After both the calculation and transmission processes are completed, the two memory areas switch to continue processing the next frame of signal data packets, achieving continuous ping-pong pipelined operation. The process is as follows: Figure 2 As shown.

[0040] 5. Radar algorithm operator components implemented based on VSIPL middleware

[0041] This invention designs and deploys CPU and GPU accelerated computing components based on the open-source standard library VSIPL (Vector Signal Image Processing Library) in the signal processing unit, which is used to conveniently and efficiently implement radar signal processing algorithms in the signal processing unit and give full play to the overall computing power advantage of the system.

[0042] This invention analyzes the computation process of radar signal processing algorithms and extracts 25 functional operators from the VSIPL library, as shown in Table 1. These operators cover the computational functions required in the implementation of airborne radar signal processing algorithms.

[0043] Table 1. VSIPL Operator Library Function Set and Acceleration Methods

[0044]

[0045]

[0046] To implement radar signal processing algorithms using the architecture of this invention, the data format and main steps of the operation in the radar signal processing algorithm need to be represented in the CPU of the signal processing unit according to the data format and operator function interface of the VSIPL operator library function set, forming a radar algorithm program framework that conforms to the VSIPL standard. The VSIPL operator functions corresponding to each step of the radar signal processing algorithm are shown in Table 2.

[0047] Table 2. VSIPL operator representation of radar algorithm steps

[0048]

[0049]

[0050] This invention provides hardware acceleration for the typical radar signal processing operators listed in Table 1 based on OpenCL-GPU, OpenMP-multi-core CPU, and the NEON instruction set. Specifically, the hardware-accelerated operators implemented using OpenMP-multi-core CPU and the NEON instruction set are accelerated and implemented within the CPU of the signal processing unit, while the operators implemented using OpenCL-GPU are accelerated and implemented within the GPU of the signal processing platform. The invention adds extended parameters to the interface of each operator function to specify the hardware acceleration method used when the main program calls the function for computation. When programming in the platform architecture of this invention, designers only need to specify the hardware acceleration method of the called VSIPL operators; the algorithm implementation is encapsulated within the operators. The hardware acceleration methods supported by each operator are shown in Table 1.

[0051] After disassembly and re-characterization, the airborne radar algorithm is written based on a unified VSIPL interface library function. The algorithm implemented using a unified interface decouples its business functions from the underlying hardware implementation. Designers can design and port the algorithm within the platform architecture of this invention. The hardware acceleration process implemented by the algorithm calling heterogeneous computing resources is implemented inside the encapsulated operator, reducing the need for algorithm designers to master hardware acceleration technology.

[0052] This invention proposes an implementation architecture based on embedded heterogeneous computing resources, providing a hardware and software solution for the implementation of next-generation airborne radar algorithms. It uses a combination of multi-core general-purpose CPU and GPU as the embedded supercomputing unit in the radar signal processing system, replacing the traditional airborne DSP array. While retaining the advantages of the original DSP platform in terms of efficient application debugging and flexible deployment, it utilizes advanced, highly integrated, and high-computing-power processing units to provide computing power support for radar processing algorithms. It employs Ethernet RDMA communication to increase the transmission bandwidth of the radar signal processing platform, sending all multi-channel and multi-pulse subarray data to the CPU+GPU-based signal processing unit through a network switching unit. A ping-pong transmission-computation pipeline is designed based on RDMA, leveraging the platform's high-performance computing advantages with low CPU resource consumption in the embedded supercomputing unit. Based on standard middleware interfaces, the airborne radar signal processing algorithms are modularized, facilitating cross-platform implementation, porting, and acceleration of radar algorithms. Furthermore, the radar signal processing algorithm operator components are accelerated based on the heterogeneous computing resources in the embedded supercomputing unit, fully utilizing the computing power advantages of heterogeneous computing resources while reducing the overall difficulty for designers in using the embedded supercomputing unit.

[0053] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An airborne radar signal processing system architecture, characterized in that, It includes a radio frequency processing skin unit, a network switching unit, and a signal processing unit, wherein: The radio frequency (RF) processing skin unit consists of an RF subarray composed of multiple RF elements and an RFSoC connected to the subarray. Multiple elements in the subarray acquire RF signals from the corresponding radar band and send them to the RFSoC for processing as electrical signals. The RF circuitry in the RFSoC performs RF processing and synthesis on the RF signals from different elements of the subarray, and performs digital sampling to form a single-channel subarray digital signal. Then, according to the radar signal processing requirements, the subarray signal preprocessing and down-conversion operations are implemented in the programmable logic unit of the RFSoC, ultimately generating a radar subarray-level single-channel baseband signal, which is sent to the network switching unit via the SerDes network interface. The network switching unit uses an FPGA to provide a SerDes network interface that corresponds one-to-one with the RF processing skin unit. It receives and aggregates the single-channel baseband signals of the radar subarray level output by all RF processing skin units. The FPGA is used to package the baseband signal data of each channel received into a multi-channel radar subarray baseband signal data packet, which is then sent to the signal processing unit via Ethernet RDMA according to the multi-pulse processing cycle. The signal processing unit uses a general-purpose CPU and GPU to form a computing unit. The CPU, in conjunction with an Ethernet network card that supports high-speed RDMA transmission, receives multi-pulse multi-channel radar subarray baseband signal data for one coherent cycle according to the radar signal processing frame rate. The radar signal processing algorithm is deployed in the CPU and GPU. The CPU manages and schedules the radar signal processing algorithm, while the GPU's high-performance parallel computing capability performs high-speed parallel processing on the multi-pulse multi-channel radar subarray baseband signal data to realize the radar signal processing process. Finally, the target point information detected by the radar is generated and sent to the airborne back-end data processing platform through the airborne FC network. The CPU and GPU are connected via PCIe. The GPU supports the OpenCL toolchain. The radar signal processing algorithm is written according to the OpenCL programming framework and stored in the CPU memory in the form of .cl files. A transmission-computation ping-pong pipelined processing method was designed and deployed on the CPU of the signal processing unit to realize the parallel transmission and computation of radar signal processing algorithms in the CPU-GPU signal processing unit. Deploy CPU and GPU accelerated computing components based on the open-source standard library VSIPL in the signal processing unit; Based on the computational flow of radar signal processing algorithms, different VSIPL operator functions are designed to construct a VSIPL operator library function set, which covers the computational functions required in the implementation of airborne radar signal processing algorithms. The radar signal processing algorithm is characterized according to the data format and operator function interface of the VSIPL operator library function set; Hardware acceleration of typical radar signal processing operators in the VSIPL operator library function set is achieved using OpenCL-GPU, OpenMP-multi-core CPU, and NEON instruction set.

2. The airborne radar signal processing system architecture according to claim 1, characterized in that, The CPU implements data storage, distribution, and ping-pong pipelined operations, sending the entire packet of baseband signal data to the GPU for radar signal processing calculations. When performing radar signal calculations, the CPU compiles the calculation process contained in the .cl file online and deploys it on the GPU, and completes instruction and data interaction with the GPU through the PCIe bus, thus implementing the radar signal processing calculations on the GPU.

3. The airborne radar signal processing system architecture according to claim 1, characterized in that, Data transmission of radar data signals from the network switching unit to the signal processing unit that performs radar signal processing is achieved using Ethernet-based RDMA technology.

4. The airborne radar signal processing system architecture according to claim 1, characterized in that, The ping-pong streaming processing method includes: RDMA initialization is performed, registering the memory of the transmit and receive areas and informing the communication peer to achieve memory mapping. The network switching unit samples and preprocesses the baseband signal data of all subarray channels within each CPI time period, packages it into a frame of data of several hundred MB in size, and continuously sends it to the corresponding memory area of ​​the signal processing unit CPU. The CPU of the signal processing unit registers two memory areas for data reception. Since the RDMA communication process does not require explicit CPU process occupation, the CPU does not need to wait for the communication process. While receiving signal data packets from the network switching unit in one memory area, the CPU performs radar signal processing algorithm calculations on the data packets already received in the other area. After the single calculation and transmission process are completed, the two memory areas are switched to continue processing the next frame of signal data packets, realizing continuous ping-pong pipeline operation.

5. The airborne radar signal processing system architecture according to claim 1, characterized in that, The VSIPL operator library function set includes the following operational functions: one-dimensional floating-point FFT of vector groups, one-dimensional floating-point FFT of a single vector, conjugate inner product of complex vectors, element-wise conjugate floating-point multiplication between complex vectors or matrices, matrix floating-point multiplication, Hermitian floating-point multiplication between complex matrices, conjugate floating-point multiplication between matrices, FIR filtering, calculating vector convolution, calculating vector correlation, element-wise multiplication of scalars and vectors or matrices, matrix QR decomposition, sum of squares of vector or matrix elements, element-wise multiplication between vectors or matrices, element-wise summation between vectors or matrices, element-wise summation of elements within a vector or matrix, complex summation of two scalars, element-wise difference between vectors or matrices, element-wise summation between vectors or matrices, finding the conjugate transpose of a matrix, finding the Kronecker tensor product of a matrix, LU decomposition of a matrix, solving linear covariance or linear least squares problems, finding the index of the maximum value of a matrix or vector, and finding the sum of squares of complex scalars.

6. The airborne radar signal processing system architecture according to claim 1, characterized in that, The radar signal processing algorithm is characterized according to the data format and operator function interface of the VSIPL operator library function set, specifically as follows: When implementing radar signal processing algorithms, the CPU of the signal processing unit represents the data format of the radar signal processing algorithm and the main steps of the operation according to the data format and operator function interface of the VSIPL operator library function set, forming a radar algorithm program framework that conforms to the VSIPL standard.

7. The airborne radar signal processing system architecture according to claim 1, characterized in that, The radar signal processing steps include matrix correlation operations, matched filtering, pulse compression, moving target detection, and space-time adaptive anti-jamming.

8. The airborne radar signal processing system architecture according to claim 1, characterized in that, In the hardware acceleration, the hardware-accelerated operators based on OpenMP-multi-core CPU and NEON instruction set are accelerated and implemented in the CPU of the signal processing unit, while the operators based on OpenCL-GPU are accelerated and implemented in the GPU of the signal processing platform.

9. The airborne radar signal processing system architecture according to claim 1, characterized in that, Extended parameters are added to the interface of each operator function to specify the hardware acceleration method used when the main program calls the function for computation. When programming in this architecture, designers only need to specify the hardware acceleration method of the VSIPL operator to be called, and the implementation of the algorithm is encapsulated inside the operator.

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