A micro control unit and an electronic device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HEFEI CHIPSEA ELECTRONICS TECH CO LTD
- Filing Date
- 2023-03-08
- Publication Date
- 2026-06-16
Smart Images
Figure CN116225201B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip technology, specifically to a microcontroller unit and an electronic device. Background Technology
[0002] The power system of an MCU (Micro Controller Unit) chip is crucial, and it is generally desirable for the power system to perform its functions with minimal area in order to reduce costs.
[0003] Traditional MCUs are typically powered by LDOs (low dropout linear regulators), which offer advantages such as low cost, low noise, and low quiescent current. However, since the MCU always uses the LDO for power regardless of its operating state, its power consumption is relatively high. Summary of the Invention
[0004] This application provides a microprocessor unit and an electronic device that can reduce the power consumption of the microprocessor unit.
[0005] This application provides a microprocessor unit, comprising: a first power module; a second power module connected to the first power module; a core module connected to the second power module; and a switch module connected to the first power module, the second power module, and the core module. During the power-on boot phase, the first power module is powered on, the first power module powers on the second power module, the switch module controls the second power module to supply power to the core module, and the second power module controls the core module to perform a configuration file writing operation. During the operating phase, the switch module controls either the first power module or the second power module to supply power to the core module, wherein the driving capability of the first power module is less than that of the second power module.
[0006] In some embodiments, the microprocessor unit further includes a control module connected to a first power module and a second power module; wherein, during the power-on boot phase, the first power module is powered on, the first power module powers on the control module and the second power module, the control module configures the second power module, and after the second power module is configured, the first power module is enabled.
[0007] The second power module controls the switch module to supply power to the core module and controls the core module to perform configuration file writing operations.
[0008] In some embodiments, the control module includes a configuration register, which the control module uses to configure the functions of the second power module.
[0009] In some embodiments, the first power module includes: a first power supply pin connected to a second power module, a control module, and a switch module; a first enable pin connected to the second power module; a reset pin connected to the control module; and a clock pin connected to the control module. During the power-on boot phase, the first power module is powered on. After a first delay, the levels of the first power supply pin and the reset pin are pulled high to power on the second power module and the control module and to reset the control module. After a second delay, the level of the clock pin is pulled high, and the control module begins operation to configure the second power module. After the second power module is configured, the level of the first enable pin is pulled high to enable the second power module.
[0010] In some embodiments, the first power module further includes a first power pin, which is connected to an external power source to supply power to the first power module; wherein, during the power-on boot phase, the level of the first power pin is pulled high to power on the first power module.
[0011] In some embodiments, the second power module includes: a second power pin connected to the first power module; a second enable pin connected to the first power module; a configuration pin connected to the control module; an indicator pin connected to the core module; and a second power supply pin connected to the switch module. During the power-on boot phase, the level of the second power pin is pulled high to power on the second power module. Based on the configuration pin, the control module's functional configuration is received. After the second power module's functional configuration is completed, the level of the second enable pin is pulled high when the first power module is enabled. After the second power module starts up, the levels of the indicator pin and the second power supply pin are pulled high. When the level of the indicator pin is pulled high, the core module performs a configuration file writing operation.
[0012] In some embodiments, the driving capability of the second power module is greater than that of the first power module; wherein, during normal operation, the switching module controls the second power module to supply power to the core module, and during low-power operation, the switching module controls the first power module to supply power to the core module.
[0013] In some embodiments, the switching module includes: a first switch, a first end of which is connected to a first power module, and a second end of which is connected to a core module; and a second switch, a first end of which is connected to a second power module, and a second end of which is connected to the core module; wherein, during normal operation, the first switch is off and the second switch is on, and during low-power operation, the first switch is on and the second switch is off.
[0014] In some embodiments, during the power-on boot phase, the second power module controls the external memory to perform a configuration file writing operation on the core module.
[0015] This application also provides an electronic device that includes the microprocessor unit as described above.
[0016] The microprocessor unit provided in this embodiment includes: a first power module; a second power module connected to the first power module; a core module connected to the second power module; and a switch module connected to the first power module, the second power module, and the core module. During the power-on boot phase, the first power module is powered on, and the first power module powers on the second power module. The switch module controls the second power module to supply power to the core module, and the second power module controls the core module to perform a configuration file writing operation. During the operating phase, the switch module controls either the first or second power module to supply power to the core module, wherein the driving capability of the first power module is less than that of the second power module. By using two power modules to power the core module, with one power module powered / controlled by the other, it is convenient to control the startup and shutdown of the second power module. When the core module operates in a low-power mode, the power module with the lower driving capability can be selected to manage its power consumption, thereby reducing the overall power consumption of the microprocessor unit. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of the structure of the first embodiment of the microprocessor unit provided in this application;
[0019] Figure 2 This is a schematic diagram of the structure of the second embodiment of the microprocessor unit provided in this application;
[0020] Figure 3 This is a structural schematic diagram of an embodiment of the first power module 11;
[0021] Figure 4 This is a schematic diagram of the structure of one embodiment of the second power module 12;
[0022] Figure 5 This is a schematic diagram of the structure of the third embodiment of the microprocessor unit provided in this application;
[0023] Figure 6 yes Figure 5A timing diagram corresponding to one embodiment;
[0024] Figure 7 This is a schematic diagram of the structure of an embodiment of the electronic device provided in this application. Detailed Implementation
[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0026] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0027] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.
[0028] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values may in practice be based on additional conditions or values beyond those stated.
[0029] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.
[0030] See Figure 1 , Figure 1This is a schematic diagram of the structure of a first embodiment of the microprocessor unit provided in this application. The microprocessor unit 100 includes a first power module 11, a second power module 12, a core module 13, and a switch module 14. The second power module 12 is connected to the first power module 11, the core module 13 is connected to the second power module 12, and the switch module 14 is connected to the first power module 11, the second power module 12, and the core module 13.
[0031] Among them, core module 13, also known as the core or kernel, is the most important component of processors such as CPUs and MCUs. All calculations, command reception / storage, and data processing are executed by the core. Various CPU cores have a fixed logical structure, with logical units such as L1 cache, L2 cache, execution units, instruction-level units, and bus interfaces arranged in a scientific manner. Taking STM32 as an example, STM32 represents a 32-bit microcontroller with an ARM Cortex-M core. Common cores include ARM Cortex-M0, M0+, M3, M4, and M7 cores.
[0032] Specifically, during the power-on boot phase, an external power supply powers the first power module 11, the first power module 11 powers the second power module 12, and the switch module 14 controls the second power module 12 to supply power to the core module 13. The second power module 12 controls the core module 13 to perform a configuration file writing operation (option byte load). During the working phase, the switch module 14 controls either the first power module 11 or the second power module 12 to supply power to the core module 13. The first power module 11 and the second power module 12 have different driving capabilities.
[0033] Specifically, writing configuration files can include modifying configuration files.
[0034] Understandably, during the power-on boot phase, the first power module 11 is powered by an external power source (such as a PAD) to complete the power-on process. Then, the first power module 11 powers the second power module 12, completing the power-on of the second power module 12. After the second power module 12 is powered on, the configuration file is written to the core module 13. In this way, since the first power module 11 is powered by an external power source and is an always-on power module, while the second power module 12 is powered by the first power module 11, the startup and shutdown of the second power module 12 can be controlled by the first power module 11, facilitating the operation of the second power module 12's startup and shutdown.
[0035] Understandably, during the working phase, the switch module 14 can control the switching between the first power module 11 and the second power module 12, so that either the first power module 11 or the second power module 12 can supply power to the core module 13.
[0036] In this embodiment, since the first power module 11 and the second power module 12 have different driving capabilities, they can be switched according to the real-time needs of the core module 13. Optionally, the driving capability of the first power module is less than that of the second power module. For example, when the core module 13 is operating in a low-power mode, the first power module 11, which has a weaker driving capability and lower power consumption, can be selected to power the core module 13. When the core module 13 is operating in a high-performance (high-power) mode, the second power module 12, which has a stronger driving capability and higher power consumption, can be selected to power the core module 13. Therefore, the overall power consumption of the microprocessor unit 100 can be reduced.
[0037] See Figure 2 , Figure 2 This is a schematic diagram of the structure of a second embodiment of the microprocessor unit provided in this application. The microprocessor unit 100 includes a first power module 11, a second power module 12, a core module 13, a switch module 14, and a control module 15. The second power module 12 is connected to the first power module 11, the core module 13 is connected to the second power module 12, the switch module 14 is connected to the first power module 11, the second power module 12, and the core module 13, and the control module 15 is connected to the first power module 11 and the second power module 12.
[0038] Specifically, during the power-on boot phase, an external power supply powers the first power module 11, which in turn powers the second power module 12 and the control module 15. The control module 15 configures the second power module 12. After the second power module 12 is configured, the first power module 11 enables the second power module 12. The switch module 14 controls the second power module 12 to supply power to the core module 13, and the second power module 12 controls the core module 13 to perform a configuration file write operation (option byte load). During the operation phase, the switch module 14 controls either the first power module 11 or the second power module 12 to supply power to the core module 13. The first power module 11 and the second power module 12 have different driving capabilities.
[0039] The control module 15 configures the second power module 12, including configuring parameters such as the output voltage, output current, and output power of the second power module 12. Optionally, the control module 15 has a built-in configuration register that stores configuration parameters. When configuring the second power module 12, the configuration parameters stored in the register are used to configure the function of the second power module 12.
[0040] Understandably, during the power-on boot phase, the first power module 11 is powered by an external power source (such as a PAD) to complete the power-on process. Then, the first power module 11 powers the second power module 12 and the control module 15, powering on the second power module 12. After the second power module 12 is powered on, the control module 15 configures it, and then writes the configuration file to the core module 13. In this way, since the first power module 11 is powered by an external power source and is a normally on power module, while the second power module 12 is powered by the first power module 11, the startup and shutdown of the second power module 12 can be controlled by the first power module 11, facilitating the operation of the second power module 12's startup and shutdown.
[0041] Understandably, during the working phase, the switch module 14 can control the switching between the first power module 11 and the second power module 12, so that either the first power module 11 or the second power module 12 can supply power to the core module 13.
[0042] In this embodiment, since the driving capabilities of the first power module 11 and the second power module 12 are different, they can be switched according to the real-time needs of the core module 13. Optionally, the driving capability of the first power module is less than that of the second power module. For example, when the core module 13 is operating in a low-power mode, the first power module 11, which has a weaker driving capability and lower power consumption, can be selected to power the core module 13. When the core module 13 is operating in a high-performance (high-power) mode, the second power module 12, which has a stronger driving capability and higher power consumption, can be selected to power the core module 13. Therefore, the overall power consumption of the microprocessor unit 100 can be reduced. Moreover, in this embodiment, the power-on control of the second power module 12 during the power-on boot phase is implemented by the control module 15, realizing the power-on boot sequence from the first power module 11 to the second power module 12. Then, the configuration file writing operation of the core module 13 is controlled by the second power module 12. At the same time, the control module 15 can also configure the functions of the second power module 12.
[0043] The first power module 11 and the second power module 12 will be described below.
[0044] like Figure 3 As shown, Figure 3 This is a schematic diagram of a first power supply module 11 according to an embodiment. The first power supply module 11 includes a first power supply pin V1, a first enable pin BODN, a reset pin RSTN, and a clock pin CLK.
[0045] The first power supply pin V1 is connected to the second power supply module 12, the control module 15, and the switch module 14; the first enable pin BODN is connected to the second power supply module 12; the reset pin RSTN is connected to the control module 15; and the clock pin CLK is connected to the control module 15.
[0046] During the power-on boot phase, an external power supply powers the first power module 11. After a first delay, the levels of the first power supply pin V1 and the reset pin RSTN are pulled high. Therefore, the first power module 11 powers on the second power module 12 and the control module 15 through the first power supply pin V1, and then resets the control module 15 through the reset pin RSTN. After a second delay, the level of the clock pin CLK is pulled high. The control module 15 starts working under the clock signal provided by the clock pin CLK to configure the functions of the second power module 12. After the function configuration of the second power module 12 is completed, the level of the first enable pin BODN is pulled high to enable the second power module 12. After the second power module 12 is enabled, the second power module 12 controls the core module 13 to perform a configuration file writing operation (option byte load).
[0047] During the working phase, the switch module 14 controls the first power module 11 or the second power module 12 to supply power to the core module 13. The first power module 11 and the second power module 12 have different driving capabilities.
[0048] Optionally, the first power module 11 further includes a first power pin AVD / AVS, which is connected to an external power supply to power the first power module 11; during the power-on boot phase, the level of the first power pin AVD / AVS is pulled high to power on the first power module 11.
[0049] Optionally, in one embodiment, an external power supply is used to provide a voltage of 3.3V, and a first power supply pin V1 is used to provide a voltage of 0.9V.
[0050] like Figure 4 As shown, Figure 4 This is a schematic diagram of an embodiment of the second power module 12, which includes a second power supply pin VCC, a second enable pin LDO_EN, a configuration pin REG_BGP_LV[4:0], an indicator pin LDO_OK, and a second power supply pin V2.
[0051] Among them, the second power supply pin VCC is connected to the first power supply module 11; the second enable pin LDO_EN is connected to the first power supply module 11; the configuration pin REG_BGP_LV[4:0] is connected to the control module 15; the indicator pin LDO_OK is connected to the core module 13; and the second power supply pin V2 is connected to the switch module 14.
[0052] Among them, the configuration pin REG_BGP_LV[4:0] is mainly used for BGP configuration. This is just an example. In other embodiments, the second power module 12 can also be configured through other configuration pins.
[0053] During the power-on boot-up phase, the first power module 11 is powered on, which in turn powers the control module 15 and the second power module 12. The level of the second power supply pin VCC is pulled high, and the function configuration of the control module 15 is received based on the configuration pin REG_BGP_LV[4:0]. After the function configuration of the second power module 12 is completed, the level of the second enable pin LDO_EN is pulled high under the enable of the first power module 11. After the second power module 12 is started, the level of the indicator pin LDO_OK and the level of the second power supply pin V2 are pulled high. When the level of the indicator pin LDO_OK is pulled high, the core module 13 performs a configuration file writing operation.
[0054] During the working phase, the switch module 14 controls the first power module 11 or the second power module 12 to supply power to the core module 13. The first power module 11 and the second power module 12 have different driving capabilities.
[0055] See Figure 5 , Figure 5 This is a schematic diagram of the structure of a third embodiment of the microprocessor unit provided in this application. The microprocessor unit 100 includes a first power module 11, a second power module 12, a core module 13, a switch module 14, and a control module 15. The second power module 12 is connected to the first power module 11, the core module 13 is connected to the second power module 12, the switch module 14 is connected to the first power module 11, the second power module 12, and the core module 13, and the control module 15 is connected to the first power module 11 and the second power module 12.
[0056] The first power supply module 11 includes a first power supply pin V1, a first enable pin BODN, a reset pin RSTN, and a clock pin CLK.
[0057] The second power module 12 includes a second power supply pin VCC, a second enable pin LDO_EN, a configuration pin REG_BGP_LV[4:0], an indicator pin LDO_OK, and a second power supply pin V2.
[0058] The switch module 14 includes a first switch 141 and a second switch 142.
[0059] Specifically, the first power supply pin V1 is connected to the second power supply pin VCC, the control module 15, and the first terminal of the first switch 141. The second terminal of the first switch 141 is connected to the core module 13. The first enable pin BODN is connected to the second enable pin LDO_EN, the reset pin RSTN is connected to the control module 15, and the clock pin CLK is connected to the control module 15. The configuration pin REG_BGP_LV[4:0] is connected to the control module 15, the indicator pin LDO_OK is connected to the core module 13, the second power supply pin V2 is connected to the first terminal of the second switch 142, and the second terminal of the second switch 142 is connected to the core module 13.
[0060] During the power-on boot phase, the level of the first power supply pin AVD / AVS is pulled high to power on the first power module 11. After the first delay, the levels of the first power supply pin V1 and the reset pin RSTN are pulled high. Therefore, the first power module 11 powers on the second power module 12 and the control module 15 through the first power supply pin V1. The level of the second power supply pin VCC is pulled high, and the control module 15 is reset through the reset pin RSTN. After the second delay, the level of the clock pin CLK is pulled high. The control module 15 starts working under the clock signal provided by the clock pin CLK to configure the function of the second power module 12 based on the configuration pin REG_BGP_LV[4:0]. After the function configuration of the second power module 12 is completed, the level of the first enable pin BODN is pulled high to pull up the level of the second enable pin LDO_EN, enabling the second power module 12. After the second power module 12 is started, the level of the indicator pin LDO_OK and the second power supply pin V2 is pulled high. When the level of the indicator pin LDO_OK is pulled high, the core module 13 performs the configuration file writing operation.
[0061] Optionally, the core module 13 performs the configuration file writing operation by using an external memory (such as flash) to perform the configuration file writing operation on the core module 13.
[0062] During the working phase, the switch module 14 controls the first power module 11 or the second power module 12 to supply power to the core module 13. The first power module 11 and the second power module 12 have different driving capabilities.
[0063] The following is combined with Figure 6 , Figure 6 yes Figure 5 The timing diagram corresponding to one embodiment, and the specific power-on boot process are as follows:
[0064] 1) After the first power supply pin AVD (3.3V) is powered on, when the voltage of the first power supply pin AVD is greater than the rising threshold, the reset is released (the reset pin RSTN is pulled high);
[0065] 2) When the first power supply pin V1 and clock pin CLK connected to the control module 15 start working, the control module 15 starts working;
[0066] 3) Since the configuration register of the second power module 12 is configured by the control module 15, the second power module 12 will be configured after a period of time after the control module 15 starts working (taking REG_BGP_LV[4:0] as an example in the timing diagram);
[0067] 4) When the second enable pin LDO_EN of the second power module 12 is pulled high, the second power module 12 is started.
[0068] 5) After the second power module 12 is started, it pulls the indicator pin LDO_OK and the second power supply pin V2 high, where the second power supply pin V2 supplies power to the core module 13;
[0069] 6) After the indicator pin LDO_OK is pulled high, the code options are loaded. When the code options are loaded, the core module 13 is reset and released.
[0070] 7) Core module 13 starts up and power-on boot complete.
[0071] The microprocessor unit provided in this embodiment includes: a first power module; a second power module connected to the first power module; a core module connected to the second power module; and a switch module connected to the first power module, the second power module, and the core module. During the power-on boot phase, the first power module is powered on, and the first power module powers on the second power module. The switch module controls the second power module to supply power to the core module, and the second power module controls the core module to perform a configuration file writing operation. During the operating phase, the switch module controls either the first or second power module to supply power to the core module, wherein the driving capability of the first power module is less than that of the second power module. By using two power modules to power the core module, with one power module powered / controlled by the other, it is convenient to control the startup and shutdown of the second power module. When the core module operates in a low-power mode, the power module with the lower driving capability can be selected to manage its power consumption, thereby reducing the overall power consumption of the microprocessor unit.
[0072] See Figure 7 , Figure 7 This is a schematic diagram of an embodiment of the electronic device provided in this application. The electronic device 200 includes a microprocessor unit 100 as described in the above embodiment.
[0073] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A microcontroller unit, characterized in that, The microcontroller unit includes: First power module; A second power module is connected to the first power module. The core module is connected to the second power module; A switching module, wherein the switching module is connected to the first power module, the second power module and the core module; During the power-on boot-up phase, the first power module is powered on, the first power module powers on the second power module, the switch module controls the second power module to supply power to the core module, and the second power module controls the core module to perform a configuration file writing operation. During the operation phase, the switch module controls either the first power module or the second power module to supply power to the core module, wherein the driving capability of the first power module is less than that of the second power module.
2. The microcontroller unit according to claim 1, characterized in that, The microcontroller unit further includes a control module, which is connected to the first power module and the second power module. During the power-on boot-up phase, the first power module is powered on, which in turn powers on the control module and the second power module. The control module configures the second power module. After the second power module is configured, the first power module enables the second power module. The switch module controls the second power module to supply power to the core module, and the second power module controls the core module to perform a configuration file writing operation.
3. The microcontroller unit according to claim 2, characterized in that, The control module includes a configuration register, which is used to configure the functions of the second power module.
4. The microcontroller unit according to claim 2, characterized in that, The first power module includes: A first power supply pin is connected to the second power module, the control module, and the switch module. A first enable pin is connected to the second power module; A reset pin, which is connected to the control module; A clock pin, which is connected to the control module; During the power-on boot-up phase, the first power module is powered on. After a first delay, the levels of the first power supply pin and the reset pin are pulled high to power on the second power module and the control module and to reset the control module. After a second delay, the level of the clock pin is pulled high, and the control module begins to work to configure the second power module. After the second power module is configured, the level of the first enable pin is pulled high to enable the second power module.
5. The microcontroller unit according to claim 4, characterized in that, The first power module further includes a first power pin, which is connected to an external power source to supply power to the first power module. During the power-on boot-up phase, the level of the first power supply pin is pulled high to power on the first power module.
6. The microcontroller unit according to claim 2, characterized in that, The second power module includes: The second power supply pin is connected to the first power module. The second enable pin is connected to the first power module; A configuration pin is provided, which is connected to the control module. An indicator pin, which is connected to the core module; The second power supply pin is connected to the switch module; During the power-on boot phase, the level of the second power supply pin is pulled high to power on the second power module. Based on the configuration pin, the function configuration of the control module is accepted. After the function configuration of the second power module is completed, the level of the second enable pin is pulled high when the first power module is enabled. After the second power module is started, the levels of the indicator pin and the second power supply pin are pulled high. When the level of the indicator pin is pulled high, the core module performs a configuration file writing operation.
7. The microcontroller unit according to claim 1, characterized in that, The driving capability of the second power module is greater than that of the first power module. During normal operation, the switching module controls the second power module to supply power to the core module; during low-power operation, the switching module controls the first power module to supply power to the core module.
8. The microcontroller unit according to claim 7, characterized in that, The switching module includes: A first switch, the first end of which is connected to the first power module, and the second end of which is connected to the core module; A second switch, the first end of which is connected to the second power module, and the second end of which is connected to the core module; During normal operation, the first switch is open and the second switch is closed; during low-power operation, the first switch is closed and the second switch is open.
9. The microcontroller unit according to claim 1, characterized in that, During the power-on boot phase, the second power module controls the external memory to perform a configuration file writing operation on the core module.
10. An electronic device, characterized in that, The electronic device includes a microcontroller unit as described in any one of claims 1-9.