Function verification method and system, electronic device and computer readable medium

Abstract

The present disclosure provides a function verification method, comprising: obtaining a first time length consumed by a processor in executing a first processing instruction capable of being used to implement a translation lookaside buffer hit; obtaining a second time length consumed by the processor in executing a second processing instruction capable of being used to implement a translation lookaside buffer miss; and verifying whether a function of the translation lookaside buffer is abnormal according to the first time length and the second time length. The present disclosure also provides a function verification system, an electronic device and a computer readable medium.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a functional verification method and system, electronic device, and computer-readable medium thereof. Background Technology

[0002] RISC-V is an open-source instruction set architecture (ISA) based on the Reduced Instruction Set Computing (RISC) principle. It can be freely used for any purpose, has extensive software support, and effectively addresses the common weaknesses of new instruction sets. The RISC-V processor's Central Processing Unit (CPU) includes a Memory Management Unit (MMU), which is primarily responsible for mapping virtual addresses to physical addresses. The Translation Lookaside Buffer (TLB), part of the MMU, effectively improves CPU operating efficiency.

[0003] Currently, the common method for detecting TLB malfunctions is through signal observation, but this method has low efficiency and accuracy. Summary of the Invention

[0004] In a first aspect, this disclosure provides a functional verification method, including:

[0005] Get the first duration of time spent by the processor executing the first processing instruction that can be used to achieve a translation back buffer hit;

[0006] The second duration of time spent by the processor executing a second processing instruction that can be used to implement the second processing instruction that was missed by the transition back buffer is obtained;

[0007] The first duration and the second duration are used to verify whether the conversion backup buffer has a functional abnormality.

[0008] Optionally, the step of verifying whether the functionality of the acquisition processor's conversion backup buffer is abnormal based on the first duration and the second duration includes:

[0009] Calculate the difference between the second duration and the first duration to obtain the duration difference value;

[0010] Determine whether the duration difference is greater than a preset duration threshold;

[0011] When it is determined that the duration difference is greater than or equal to the preset duration threshold, the function of the processor's conversion backup buffer is detected to be normal.

[0012] When it is determined that the duration difference is less than the preset duration threshold, a functional abnormality is detected in the processor's conversion backup buffer.

[0013] Optionally, the step of obtaining the first duration of time spent by the processor executing the first processing instruction capable of achieving a translation backstop hit includes:

[0014] Send a first storage instruction to the processor to write the first data into the memory;

[0015] Obtain the first write completion time corresponding to when the processor completes the data write according to the first storage instruction, and the first virtual page number corresponding to the space where the first data is written;

[0016] The processor is sent the first processing instruction to process the corresponding data. The first processing virtual address in the first processing instruction includes: the first virtual page number and the first offset value, wherein the first offset value is less than the size of a page.

[0017] Obtain the first processing completion time corresponding to when the processor completes data processing according to the first processing instruction;

[0018] The first duration is determined based on the first write completion time and the first processing completion time.

[0019] Optionally, the first offset value is less than a pagination page size and greater than a cache line size.

[0020] Optionally, the step of obtaining the first write completion time corresponding to when the processor completes the data write according to the first storage instruction includes:

[0021] The first count value corresponding to the clock cycle count register when the processor completes the data writing according to the first storage instruction is used to characterize the first write completion time;

[0022] The step of obtaining the first processing completion time corresponding to when the processor completes data processing according to the first processing instruction includes:

[0023] The second count value corresponding to the clock cycle count register when the processor completes data processing according to the first processing instruction is used to characterize the time when the first processing is completed.

[0024] The step of determining the first duration based on the first write completion time and the first processing completion time includes:

[0025] The first duration is determined based on the difference between the second count value and the first count value.

[0026] Optionally, the step of determining the first duration based on the difference between the second count value and the first count value includes:

[0027] The difference between the second count value and the first count value is used to characterize the first duration.

[0028] Optionally, the step of obtaining the second duration of time spent by the processor executing a second processing instruction capable of implementing the missed transition backstop includes:

[0029] Send a second storage instruction to the processor to write the second data into the previous memory;

[0030] Obtain the second write completion time corresponding to when the processor completes the data write according to the second storage instruction, and the second virtual page number corresponding to the space where the second data is written;

[0031] The processor is sent a second processing instruction to process the corresponding data. The second processing virtual address in the first processing instruction includes: the second virtual page number and the second offset value, wherein the second offset value is greater than the size of a page.

[0032] Obtain the second processing completion time corresponding to when the processor completes data processing according to the second processing instruction;

[0033] The second duration is determined based on the second write completion time and the second processing completion time.

[0034] Optionally, the step of obtaining the second write completion time corresponding to when the processor completes the data write according to the second storage instruction includes:

[0035] The third count value corresponding to the clock cycle count register when the processor completes the data writing according to the second storage instruction is used to characterize the second write completion time;

[0036] The step of obtaining the second processing completion time corresponding to when the processor completes data processing according to the second processing instruction includes:

[0037] The fourth count value corresponding to the clock cycle count register when the processor completes data processing according to the second processing instruction is used to characterize the time when the second processing is completed;

[0038] The step of determining the second duration based on the second write completion time and the second processing completion time includes:

[0039] The second duration is determined based on the difference between the fourth count value and the third count value.

[0040] Optionally, the difference between the fourth count value and the third count value can be used to characterize the second duration.

[0041] Optionally, the first processing instruction is a write instruction or a read instruction;

[0042] The first processing instruction is a write instruction or a read instruction.

[0043] Secondly, this disclosure provides a functional verification system, including:

[0044] The first acquisition module is configured to acquire the first duration of time spent by the processor executing a first processing instruction that can be used to achieve a switch back buffer hit.

[0045] The second acquisition module is configured to acquire the second duration of time spent by the processor executing a second processing instruction that can be used to implement the missed transition back buffer;

[0046] The verification module is configured to verify whether the conversion backup buffer has a functional abnormality based on the first duration and the second duration.

[0047] Thirdly, embodiments of this disclosure also provide an electronic device, including:

[0048] Execution processor;

[0049] Memory, used to store one or more programs;

[0050] When the one or more programs are executed by the execution processor, the execution processor implements the functional verification method as provided in the first aspect.

[0051] Fourthly, this disclosure provides a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by an execution processor, implements the steps of the functional verification method provided in the first aspect. Attached Figure Description

[0052] Figure 1 This is a schematic diagram illustrating a specific application scenario involved in this disclosure;

[0053] Figure 2 This is a flowchart of a functional verification method provided in an embodiment of this disclosure;

[0054] Figure 3 This is a flowchart of an optional implementation method of step S1 in this embodiment of the present disclosure;

[0055] Figure 4 This is a schematic diagram of a structure in an embodiment of the present disclosure where no virtual cache is provided in the CPU;

[0056] Figure 5 This is a schematic diagram of a structure in an embodiment of the present disclosure where a virtual cache is provided in the CPU;

[0057] Figure 6 This is a flowchart of an optional implementation method of step S2 in this embodiment of the present disclosure;

[0058] Figure 7 This is a flowchart of an optional implementation method of step S3 in this embodiment of the present disclosure;

[0059] Figure 8 This is a flowchart of a functional verification method provided in an embodiment of this disclosure;

[0060] Figure 9 This is a structural block diagram of a functional verification system provided in an embodiment of this disclosure;

[0061] Figure 10 This is a structural block diagram of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0062] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0063] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the term encompasses the elements or objects listed following the term and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or “connected,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0064] Figure 1 This is a schematic diagram illustrating a specific application scenario involved in this disclosure, such as... Figure 1 As shown, taking the application of the technical solution of this disclosure to a RISC-V processor as an example, the RISC-V processor includes: a CPU (i.e., a processor) and a field-programmable gate array (FPGA).

[0065] The CPU includes a Management Unit (MMU), which primarily manages the control circuitry for virtual and physical memory, mainly responsible for mapping virtual addresses to physical addresses. The basic idea of ​​virtual memory is that the total size of the program, data, and stack can exceed the size of the physical memory space. The operating system stores the currently running portion in memory, while unused portions are stored on disk. If the CPU's MMU is enabled, the processor issues virtual addresses, which are captured by the MMU. The MMU performs address translation, using page tables to look up the virtual address and obtain the final physical address.

[0066] TLB is part of MMU and is essentially a table cache. It caches page table entries (the mapping from virtual address to physical address) for recently used data. Its purpose is to speed up data (memory) access. The CPU doesn't need to go through multiple levels of page table translation; it can directly obtain the virtual-to-physical address mapping from the TLB, reducing redundant page table lookups and accelerating CPU operation.

[0067] In this disclosure, in order to verify whether there is any abnormality in the TLB function of the CPU, it is necessary to develop a corresponding bare-metal program in advance, which includes the source code and linker script of the bare-metal program; run the bare-metal program through the normal boot chip, compile the bare-metal program using the RISC-V toolchain, and load it into the memory of the FPGA through the GDB debugger.

[0068] When the CPU is in machine mode, it uses physical addresses and therefore does not utilize the TLB. To verify if the TLB is malfunctioning, the MMU needs to be enabled in supervisor mode or user mode. 64-bit RISC-V processors typically use the SV39 paging scheme, so this functionality needs to be implemented in a minimal bare-metal program before enabling the MMU. Before verifying TLB malfunction, the RISC-V-based SV39 paging scheme needs to be configured and the MMU enabled. Subsequent verification of TLB malfunction can be achieved via software through interaction between the FPGA and the CPU. A detailed description with specific examples follows.

[0069] Figure 2 This is a flowchart of a functional verification method provided in an embodiment of this disclosure, such as... Figure 2 As shown, this functional verification method is used to verify whether there are functional abnormalities in the TLB, and specifically includes:

[0070] Step S1: Obtain the first time taken for the CPU to execute the first processing instruction that can be used to achieve a TLB hit.

[0071] Step S2: Obtain the second time taken for the CPU to execute the second processing instruction that can be used to implement the TLB Miss.

[0072] Step S3: Verify whether there is a functional abnormality in the TLB based on the first duration and the second duration.

[0073] It should be noted that the technical solution disclosed herein does not limit the execution order of steps S1 and S2. That is, step S1 can be executed before step S2, after step S2, or simultaneously with step S2.

[0074] Generally, when the TLB is functioning normally, the time taken for the CPU to execute instructions when the TLB hits is much shorter (mainly due to the CPU's own operating speed) than the time taken when the TLB misses. Therefore, based on the above principle, in this embodiment of the disclosure, by obtaining the first time taken for the CPU to execute the first processing instruction that can be used to achieve a TLB hit, and the second time taken for the CPU to execute the first processing instruction that can be used to achieve a TLB miss, and then determining whether the TLB is malfunctioning based on the difference between the first and second times.

[0075] Figure 3 This is a flowchart of an optional implementation method of step S1 in this embodiment of the present disclosure, such as... Figure 3 As shown, optionally, step S1 includes:

[0076] Step S101: Send a first store instruction to the CPU to write the first data into memory.

[0077] Step S102: Obtain the first write completion time corresponding to when the CPU completes the data write according to the first storage instruction, and the first virtual page number corresponding to the space where the first data is written.

[0078] The FPGA sends a first store instruction to the CPU to control the CPU to write the first data into memory. The physical address of the first data in memory can be specified by the first store instruction, or determined by the memory according to certain rules (e.g., randomly selecting an unused physical address, selecting unused physical addresses in ascending order, or selecting unused physical addresses in ascending order of historical usage frequency). After the CPU completes writing the first data into memory, the CPU can send feedback to the FPGA to the first write completion time and the first virtual page number VPN1 corresponding to the first data in memory.

[0079] Step S103: Send a first processing instruction to the CPU to process the corresponding data. The first processing virtual address in the first processing instruction includes: a first virtual page number and a first offset value. The first offset value is less than the size of a page.

[0080] In this embodiment of the disclosure, the instruction sent by the FPGA to the CPU in step S101 is a store instruction; the processing instruction sent by the FPGA to the CPU in step S103 can be either a store instruction or a load instruction.

[0081] In this disclosure, a virtual address consists of a virtual page number and an offset.

[0082] The FPGA sends a first processing instruction to the CPU. This instruction contains a first processing virtual address VPN1 and a first offset value Offset1 for the data to be processed. The first processing virtual address VPN1 is obtained in step S102, and the first offset value Offset1 is a pre-set value. Optionally, the first offset value is less than the size of a page.

[0083] Step S104: Obtain the first processing completion time corresponding to when the CPU completes data processing according to the first processing instruction.

[0084] If the TLB functions correctly, the CPU will inevitably achieve a TBL hit during the execution of the first processing instruction. This is because, if the TLB functions correctly, after the CPU executes the first store instruction in step S101, the TLB will automatically cache the page table entries of the most recently used data. The TLB's "Tab" (also known as the page table buffer) will contain page table entries with the first virtual page number and its corresponding physical page frame number. Therefore, the CPU will complete data processing quickly and in a short time according to the first processing instruction. Conversely, if the TLB malfunctions, the CPU will complete data processing slowly and in a longer time according to the first processing instruction.

[0085] Step S105: Determine the first duration based on the first write completion time and the first processing completion time.

[0086] Optionally, in step S105, the first duration can be obtained by subtracting the first processing completion time and the first write completion time. If the TLB functions normally, the first duration is relatively short; if the TLB functions abnormally, the first duration is relatively long.

[0087] Figure 4 This is a schematic diagram of a structure in an embodiment of this disclosure where no virtual cache is provided in the CPU, as shown below. Figure 4As shown, in some embodiments, when no virtual cache is set in the CPU, the CPU will directly send the virtual address in the received instruction to the TLB in the MMU for TLB matching.

[0088] Figure 5 This is a schematic diagram of a structure in an embodiment of the present disclosure where a virtual cache is provided within the CPU, as shown below. Figure 5 As shown, in some embodiments, to further improve CPU processing efficiency, in addition to a TLB, a Virtually-Indexed Virtually-Tagged Cache (VIVT Cache) is also set up within the CPU. The VIVT Cache uses virtual addresses (VA) as lookup objects. When the CPU issues a virtual address, the cache searches for the corresponding cache line in the cache based on the index part of the sent virtual address. It compares the tag part of the found cache line with the tag part of the virtual address. If the tags match, a cache hit occurs. Then, the validity bit in the cache line is used to determine if the data in the cache line is valid. If valid, the corresponding data is found based on the offset part of the virtual address and returned to the CPU. If a mismatch is found during the tag comparison, a cache miss occurs. In this case, the virtual address needs to be translated into a physical address through the MMU (which includes the TLB), and the corresponding main memory data storage address is found based on the physical address before the data is returned to the CPU.

[0089] As can be seen from the above, when the CPU memory is in the VIVT cache, the virtual address is first matched against the VIVT cache, and only if the cache misses does the TLB match occur. In this disclosure, to avoid a cache hit at the first virtual address in the first processing instruction, which would prevent the subsequent TLB matching process from proceeding, the first offset value can be set to be less than one page (generally 2). m (Bytes, m value is preset according to actual needs) size and greater than one cache line (usually 2 bytes). n The size of the first offset is byte, and the value of n is preset according to actual needs, and n is less than m. This is because when the first offset value is greater than the size of a cache line, a cache miss will occur.

[0090] Figure 6 This is a flowchart of an optional implementation method of step S2 in this embodiment of the present disclosure, such as... Figure 6 As shown, optionally, step S2 includes:

[0091] Step S201: Send a second storage instruction to the CPU to write the second data into the previous memory.

[0092] Step S202: Obtain the second write completion time corresponding to when the CPU completes the data write according to the second storage instruction, and the second virtual page number corresponding to the space where the second data is written.

[0093] The FPGA sends a second store instruction to the CPU to control the CPU to write second data into memory. The physical address of the second data in memory can be specified by the second store instruction, or determined by the memory according to certain rules. After the CPU completes writing the second data into memory, the CPU can send feedback to the FPGA to the second write completion time and the second virtual page number corresponding to the second data in memory.

[0094] Step S203: Send a second processing instruction to the CPU to process the corresponding data. The second processing virtual address in the first processing instruction includes: a second virtual page number and a second offset value. The second offset value is greater than the size of a page.

[0095] In this embodiment of the disclosure, the instruction sent by the FPGA to the CPU in step S201 is a store instruction; the processing instruction sent by the FPGA to the CPU in step S203 can be either a store instruction or a load instruction.

[0096] The FPGA sends a second processing instruction to the CPU. This instruction contains a second processing virtual address VPN2 and a second offset value Offset2 for the data to be processed. The second processing virtual address VPN2 is obtained in step S202, and the second offset value Offset2 is a preset value. Optionally, the second offset value is greater than the size of a page.

[0097] Step S204: Obtain the second processing completion time corresponding to when the CPU completes data processing according to the second processing instruction.

[0098] Because the first offset value is larger than the size of a page, the CPU will experience cache misses (if the CPU memory is in the VIVT cache) and TLB misses when translating virtual addresses to physical addresses. This will slow down the CPU's data processing speed according to the second processing instruction, resulting in a longer processing time.

[0099] Step S205: Determine the second duration based on the second write completion time and the second processing completion time.

[0100] Optionally, in step S205, the second duration can be obtained by subtracting the second processing completion time and the second write completion time. Since a TLB miss will inevitably occur during the CPU's execution of the second processing instruction, the second duration is relatively large.

[0101] Figure 7 This is a flowchart of an optional implementation method for step S3 in an embodiment of this disclosure, such as... Figure 7 As shown, in some embodiments, step S3 includes:

[0102] Step S301: Calculate the difference between the second duration and the first duration to obtain the duration difference value;

[0103] Step S302: Determine whether the duration difference is greater than the preset duration threshold.

[0104] The specific value of the preset duration threshold used for comparison with the duration difference can be reasonably designed and adjusted based on actual experience. This disclosure does not limit the specific value of the preset duration threshold.

[0105] When step S302 determines that the duration difference is greater than or equal to the preset duration threshold, it indicates that the difference between the first duration and the second duration is large, and the TLB function is normal. When step S302 determines that the duration difference is less than the preset duration threshold, it indicates that the difference between the first duration and the second duration is small, and the TLB function is abnormal.

[0106] Figure 8 This is a flowchart of a functional verification method provided in an embodiment of this disclosure, such as... Figure 8 As shown, Figure 8 For based on Figure 2 One specific alternative implementation of the method shown includes the following functional verification method:

[0107] Step S101': Send the first store instruction to the CPU to write the first data into memory.

[0108] Step S102': Use the first count value corresponding to the clock cycle count register when the CPU completes the data writing according to the first storage instruction to represent the first write completion time, and obtain the first virtual page number corresponding to the space where the first data is written.

[0109] That is, the first time the write is completed can be recorded as the first count value C1.

[0110] Step S103': Send a first processing instruction to the CPU to process the corresponding data. The first processing virtual address in the first processing instruction includes: a first virtual page number and a first offset value. The first offset value is less than the size of a page.

[0111] Step S104': Use the second count value corresponding to the clock cycle count register when the CPU completes data processing according to the first processing instruction to characterize the time when the first processing is completed.

[0112] That is, the time when the first processing is completed can be recorded as the second count value C2.

[0113] Step S105': Determine the first duration based on the first write completion time and the first processing completion time.

[0114] In some embodiments, step S105' specifically includes: using the difference C2-C1 between the second count value and the first count value to characterize the first duration. That is, the first duration can be recorded as the difference between C2 and C1.

[0115] Of course, in another embodiment, the difference between the second count value and the first count value can be calculated, and then the difference can be multiplied by the duration corresponding to one clock cycle t, and the product can be used as the first duration.

[0116] Step S201': Send a second storage instruction to the CPU to write the second data into the previous memory.

[0117] Step S202': Use the third count value corresponding to the clock cycle count register when the CPU completes the data writing according to the second storage instruction to characterize the second write completion time, and obtain the second virtual page number corresponding to the space where the second data is written.

[0118] That is, the second write completion time can be recorded as the third count value C3.

[0119] Step S203': Send a second processing instruction to the CPU to process the corresponding data. The second processing virtual address in the first processing instruction includes: a second virtual page number and a second offset value. The second offset value is greater than the size of a page.

[0120] Step S204': Use the fourth count value corresponding to the clock cycle count register when the CPU completes data processing according to the second processing instruction to characterize the time when the second processing is completed.

[0121] That is, the time when the second processing is completed can be recorded as the fourth count value C4.

[0122] Step S205': Determine the second duration based on the second write completion time and the second processing completion time.

[0123] In some embodiments, step S205' specifically includes: using the difference C4-C3 between the fourth count value and the third count value to characterize the second duration. That is, the second duration can be recorded as the difference between C4 and C3.

[0124] Of course, in another embodiment, the difference between the fourth count value and the third count value can be calculated, and then multiplied by the duration corresponding to one clock cycle, and the product can be used as the second duration.

[0125] Step S301': Calculate the difference between the second duration and the first duration to obtain the duration difference value.

[0126] Step S302': Determine whether the duration difference is greater than the preset duration threshold.

[0127] In some embodiments, the second duration is C4-C3, the first duration is C2-C1, and the duration difference is: C4-C3-(C2-C1). In this case, the preset duration threshold can be greater than or equal to 50, for example, the preset duration threshold is 50, 70, 100, etc.

[0128] In other embodiments, the second duration is (C4-C3)*t, the first duration is (C2-C1)*t, and the duration difference is [(C4-C3)-(C2-C1)]*t. In this case, the preset duration threshold can be greater than or equal to 50*t. For example, the preset duration threshold can be 50*t, 70*t, 100*t, etc.

[0129] The specific value of the preset duration threshold used for comparison with the duration difference can be reasonably designed and adjusted based on actual experience. This disclosure does not limit the specific value of the preset duration threshold.

[0130] When step S302' determines that the duration difference is greater than or equal to the preset duration threshold, it indicates that the difference between the first duration and the second duration is large, and the TLB function is normal. When step S302' determines that the duration difference is less than the preset duration threshold, it indicates that the difference between the first duration and the second duration is small, and the TLB function is abnormal.

[0131] Based on the same inventive concept, this disclosure also provides a functional verification system. Figure 9 This is a structural block diagram of a functional verification system provided in an embodiment of this disclosure, such as... Figure 9 As shown, the functional verification system can be used to implement the functional verification method in the above embodiment. The functional verification system includes: a first acquisition module 1, a second acquisition module 2, and a verification module 3.

[0132] The first acquisition module 1 is configured to acquire the first time taken by the CPU to execute the first processing instruction that can be used to achieve a TLB hit.

[0133] The second acquisition module 2 is configured to acquire the second duration of time spent by the CPU executing a second processing instruction that can be used to implement a TLB miss.

[0134] Verification module 3 is configured to verify whether there is a functional abnormality in the TLB based on the first duration and the second duration.

[0135] The first acquisition module 1 in this embodiment can be used to execute step S1 in the above embodiment, the second acquisition module 2 can be used to execute step S2 in the above embodiment, and the detection module 3 can be used to execute step S3 in the above embodiment. For a detailed description of each of the above modules, please refer to the corresponding memory in the previous embodiment, which will not be repeated here.

[0136] Based on the same inventive concept, this disclosure also provides an electronic device. Figure 10 This is a structural block diagram of an electronic device provided in an embodiment of this disclosure, such as... Figure 10 As shown, the electronic device includes: an execution processor 101, a memory 102, and one or more I / O interfaces 103. The memory 102 stores one or more programs, which, when executed by the one or more processors, cause the one or more processors to implement any of the functional verification methods described in the above embodiments; the one or more I / O interfaces 103 are connected between the processor and the memory, configured to enable information interaction between the processor and the memory.

[0137] The processor 101 is a device with data processing capabilities; the memory 102 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read-write interface) 103 is connected between the processor 101 and the memory 102, and can realize information interaction between the processor 101 and the memory 102, including but not limited to data bus (Bus).

[0138] In some embodiments, the execution processor 101, memory 102, and I / O interface 103 are interconnected via bus 104, and thus connected to other components of the computing device.

[0139] In some embodiments, the execution processor 101 includes an FPGA; a program in memory may be loaded into the FPGA before implementing the functional verification method provided in this disclosure.

[0140] In some embodiments, the execution processor may be a RISC-V processor.

[0141] According to embodiments of this disclosure, a computer-readable medium is also provided. This computer-readable medium stores a computer program, which, when executed by an execution processor, implements the steps of any of the functional verification methods described in the above embodiments.

[0142] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a machine-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication component, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), it performs the functions defined above in the system of this disclosure.

[0143] It should be noted that the computer-readable medium disclosed herein may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0144] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0145] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A functional verification method, characterized in that, include: Get the first duration of time spent by the processor executing the first processing instruction that can be used to achieve a translation back buffer hit; The second duration of time spent by the processor executing a second processing instruction that can be used to implement the second processing instruction that was missed by the transition back buffer is obtained; The first duration and the second duration are used to verify whether the conversion backup buffer has a functional abnormality; The step of verifying whether the function of the acquisition processor's conversion backup buffer is abnormal based on the first duration and the second duration includes: Calculate the difference between the second duration and the first duration to obtain the duration difference value; Determine whether the duration difference is greater than a preset duration threshold; When it is determined that the duration difference is greater than or equal to the preset duration threshold, the function of the conversion backup buffer is detected to be normal. When it is determined that the duration difference is less than the preset duration threshold, a functional abnormality is detected in the conversion backup buffer.

2. The functional verification method according to claim 1, characterized in that, The step of obtaining the first time taken by the processor to execute the first processing instruction that can be used to achieve a translation back buffer hit includes: Send a first storage instruction to the processor to write the first data into the memory; Obtain the first write completion time corresponding to when the processor completes the data write according to the first storage instruction, and the first virtual page number corresponding to the space where the first data is written; The processor is sent the first processing instruction to process the corresponding data. The first processing virtual address in the first processing instruction includes: the first virtual page number and the first offset value, wherein the first offset value is less than the size of a page. Obtain the first processing completion time corresponding to when the processor completes data processing according to the first processing instruction; The first duration is determined based on the first write completion time and the first processing completion time.

3. The functional verification method according to claim 2, characterized in that, The first offset value is less than the size of a pagination page and greater than the size of a cache line.

4. The functional verification method according to claim 2, characterized in that, The step of obtaining the first write completion time corresponding to when the processor completes the data write according to the first storage instruction includes: The first count value corresponding to the clock cycle count register when the processor completes the data writing according to the first storage instruction is used to characterize the first write completion time; The step of obtaining the first processing completion time corresponding to when the processor completes data processing according to the first processing instruction includes: The second count value corresponding to the clock cycle count register when the processor completes data processing according to the first processing instruction is used to characterize the time when the first processing is completed. The step of determining the first duration based on the first write completion time and the first processing completion time includes: The first duration is determined based on the difference between the second count value and the first count value.

5. The functional verification method according to claim 4, characterized in that, The step of determining the first duration based on the difference between the second count value and the first count value includes: The difference between the second count value and the first count value is used to characterize the first duration.

6. The functional verification method according to claim 1, characterized in that, The step of obtaining the second duration of time spent by the processor executing a second processing instruction that can be used to implement the second processing instruction that was missed by the translation backstop buffer includes: Send a second storage instruction to the processor to write the second data into the previous memory; Obtain the second write completion time corresponding to when the processor completes the data write according to the second storage instruction, and the second virtual page number corresponding to the space where the second data is written; The processor is sent a second processing instruction to process the corresponding data. The second processing virtual address in the first processing instruction includes: the second virtual page number and the second offset value, wherein the second offset value is greater than the size of a page. Obtain the second processing completion time corresponding to when the processor completes data processing according to the second processing instruction; The second duration is determined based on the second write completion time and the second processing completion time.

7. The functional verification method according to claim 6, characterized in that, The step of obtaining the second write completion time corresponding to when the processor completes the data write according to the second storage instruction includes: The third count value corresponding to the clock cycle count register when the processor completes the data writing according to the second storage instruction is used to characterize the second write completion time; The step of obtaining the second processing completion time corresponding to when the processor completes data processing according to the second processing instruction includes: The fourth count value corresponding to the clock cycle count register when the processor completes data processing according to the second processing instruction is used to characterize the time when the second processing is completed; The step of determining the second duration based on the second write completion time and the second processing completion time includes: The second duration is determined based on the difference between the fourth count value and the third count value.

8. The functional verification method according to claim 7, characterized in that, The difference between the fourth count value and the third count value is used to characterize the second duration.

9. The functional verification method according to any one of claims 1 to 8, characterized in that, The first processing instruction is a write instruction or a read instruction; The second processing instruction is a write instruction or a read instruction.

10. A functional verification system, characterized in that, include: The first acquisition module is configured to acquire the first duration of time spent by the processor executing a first processing instruction that can be used to achieve a switch back buffer hit. The second acquisition module is configured to acquire the second duration of time spent by the processor executing a second processing instruction that can be used to implement the missed transition back buffer; The verification module is configured to verify whether the conversion backup buffer has a functional abnormality based on the first duration and the second duration. The step of verifying whether the function of acquiring the processor's conversion backup buffer is abnormal based on the first duration and the second duration includes: Calculate the difference between the second duration and the first duration to obtain the duration difference value; Determine whether the duration difference is greater than a preset duration threshold; When it is determined that the duration difference is greater than or equal to the preset duration threshold, the function of the conversion backup buffer is detected to be normal. When it is determined that the duration difference is less than the preset duration threshold, a functional abnormality is detected in the conversion backup buffer.

11. An electronic device, characterized in that, include: Execution processor; Memory, used to store one or more programs; When the one or more programs are executed by the execution processor, the execution processor implements the functional verification method as described in any one of claims 1 to 9.

12. A computer-readable medium having a computer program stored thereon, wherein, When the computer program is executed by an execution processor, it implements the steps of the functional verification method as described in any one of claims 1 to 9.

Images