Data processing unit, data processing method, and electronic device

Abstract

The present disclosure provides a data processing unit, relates to the technical field of computers, and particularly relates to the technical field of cache. The data processing unit comprises: a processor core configured to send a memory access request; and a first cache unit comprising an instruction queue and a data queue, the instruction queue being configured to store instruction information to be executed, and the data queue being configured to store a load address and a store address; the first cache unit being configured to: in response to receiving the memory access request from the processor core, determining whether to accept the memory access request according to the memory access request, the instruction queue and the data queue; in the case of determining to accept the memory access request, performing an operation corresponding to the memory access request, and in the case of determining not to accept the memory access request, sending an indication of rejecting the memory access request to the processor core. The present disclosure further provides a data processing method, an electronic device and a storage medium.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more particularly to the field of cache technology. More specifically, this disclosure provides a data processing unit, an electronic device, a data processing method, and a storage medium. Background Technology

[0002] With the development of computer technology, processors can include at least one processor core and multiple levels of cache. Summary of the Invention

[0003] This disclosure provides a data processing unit, a data processing method, an electronic device, and a storage medium.

[0004] According to one aspect of this disclosure, a data processing unit is provided, comprising: a processor core configured to send a memory access request; and a first cache unit including an instruction queue and a data queue, the instruction queue for storing instructions to be executed, and the data queue for storing load addresses and storage addresses; the first cache unit is configured to: in response to receiving a memory access request from the processor core, determine whether to accept the memory access request based on the memory access request, the instruction queue, and the data queue; if it is determined that the memory access request is accepted, perform an operation corresponding to the memory access request; and if it is determined that the memory access request is not accepted, send an indication to the processor core to reject the memory access request.

[0005] According to another aspect of this disclosure, an electronic device is provided, including: a data processing unit provided in this disclosure; and a second cache unit.

[0006] According to another aspect of this disclosure, a data processing method is provided, the method comprising: responding to a memory access request from a processor core, determining whether to accept the memory access request based on the memory access request, an instruction queue of a first cache unit, and a data queue of the first cache unit, wherein the instruction queue is used to store instruction information to be executed, and the data queue is used to store load address and storage address; if it is determined that the memory access request is accepted, performing an operation corresponding to the memory access request; and if it is determined that the memory access request is not accepted, sending an indication to the processor core to reject the memory access request.

[0007] According to another aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a method provided according to this disclosure.

[0008] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions for causing a computer to perform the methods provided according to this disclosure.

[0009] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the method provided according to this disclosure.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0011] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0012] Figure 1 This is a schematic block diagram of a data processing unit according to an embodiment of the present disclosure;

[0013] Figure 2 This is a schematic diagram of a first cache unit according to an embodiment of the present disclosure;

[0014] Figure 3 This is a schematic diagram illustrating the execution of an operation corresponding to a memory access request according to an embodiment of this disclosure;

[0015] Figure 4 This is a schematic diagram illustrating the execution of an operation corresponding to a memory access request according to another embodiment of this disclosure;

[0016] Figure 5 This is a schematic diagram illustrating the execution of an operation corresponding to a memory access request according to another embodiment of this disclosure;

[0017] Figure 6 This is a schematic diagram illustrating the execution of an operation corresponding to a memory access request according to another embodiment of this disclosure;

[0018] Figure 7 This is a schematic diagram illustrating the execution of an operation corresponding to a memory access request according to another embodiment of this disclosure;

[0019] Figure 8 This is a schematic diagram illustrating the execution of an operation corresponding to a memory access request according to another embodiment of this disclosure;

[0020] Figure 9 This is a schematic diagram illustrating the execution of an operation corresponding to a memory access request according to another embodiment of this disclosure;

[0021] Figure 10This is a schematic diagram illustrating the execution of an operation corresponding to a memory access request according to another embodiment of this disclosure;

[0022] Figure 11 This is a flowchart of a data processing method according to an embodiment of the present disclosure;

[0023] Figure 12 This is a schematic block diagram of an electronic device according to an embodiment of the present disclosure; and

[0024] Figure 13 This is a block diagram of an electronic device to which a data processing method can be applied, according to an embodiment of the present disclosure. Detailed Implementation

[0025] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0026] The processor's Load Store Unit (LSU) can optimize load instructions to reduce memory access latency. For example, multi-level caches can be used to reduce cache latency. For instance, the processor core can initiate a memory access request. This request can be processed by the LSU, the L1 Data Cache, and the L2 Data Cache. The LSU can determine the execution order of multiple memory access instructions. When a memory access request is received by the L1 Data Cache, if the address corresponding to the request is found within that L1 Data Cache, a cache hit occurs. The data corresponding to the request can then be read from the L1 Data Cache and written back to the LSU, and finally back to the processor core. If the address corresponding to the request does not exist in the L1 Data Cache, the request can be sent to the L2 Cache. When the address corresponding to the request exists in the L1 Data Cache, the time from the processor core initiating the load request to receiving the written-back data is approximately 3 to 5 cycles. If the address corresponding to the memory access request exists in the first-level data cache, the time required from the processor core initiating a load request to receiving the write-back data is approximately tens or even hundreds of cycles.

[0027] In artificial intelligence scenarios, processors can access contiguous address data consecutively. This contiguous access can lead to most memory access requests being cache-hit. However, even if a cache hit occurs, there will still be a read latency of 3 to 5 cycles, which does not benefit the overall processor performance.

[0028] Figure 1 This is a schematic block diagram of a data processing unit according to an embodiment of the present disclosure.

[0029] like Figure 1 As shown, the data processing unit 100 may include a processor core 110 and a first cache unit 120.

[0030] Processor core 110 is configured to send memory access requests. For example, there can be at least one processor core.

[0031] The first cache unit 120 includes an instruction queue and a data queue.

[0032] In this embodiment, the first cache unit can be a Level 0 cache (L0 cache). For example, the first cache unit can be located between the second cache unit and the processor core. The second cache unit can be the Level 1 data cache described above. Memory access requests can be processed sequentially by the memory access unit, the first cache unit, and the second cache unit.

[0033] In this embodiment of the disclosure, the instruction queue can store instruction information to be executed. For example, the instruction information to be executed may include at least one of the following: memory access instruction information, write-back instruction information, thread identifier (ID), and data type. The instruction queue may be a first-in-first-out (FIFO) queue.

[0034] In this embodiment of the disclosure, the data queue can store: a load address and a storage address. The data queue can also be a first-in-first-out queue.

[0035] In this embodiment of the disclosure, the first cache unit 120 may be configured to: in response to receiving a memory access request from the processor core, determine whether to accept the memory access request based on the memory access request, the instruction queue, and the data queue.

[0036] In this embodiment of the disclosure, upon determining that a memory access request will be accepted, an operation corresponding to the memory access request is executed. For example, if the memory access request is a load request, and storage space exists in both the instruction queue and the data queue, the memory access request can be accepted. Next, an operation corresponding to the memory access request can be executed. This operation may include sending a request to the first-level data cache or writing the relevant data back to the processor core.

[0037] In this embodiment of the disclosure, if it is determined that a memory access request will not be accepted, an indication to reject the memory access request is sent to the processor core. For example, if it is determined that there is load instruction information related to the memory request in the instruction queue, there is a memory address corresponding to the memory request in the data queue, and there is no remaining storage space in the data queue, the memory request can be rejected, and an indication to reject the memory access request can be sent to the processor core.

[0038] The embodiments of this disclosure include a first cache unit, which enables more efficient handling of memory access requests and helps improve chip performance. Furthermore, the first cache unit incorporates a data queue capable of storing load addresses and memory addresses, allowing for flexible adaptation to various scenarios. For example, in cases of numerous memory requests, the data queue can store a larger number of memory addresses to efficiently handle a large volume of requests. In cases of numerous load requests, the data queue can act as a high-speed cache, reducing write-back latency for load instructions. Thus, it effectively adapts to scenarios with numerous memory and load requests, improving chip resource utilization and further enhancing chip performance.

[0039] It is understood that the data processing unit of this disclosure has been described above, and the first cache unit will be further described below in conjunction with relevant embodiments.

[0040] Figure 2 This is a schematic diagram of a first cache unit according to an embodiment of the present disclosure.

[0041] like Figure 2 As shown, the first cache unit 220 may include an instruction queue 221 and a data queue 222.

[0042] Instruction queue 221 includes multiple storage spaces for storing instructions to be executed. Instruction queue 221 can be a first-in, first-out (FIFO) queue. The enqueue pointer of instruction queue 221 indicates the storage space for instructions to be added to the queue. The dequeue pointer of instruction queue 221 indicates the storage space for instructions to be removed from the queue. The execution pointer of instruction queue 221 indicates the storage space for instructions to be executed.

[0043] Storage queue 222 includes multiple storage spaces, which can store at least one of a load address and a storage address. Storage queue 222 can be a first-in-first-out (FIFO) queue. The enqueue pointer of storage queue 222 can indicate the storage space of a load address or storage address to be added to the queue. The dequeue pointer of storage queue 222 can indicate the storage space of a load address or storage address to be removed from the queue.

[0044] As can be understood, the first cache unit has been described above, and the first cache unit will be further described below in conjunction with relevant embodiments.

[0045] In some embodiments, the memory access request includes a load request, and the instruction information includes the load address and thread information. For example, the thread information may include a thread identifier. The following will combine... Figures 3 to 6 The first cache unit of this disclosure will be further described.

[0046] Figure 3 This is a schematic diagram illustrating the execution of an operation corresponding to a memory access request according to an embodiment of the present disclosure.

[0047] like Figure 3 As shown, the first cache unit 320 may include an instruction queue 321 and a data queue 322. A load request 301 may include a target address `addr` and a target thread identifier `thread_id`. For load request 301, the value of the target address `addr` can be 0, and the target thread identifier `thread_id` can also be 0. It should be understood that the values ​​of the address and the thread identifier in this embodiment are merely examples.

[0048] In this embodiment of the disclosure, the first cache unit is further configured to: query the instruction queue and the data queue in response to receiving a load request from the processor core.

[0049] For example, the first cache unit is configured to query the instruction queue to determine if instruction information corresponding to the load request exists. Figure 3 As shown, instruction queue 321 contains multiple instruction messages. For load instruction message 3211, the address `addr` value is "0x1000" and the thread identifier `thread_id` value is 1, which corresponds to a load request. For load instruction message 3212, the address `addr` value is "0x2000" and the thread identifier `thread_id` value is 2, which also corresponds to a load request. For load instruction message 3213, the address `addr` value is "0x5000" and the thread identifier `thread_id` value is 5, which also corresponds to a load request. As mentioned above, the target address `addr` value can be 0, corresponding to the hexadecimal number "0x0000", confirming that there is no instruction message corresponding to a load request in instruction queue 321.

[0050] For example, the first cache unit is configured to query the data queue to determine if a load address corresponding to the load request exists. Figure 3 As shown, multiple addresses exist in data queue 322. The value of load address 3221 is "0". The value of load address 3222 is "0x6000". As mentioned above, the value of the target address addr can be 0, which confirms that load address 3221 corresponding to load request 301 exists in data queue 322.

[0051] If it is determined that there is no instruction information corresponding to load request 301 in instruction queue 321 and there is a load address corresponding to load request 301 in data queue 322, then load request 301 can be accepted. Next, the operation corresponding to load request 301 can be executed.

[0052] In this embodiment, the first cache unit is further configured to: load the load address from the data queue when it is determined that there is no instruction information corresponding to the load request in the instruction queue and there is a load address corresponding to the load request in the data queue; and write the load address back to the processor core. For example, the load address 3221 can be loaded from the data queue 322. The load address 3221 is then written back to the processor core. Through this embodiment, the latency of the load request can be reduced, and chip efficiency can be improved.

[0053] It is understood that the above explanation used the example of the instruction queue not containing instruction information corresponding to the load request. However, this disclosure is not limited to this; the instruction queue may contain instruction information corresponding to the load request, as will be explained below.

[0054] Figure 4 This is a schematic diagram illustrating the execution of an operation corresponding to a memory access request according to another embodiment of this disclosure.

[0055] like Figure 4 As shown, the first cache unit 420 may include an instruction queue 421 and a data queue 422. A load request 402 may include a target address `addr` and a target thread identifier `thread_id`. For load request 402, the value of the target address `addr` can be 0, and the value of the target thread identifier `thread_id` can also be 0. It should be understood that the values ​​of the address and the thread identifier in this embodiment are merely examples.

[0056] In this embodiment of the disclosure, the first cache unit is further configured to: query the instruction queue and the data queue in response to receiving a load request from the processor core.

[0057] For example, the first cache unit is configured to query the instruction queue to determine if instruction information corresponding to the load request exists. Figure 4As shown, instruction queue 421 contains multiple instruction messages. For load instruction message 4211, the value of address `addr` is "0x1000", and the value of thread identifier `thread_id` is 1, which corresponds to a load request. For load instruction message 4214, the value of address `addr` is "0x0", and the value of thread identifier `thread_id` is 0, which also corresponds to a load request. As mentioned above, the value of the target address `addr` is 0, corresponding to the hexadecimal number "0x0", which is consistent with the address of load instruction message 4214. The value of the target thread identifier `thread_id` is 0, consistent with the thread identifier of load instruction message 4214, confirming that load request 402 corresponds to load instruction message 4214.

[0058] For example, the first cache unit is configured to query the data queue to determine if a load address corresponding to the load request exists. Figure 4 As shown, multiple addresses exist in data queue 422. The value of address 4221 is "0". The value of address 4222 is "0x6000". As mentioned above, the value of the target address addr can be 0, which confirms that there exists a load address 4221 corresponding to load request 402.

[0059] If it is determined that there is instruction information corresponding to load request 402 in instruction queue 421 and a load address corresponding to load request 402 in data queue 422, load request 402 can be accepted. Next, the operation corresponding to load request 402 can be executed.

[0060] In this embodiment, the first cache unit is further configured to: add the load request to the instruction queue when it is determined that there is corresponding instruction information in the instruction queue and a load address corresponding to the load request exists in the data queue; and, in response to determining that the corresponding instruction information has been executed, load the load address from the data queue and write the load address back to the processor core. For example, the load request 402 can be stored as a load instruction in the remaining storage space 4215 of the instruction queue. After determining that the instruction information 4214 has been executed, the load address 4221 is loaded from the data queue 422 and written back to the processor core. Through this embodiment, the latency of the load request can be reduced, and chip efficiency can be improved.

[0061] It is understood that the above explanation uses the example of a data queue containing a load address corresponding to a load request to illustrate this disclosure. However, this disclosure is not limited to this; the data queue may also not contain a load address, as will be further explained below.

[0062] Figure 5 This is a schematic diagram illustrating the execution of an operation corresponding to a memory access request according to another embodiment of this disclosure.

[0063] like Figure 5 As shown, the first cache unit 520 may include an instruction queue 521 and a data queue 522. A load request 503 may include a target address `addr` and a target thread identifier `thread_id`. For load request 503, the value of the target address `addr` can be 0, and the value of the target thread identifier `thread_id` can also be 0. It should be understood that the values ​​of the address and the thread identifier in this embodiment are merely examples.

[0064] In this embodiment of the disclosure, the first cache unit is further configured to: query the instruction queue and the data queue in response to receiving a load request from the processor core.

[0065] For example, the first cache unit is configured to query the instruction queue to determine if instruction information corresponding to the load request exists. Figure 5 As shown, instruction queue 521 contains multiple instruction messages. For load instruction message 5211, the address `addr` value is "0x1000" and the thread identifier `thread_id` value is 1, which corresponds to a load request. For load instruction message 5216, the address `addr` value is "0x6000" and the thread identifier `thread_id` value is 0, which corresponds to a load request. For storage instruction message 5217, the address `addr` value is "0x4000" and the thread identifier `thread_id` value is 0, which corresponds to a storage request. For load instruction message 5218, the address `addr` value is "0x8000" and the thread identifier `thread_id` value is 0, which corresponds to a load request. For load instruction message 5219, the address `addr` value is "0x1000" and the thread identifier `thread_id` value is 1, which corresponds to a load request. As mentioned above, the target address `addr` value is 0, corresponding to the hexadecimal number "0x0", indicating that instruction queue 521 does not contain instruction message corresponding to load request 503.

[0066] For example, the first cache unit is configured to query the data queue to determine if a load address corresponding to the load request exists. Figure 5 As shown, multiple addresses exist in data queue 522. The value of load address 5222 is "0x6000". The value of load address 5223 is "0x4000". The value of load address 5224 is "0x8000". The value of load address 5225 is "0x1000". As mentioned above, the value of the target address addr can be 0, which confirms that there is no load address in data queue 522 corresponding to load request 503. Furthermore, it can be determined that data queue 522 has no remaining storage space.

[0067] If it is determined that there is no instruction information corresponding to load request 503 in instruction queue 521 and no load address corresponding to load request 503 in data queue 522, load request 503 can be accepted. Next, the operation corresponding to load request 503 can be executed.

[0068] In this embodiment of the disclosure, the first cache unit is further configured to: add the load request to the instruction queue when it is determined that there is no corresponding instruction information in the instruction queue, no load address in the data queue, and no remaining storage space in the data queue; and send the load request to the second cache unit. For example, the load request 503 can be stored as a load instruction information in the remaining storage space 52110 of the instruction queue 521. Furthermore, when there is no remaining storage space in the data queue 522, the load request 503 can be sent to the first-level data cache, which serves as the second cache unit, to query whether there is a load address corresponding to the load request 503 in the first-level data cache.

[0069] Figure 6 This is a schematic diagram illustrating the execution of an operation corresponding to a memory access request according to another embodiment of this disclosure.

[0070] like Figure 6 As shown, the first cache unit 620 may include an instruction queue 621 and a data queue 622. A load request 604 may include a target address `addr` and a target thread identifier `thread_id`. For load request 604, the value of the target address `addr` can be 0, and the value of the target thread identifier `thread_id` can also be 0. It should be understood that the values ​​of the address and the thread identifier in this embodiment are merely examples.

[0071] In this embodiment of the disclosure, the first cache unit is further configured to: query the instruction queue and the data queue in response to receiving a load request from the processor core.

[0072] For example, the first cache unit is configured to query the instruction queue to determine if instruction information corresponding to the load request exists. Figure 6As shown, instruction queue 621 contains multiple instruction messages. For load instruction message 6211, the value of address `addr` is "0x1000" and the value of thread identifier `thread_id` is 1, which corresponds to a load request. For storage instruction message 6216', the value of address `addr` is "0x6000" and the value of thread identifier `thread_id` is 0, which corresponds to a storage request. For load instruction message 6217', the value of address `addr` is "0x4000" and the value of thread identifier `thread_id` is 0, which corresponds to a load-store request. For load instruction message 6218, the value of address `addr` is "0x8000" and the value of thread identifier `thread_id` is 0, which corresponds to a load request. For load instruction message 6219, the value of address `addr` is "0x1000" and the value of thread identifier `thread_id` is 1, which corresponds to a load request. As mentioned above, the value of the target address addr is 0, and the corresponding hexadecimal number is "0×0". It can be determined that there is no instruction information in instruction queue 621 corresponding to load request 604.

[0073] For example, the first cache unit is configured to query the data queue to determine if a load address corresponding to the load request exists. Figure 6 As shown, multiple addresses exist in data queue 622. The value of storage address 6222' is "0x6000". The value of load address 6223 is "0x4000". The value of load address 6224 is "0x8000". As mentioned above, the value of the target address addr can be 0, which confirms that there is no load address in data queue 622 corresponding to load request 604. Furthermore, it can be determined that there is remaining storage space 6226 in data queue 622.

[0074] If it is determined that there is no instruction information corresponding to load request 604 in instruction queue 621 and no load address corresponding to load request 604 in data queue 622, load request 604 can be accepted. Next, the operation corresponding to load request 604 can be executed.

[0075] In this embodiment, the first cache unit is further configured to: add the load request to the instruction queue, add the load address to the data queue, and send the load request to the second cache unit when it is determined that there is no corresponding instruction information in the instruction queue, no load address in the data queue, and remaining storage space in the data queue. For example, the load request 604 can be stored as instruction information in the remaining storage space 62110 of the instruction queue 621. The target address can be added as a load address to the remaining storage space 6226 of the data queue 622. In addition, the load request 604 can be sent to the first-level data cache, which is the second cache unit, to query whether there is a load address corresponding to the load request 604 in the first-level data cache.

[0076] The preceding text uses the example of a memory access request being a load request to illustrate the first cache unit of this disclosure. However, this disclosure is not limited to this; a memory access request can also be a storage request, and the instruction information includes the storage address and thread information. The following will combine... Figures 7 to 10 Further explanation is needed.

[0077] Figure 7 This is a schematic diagram illustrating the execution of an operation corresponding to a memory access request according to another embodiment of this disclosure.

[0078] like Figure 7 As shown, the first cache unit 720 may include an instruction queue 721 and a data queue 722. A storage request 705 may include a target address `addr` and a target thread identifier `thread_id`. For storage request 705, the value of the target address `addr` can be 0, and the value of the target thread identifier `thread_id` can also be 0. It should be understood that the values ​​of the target address and the target thread identifier in this embodiment are merely examples.

[0079] In this embodiment of the disclosure, the first cache unit is further configured to: query the instruction queue and the data queue in response to receiving a storage request from the processor core.

[0080] For example, the first cache unit is configured to query the instruction queue to determine if instruction information corresponding to a storage request exists. Figure 7As shown, instruction queue 721 contains multiple instruction messages. For load instruction message 7211, the address `addr` value is "0x1000" and the thread identifier `thread_id` value is 1, corresponding to a load request. For load instruction message 7216, the address `addr` value is "0x6000" and the thread identifier `thread_id` value is 0, corresponding to a load request. For storage instruction message 72111, the address `addr` value is "0x0" and the thread identifier `thread_id` value is 0, corresponding to a storage request. As mentioned above, the target address `addr` value is 0, corresponding to the hexadecimal number "0x0", consistent with the address of instruction message 72111. The target thread identifier `thread_id` value is 0, consistent with the thread identifier of instruction message 72111, confirming that storage request 705 corresponds to storage instruction message 72111. Furthermore, it can be determined that there is no load instruction message corresponding to storage request 705 in instruction queue 721.

[0081] For example, the first cache unit is configured to query the data queue to determine if a load address corresponding to the load request exists. Figure 7 As shown, multiple addresses exist in data queue 722. The value of storage address 7222 is "0x6000". The value of storage address 7223 is "0x4000". The value of storage address 7224 is "0x8000". The value of storage address 7226' is "0x0". As mentioned above, the value of the target address addr can be 0, which confirms that storage address 7226' corresponding to storage request 705 exists in data queue 722.

[0082] If it is determined that there is storage instruction information corresponding to storage request 705 in instruction queue 721, no load instruction information corresponding to storage request 705 in instruction queue 721, and a storage address corresponding to storage request 705 in data queue 722, then storage request 705 can be accepted. Next, the operation corresponding to storage request 705 can be executed.

[0083] In this embodiment, the first cache unit is further configured to: update the storage address in the data queue when it is determined that there is storage instruction information corresponding to the storage request in the instruction queue, no loading instruction information related to the storage request in the instruction queue, and a storage address corresponding to the storage request in the data queue; and send the storage request to the second cache unit. For example, storage address 7226' in data queue 722 can be updated. Storage request 705 can be sent to the first-level data cache, which serves as the second cache unit, to query whether a storage address corresponding to storage request 705 exists in the first-level data cache. Through this embodiment, when there is storage instruction information corresponding to the storage request and a storage address corresponding to the storage request exists in the data queue, the storage address in the data queue is updated, write fusion is achieved, the hardware utilization of the chip can be improved, and the chip performance can be further improved.

[0084] Figure 8 This is a schematic diagram illustrating the execution of an operation corresponding to a memory access request according to another embodiment of this disclosure.

[0085] like Figure 8 As shown, the first cache unit 820 may include an instruction queue 821 and a data queue 822. A storage request 806 may include a target address `addr` and a target thread identifier `thread_id`. For storage request 806, the value of the target address `addr` can be 0, and the value of the target thread identifier `thread_id` can also be 0. It should be understood that the values ​​of the address and the thread identifier in this embodiment are merely examples.

[0086] In this embodiment of the disclosure, the first cache unit is further configured to: query the instruction queue and the data queue in response to receiving a storage request from the processor core.

[0087] For example, the first cache unit is configured to query the instruction queue to determine if instruction information corresponding to a storage request exists. Figure 8As shown, instruction queue 821 contains multiple instruction messages. For storage instruction message 82113, the address `addr` value is "0x1000" and the thread identifier `thread_id` value is 1, corresponding to a storage request. For load instruction message 82114, the address `addr` value is "0x8000" and the thread identifier `thread_id` value is 1, corresponding to a storage request. For load instruction message 82115, the address `addr` value is "0x0000" and the thread identifier `thread_id` value is 0, corresponding to a storage request. As mentioned above, the target address `addr` value is 0, corresponding to the hexadecimal number "0x0", consistent with the address of load instruction message 82115. The target thread identifier `thread_id` value is 0, consistent with the thread identifier of instruction message 82115, confirming that storage request 806 corresponds to load instruction message 82115.

[0088] For example, the first cache unit is configured to query the data queue to determine if a load address corresponding to the load request exists. Figure 8 As shown, multiple addresses exist in data queue 822. The value of storage address 8227 is "0x1000". The value of storage address 8228 is "0x8000". The value of load address 8229 is "0x0000". As mentioned above, the value of the target address addr can be 0, which confirms that load address 8229 corresponding to storage request 806 exists in data queue 822. Furthermore, it can also be determined that there is remaining storage space 82210 in data queue 822.

[0089] If it is determined that there is a load instruction information corresponding to storage request 806 in instruction queue 821, a load address corresponding to storage request 806 in data queue 821, and remaining storage space 82110 in data queue 822, then storage request 806 can be accepted. Next, the operation corresponding to storage request 806 can be executed.

[0090] In this embodiment, the first cache unit is further configured to: send the storage request to the second cache unit when it is determined that there is loading instruction information related to the storage request in the instruction queue, a loading address corresponding to the storage request exists in the data queue, and there is remaining storage space in the data queue; and update the storage address in the data queue in response to determining that the loading instruction information has been executed. For example, the storage request 806 can be sent to the first-level data cache, which serves as the second cache unit, to query whether there is a storage address corresponding to the storage request 806 in the first-level data cache. After determining that the loading instruction information 82115 has been executed, the loading address 8229 can be updated using the target address of the storage request 806, so that the loading address 8229 is converted into a storage address.

[0091] Figure 9 This is a schematic diagram illustrating the execution of an operation corresponding to a memory access request according to another embodiment of this disclosure.

[0092] like Figure 9 As shown, the first cache unit 920 may include an instruction queue 921 and a data queue 922. A storage request 907 may include a target address `addr` and a target thread identifier `thread_id`. For storage request 907, the value of the target address `addr` can be 0, and the value of the target thread identifier `thread_id` can also be 0. It should be understood that the values ​​of the address and the thread identifier in this embodiment are merely examples.

[0093] In this embodiment of the disclosure, the first cache unit is further configured to: query the instruction queue and the data queue in response to receiving a storage request from the processor core.

[0094] For example, the first cache unit is configured to query the instruction queue to determine if instruction information corresponding to a storage request exists. Figure 9 As shown, instruction queue 921 contains multiple instruction messages. For load instruction message 9211, the address `addr` value is "0x1000" and the thread identifier `thread_id` value is 1, which corresponds to a load request. For load instruction message 92117, the address `addr` value is "0x8000" and the thread identifier `thread_id` value is 1, which also corresponds to a load request. For load instruction message 92118, the address `addr` value is "0x2000" and the thread identifier `thread_id` value is 0, which also corresponds to a load request. As mentioned above, the target address `addr` value is 0, corresponding to the hexadecimal number "0x0", confirming that there is no load instruction message in instruction queue 921 corresponding to storage request 907.

[0095] For example, the first cache unit is configured to query the data queue to determine if a load address corresponding to the load request exists. Figure 9 As shown, multiple addresses exist in data queue 922. The value of load address 92211 is "0x8000". The value of load address 92212 is "0x2000". As mentioned above, the value of the target address addr can be 0, which confirms that there is no storage address in data queue 922 corresponding to storage request 907.

[0096] If it is determined that there is no load instruction information corresponding to storage request 907 in instruction queue 921 and no storage address corresponding to storage request 907 in data queue 922, storage request 907 can be accepted. Next, the operation corresponding to storage request 907 can be executed.

[0097] In this embodiment of the disclosure, the first cache unit is further configured to: send the storage request to the second cache unit when it is determined that there is no loading instruction information related to the storage request in the instruction queue and no storage address corresponding to the storage request in the data queue. For example, the storage request 907 can be sent to the first-level data cache, which serves as the second cache unit, so as to query whether there is a storage address corresponding to the storage request 907 in the first-level data cache.

[0098] It is understood that the above description uses the acceptance of a memory access request as an example to illustrate this disclosure. However, this disclosure is not limited to this; it can also reject memory access requests, as will be explained further below.

[0099] Figure 10 This is a schematic diagram illustrating the execution of an operation corresponding to a memory access request according to another embodiment of this disclosure.

[0100] like Figure 10 As shown, the first cache unit 1020 may include an instruction queue 1021 and a data queue 1022. A storage request 1008 may include a target address `addr` and a target thread identifier `thread_id`. For storage request 1008, the value of the target address `addr` can be 0, and the value of the target thread identifier `thread_id` can also be 0. It should be understood that the values ​​of the address and the thread identifier in this embodiment are merely examples.

[0101] In this embodiment of the disclosure, the first cache unit is further configured to: query the instruction queue and the data queue in response to receiving a storage request from the processor core.

[0102] For example, the first cache unit is configured to query the instruction queue to determine if instruction information corresponding to a storage request exists. Figure 10As shown, instruction queue 1021 contains multiple instruction messages. For storage instruction message 102113, the value of address `addr` is "0x1000", and the value of thread identifier `thread_id` is 1, which corresponds to a storage request. For storage instruction message 102114, the value of address `addr` is "0x8000", and the value of thread identifier `thread_id` is 1, which corresponds to a storage request. For storage instruction message 102120, the value of address `addr` is "0x6000", and the value of thread identifier `thread_id` is 0, which corresponds to a storage request. For storage instruction message 102121, the value of address `addr` is "0x0000", and the value of thread identifier `thread_id` is 0, which corresponds to a storage request. As mentioned above, the value of the target address `addr` is 0, corresponding to the hexadecimal number "0x0", which is consistent with the address of load instruction message 102121. The target thread identifier thread_id has a value of 0, which is consistent with the thread identifier of load instruction information 102121. Therefore, it can be determined that storage request 1008 corresponds to load instruction information 102121.

[0103] For example, the first cache unit is configured to query the data queue to determine if a load address corresponding to the load request exists. Figure 10 As shown, multiple addresses exist in data queue 1022. The value of storage address 102213 is "0x1000". The value of storage address 102214 is "0x8000". The value of storage address 102215 is "0x6000". The value of storage address 102216 is "0x0000". As mentioned above, the value of the target address addr can be 0, which confirms that storage address 102216, corresponding to storage request 1008, exists in data queue 1022.

[0104] If it is determined that there is a load instruction information corresponding to storage request 1008 in instruction queue 1021 and a storage address corresponding to storage request 1008 in data queue 1022, storage request 1008 may not be accepted.

[0105] In this embodiment of the disclosure, the first cache unit is further configured to: send an indication to the processor core to reject the storage request when it is determined that there is load instruction information related to the storage request in the instruction queue, there is a storage address corresponding to the storage request in the data queue, and there is no remaining storage space in the data queue. For example, an indication to reject the storage request can be sent to the processor core.

[0106] As can be understood, the data processing unit of this disclosure has been described above, and the data processing method of this disclosure will be described below.

[0107] Figure 11This is a flowchart of a data processing method according to an embodiment of the present disclosure.

[0108] like Figure 11 As shown, the method 1100 may include operations S1110 to S1130.

[0109] In operation S1110, in response to a memory access request from the processor core, it is determined whether to accept the memory access request based on the memory access request, the instruction queue of the first cache unit, and the data queue of the first cache unit.

[0110] In this embodiment of the disclosure, the instruction queue is used to store instruction information to be executed, and the data queue is used to store the load address and the storage address.

[0111] In this embodiment of the disclosure, operation S1120 can be performed if it is determined that a memory access request will be accepted.

[0112] In this embodiment of the disclosure, if it is determined that a memory access request will not be accepted, operation S1130 may be performed.

[0113] In operation S1120, the operation corresponding to the memory access request is executed.

[0114] In operation S1130, an instruction to reject the memory request is sent to the processor core.

[0115] It is understood that the data processing unit 100 described above can be used to execute method 1100. The data processing unit 100 has been described above, and will not be repeated here.

[0116] In some embodiments, the memory access request includes a load request, and the instruction information includes the load address and thread information.

[0117] In this embodiment of the disclosure, determining whether to accept a memory access request includes: if it is determined that there is no instruction information corresponding to the load request in the instruction queue and there is a load address corresponding to the load request in the data queue, then the memory access request is accepted. For example, if it is determined that the memory access request is accepted, performing the operation corresponding to the memory access request includes: loading the load address from the data queue; and writing the load address back to the processor core. It is understood that the above-described first cache unit 320 can be used to perform the relevant operations. The first cache unit 320 has been described above, and will not be repeated here.

[0118] In this embodiment, determining whether to accept a memory access request includes: if it is determined that there is corresponding instruction information in the instruction queue and a load address in the data queue corresponding to the load request, then the memory access request is accepted. If the memory access request is accepted, performing the operation corresponding to the memory access request includes: adding the load request to the instruction queue. In response to determining that the corresponding instruction information has been executed, the load address is loaded from the data queue and written back to the processor core. It is understood that the above-described first cache unit 420 can be used to perform the relevant operations. The first cache unit 420 has been described above and will not be repeated here.

[0119] In this embodiment, determining whether to accept a memory access request includes: if it is determined that there is no corresponding instruction information in the instruction queue corresponding to the load request, no load address in the data queue corresponding to the load request, and no remaining storage space in the data queue, then the memory access request is accepted. If the memory access request is accepted, performing the operation corresponding to the memory access request includes: adding the load request to the instruction queue; and sending the load request to the second cache unit. It is understood that the first cache unit 520 described above can be used to perform the relevant operations. The first cache unit 520 has been described above, and will not be repeated here.

[0120] In this embodiment, determining whether to accept a memory access request includes: if it is determined that there is no corresponding instruction information in the instruction queue, no load address in the data queue, and remaining storage space in the data queue, then the memory access request is accepted. If the memory access request is accepted, the operation corresponding to the memory access request is performed, including: adding the load request to the instruction queue; adding the load address to the data queue; and sending the load request to the second cache unit. It is understood that the aforementioned first cache unit 620 can be used to perform the relevant operations. The first cache unit 620 has been described above and will not be repeated here.

[0121] In some embodiments, the memory access request includes a storage request, and the instruction information includes the storage address and thread information.

[0122] In this embodiment, determining whether to accept a memory access request includes: if it is determined that there is instruction information corresponding to the memory access request in the instruction queue, no load instruction information related to the memory access request in the instruction queue, and a memory address corresponding to the memory access request exists in the data queue, then the memory access request is accepted. If the memory access request is accepted, performing the operation corresponding to the memory access request includes: updating the memory address in the data queue. The memory access request is then sent to the second cache unit. It is understood that the aforementioned first cache unit 720 can be used to perform the relevant operations. The first cache unit 720 has been described above, and will not be repeated here.

[0123] In this embodiment of the disclosure, determining whether to accept a memory access request includes: if it is determined that there is load instruction information related to the memory access request in the instruction queue, there is a memory address corresponding to the memory access request in the data queue, and there is no remaining memory space in the data queue, then the memory access request is not accepted. It is understood that the aforementioned first cache unit 1020 can be used to perform related operations. The first cache unit 1020 has been described above, and will not be repeated here.

[0124] In this embodiment, determining whether to accept a memory access request includes: if it is determined that there is a load instruction related to the memory access request in the instruction queue, a memory address corresponding to the memory access request in the data queue, and remaining storage space in the data queue, then the memory access request is accepted. If the memory access request is accepted, performing the operation corresponding to the memory access request includes: sending the memory access request to the second cache unit. In response to determining that the load instruction has been executed, the memory address in the data queue is updated. It is understood that the above-described first cache unit 820 can be used to perform the relevant operations. The first cache unit 820 has been described above, and will not be repeated here.

[0125] In this embodiment of the disclosure, determining whether to accept a memory access request includes: if it is determined that there is no load instruction information related to the memory access request in the instruction queue and no load address corresponding to the memory access request in the data queue, then the memory access request is accepted. If the memory access request is accepted, performing the operation corresponding to the memory access request includes: sending the memory access request to the second cache unit. It is understood that the aforementioned first cache unit 920 can be used to perform the relevant operations. The first cache unit 920 has been described above, and will not be repeated here.

[0126] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0127] According to embodiments of this disclosure, an electronic device including the data processing unit described above is provided, which will be further described below.

[0128] Figure 12 This is a schematic block diagram of an electronic device according to an embodiment of the present disclosure.

[0129] like Figure 12 As shown, the electronic device 12 may include a data processing unit 1200 and a second cache unit 1230.

[0130] In this embodiment of the disclosure, the data processing unit 1200 may be, for example, the data processing unit 100 described above.

[0131] In this embodiment of the disclosure, the second cache unit 1230 can be the first-level data cache described above.

[0132] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0133] Figure 13 A schematic block diagram of an example electronic device 1300 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0134] like Figure 13 As shown, device 1300 includes a computing unit 1301, which can perform various appropriate actions and processes according to a computer program stored in read-only memory (ROM) 1302 or a computer program loaded from storage unit 1308 into random access memory (RAM) 1303. The RAM 1303 may also store various programs and data required for the operation of device 1300. The computing unit 1301, ROM 1302, and RAM 1303 are interconnected via bus 1304. Input / output (I / O) interface 1305 is also connected to bus 1304.

[0135] Multiple components in device 1300 are connected to I / O interface 1305, including: input unit 1306, such as keyboard, mouse, etc.; output unit 1307, such as various types of monitors, speakers, etc.; storage unit 1308, such as disk, optical disk, etc.; and communication unit 1309, such as network card, modem, wireless transceiver, etc. Communication unit 1309 allows device 1300 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0136] The computing unit 1301 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1301 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1301 performs the various methods and processes described above, such as data processing methods. For example, in some embodiments, the data processing method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 1308. In some embodiments, part or all of the computer program may be loaded and / or installed on device 1300 via ROM 1302 and / or communication unit 1309. When the computer program is loaded into RAM 1303 and executed by the computing unit 1301, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the computing unit 1301 may be configured to perform data processing methods by any other suitable means (e.g., by means of firmware).

[0137] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0138] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0139] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0140] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) monitor or an LCD (liquid crystal display)) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0141] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0142] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other.

[0143] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0144] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A data processing unit, comprising: The processor core is configured to send memory access requests. as well as The first cache unit includes an instruction queue and a data queue. The instruction queue stores instructions to be executed, and the data queue stores load addresses and storage addresses. The first cache unit is configured as follows: In response to receiving a memory access request from a processor core, determine whether to accept the memory access request based on the memory access request, the instruction queue, and the data queue; If the memory access request is accepted, the operation corresponding to the memory access request is executed, and If it is determined that the memory access request will not be accepted, an instruction to reject the memory access request is sent to the processor core; The memory access request includes a load request, and the instruction information includes a load address and a thread identifier. The first cache unit is also configured as follows: If it is determined that there is no instruction information corresponding to the load request in the instruction queue and there is a load address corresponding to the load request in the data queue. Load the load address from the data queue; as well as Write the load address back to the processor core.

2. The data processing unit according to claim 1, wherein, The first cache unit is also configured as follows: If it is determined that there is corresponding instruction information in the instruction queue that corresponds to the load request and there is a load address in the data queue that corresponds to the load request, then... Add the loading request to the instruction queue; as well as In response to determining that the corresponding instruction information has been executed, the load address is loaded from the data queue and written back to the processor core.

3. The data processing unit according to claim 1, wherein, The first cache unit is also configured as follows: If it is determined that there is no corresponding instruction information in the instruction queue that corresponds to the load request, there is no load address in the data queue that corresponds to the load request, and there is no remaining storage space in the data queue. Add the load request to the instruction queue; and The loading request is sent to the second cache unit.

4. The data processing unit according to claim 1, wherein, The first cache unit is also configured as follows: If it is determined that there is no corresponding instruction information in the instruction queue that corresponds to the load request, there is no load address in the data queue that corresponds to the load request, and there is remaining storage space in the data queue. Add the loading request to the instruction queue; Add the load address to the data queue; and The loading request is sent to the second cache unit.

5. A data processing unit, comprising: The processor core is configured to send memory access requests. as well as The first cache unit includes an instruction queue and a data queue. The instruction queue stores instructions to be executed, and the data queue stores load addresses and storage addresses. The first cache unit is configured as follows: In response to receiving a memory access request from a processor core, determine whether to accept the memory access request based on the memory access request, the instruction queue, and the data queue; If the memory access request is accepted, the operation corresponding to the memory access request is executed, and If it is determined that the memory access request will not be accepted, an instruction to reject the memory access request is sent to the processor core. The memory access request includes a storage request, and the instruction information includes a storage address and a thread identifier; The first cache unit is also configured as follows: If it is determined that there is no loading instruction information related to the storage request in the instruction queue and no storage address corresponding to the storage request in the data queue, the storage request is sent to the second cache unit.

6. The data processing unit according to claim 5, wherein, The first cache unit is also configured as follows: If it is determined that there is storage instruction information corresponding to the storage request in the instruction queue, no load instruction information related to the storage request in the instruction queue, and a storage address corresponding to the storage request exists in the data queue. Update the storage address in the data queue; as well as The storage request is sent to the second cache unit.

7. The data processing unit according to claim 5, wherein, The first cache unit is also configured as follows: If it is determined that there is a load instruction related to the storage request in the instruction queue, a storage address corresponding to the storage request in the data queue, and no remaining storage space in the data queue, an indication to reject the storage request is sent to the processor core.

8. The data processing unit according to claim 5, wherein, The first cache unit is also configured as follows: If it is determined that there is a load instruction related to the storage request in the instruction queue, a load address corresponding to the storage request in the data queue, and remaining storage space in the data queue... The storage request is sent to the second cache unit; as well as In response to determining that the loading instruction information has been executed, the storage address in the data queue is updated.

9. An electronic device, comprising: The data processing unit according to any one of claims 1 to 8; as well as Second cache unit.

10. A data processing method, comprising: In response to a memory access request from a processor core, a determination is made, based on the memory access request, the instruction queue of the first cache unit, and the data queue of the first cache unit, whether to accept the memory access request, wherein the instruction queue is used to store instruction information to be executed, and the data queue is used to store load address and storage address; If the memory access request is accepted, the operation corresponding to the memory access request is executed, and If it is determined that the memory access request will not be accepted, an instruction to reject the memory access request is sent to the processor core; The memory access request includes a load request, and the instruction information includes a load address and a thread identifier. The process of determining whether to accept the memory access request includes: If it is determined that there is no instruction information corresponding to the load request in the instruction queue and there is a load address corresponding to the load request in the data queue, then the memory access request is accepted. The step of performing the operation corresponding to the memory access request when it is determined that the memory access request will be accepted includes: Load the load address from the data queue; and Write the load address back to the processor core.

11. The method according to claim 10, wherein, The process of determining whether to accept the memory access request includes: If it is determined that there is corresponding instruction information in the instruction queue that corresponds to the load request and there is a load address in the data queue that corresponds to the load request, then the memory access request is accepted. The step of performing the operation corresponding to the memory access request when it is determined that the memory access request will be accepted includes: Add the loading request to the instruction queue; and In response to determining that the corresponding instruction information has been executed, the load address is loaded from the data queue and written back to the processor core.

12. The method according to claim 10, wherein, The process of determining whether to accept the memory access request includes: If it is determined that there is no corresponding instruction information in the instruction queue that corresponds to the load request, there is no load address in the data queue that corresponds to the load request, and there is no remaining storage space in the data queue, then the memory access request is accepted. The step of performing the operation corresponding to the memory access request when it is determined that the memory access request will be accepted includes: Add the load request to the instruction queue; and The loading request is sent to the second cache unit.

13. The method according to claim 10, wherein, The process of determining whether to accept the memory access request includes: If it is determined that there is no corresponding instruction information in the instruction queue that corresponds to the load request, there is no load address in the data queue that corresponds to the load request, and there is remaining storage space in the data queue, then the memory access request is accepted. The step of performing the operation corresponding to the memory access request when it is determined that the memory access request will be accepted includes: Add the loading request to the instruction queue; Add the load address to the data queue; and The loading request is sent to the second cache unit.

14. A data processing method, comprising: In response to a memory access request from a processor core, a determination is made, based on the memory access request, the instruction queue of the first cache unit, and the data queue of the first cache unit, whether to accept the memory access request, wherein the instruction queue is used to store instruction information to be executed, and the data queue is used to store load address and storage address; If the memory access request is accepted, the operation corresponding to the memory access request is executed, and If it is determined that the memory access request will not be accepted, an instruction to reject the memory access request is sent to the processor core; The memory access request includes a storage request, and the instruction information includes a storage address and a thread identifier; The process of determining whether to accept the memory access request includes: If it is determined that there is no load instruction information related to the storage request in the instruction queue and no load address corresponding to the storage request in the data queue, the memory access request is accepted. The step of performing the operation corresponding to the memory access request when it is determined that the memory access request will be accepted includes: The storage request is sent to the second cache unit.

15. The method according to claim 14, wherein, The process of determining whether to accept the memory access request includes: If it is determined that there is instruction information corresponding to the storage request in the instruction queue, no load instruction information related to the storage request in the instruction queue, and a storage address corresponding to the storage request exists in the data queue, then the memory access request is accepted. The step of performing the operation corresponding to the memory access request when it is determined that the memory access request will be accepted includes: Update the storage address in the data queue; and The storage request is sent to the second cache unit.

16. The method of claim 14, wherein, The process of determining whether to accept the memory access request includes: If it is determined that there is a load instruction information related to the storage request in the instruction queue, a storage address corresponding to the storage request in the data queue, and no remaining storage space in the data queue, then the memory access request will not be accepted.

17. The method of claim 14, wherein, The process of determining whether to accept the memory access request includes: If it is determined that there is a load instruction information related to the storage request in the instruction queue, a storage address corresponding to the storage request in the data queue, and remaining storage space in the data queue, then the memory access request is accepted. The step of performing the operation corresponding to the memory access request when it is determined that the memory access request will be accepted includes: Send the storage request to the second cache unit; and In response to determining that the loading instruction information has been executed, the storage address in the data queue is updated.

18. An electronic device comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 10 to 17.

19. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 10 to 17.

20. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 10 to 17.

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