A data acceleration computing method, device, apparatus and storage medium

Abstract

This application discloses a data acceleration computing method, apparatus, device, and storage medium, relating to the field of FPGA applications. The method includes: determining whether preset data acceleration computing conditions are met; if so, using a first preset global memory management module to determine memory status information to obtain the data to be processed sent by the host based on the memory status information, and migrating the data to be processed to the FPGA global memory; using a first computing kernel and a second preset global memory management module to read the data to be processed and perform data computation, and using a preset local memory management module to cache the current kernel computation result in the FPGA local memory; using a second computing kernel and the current kernel computation result to perform data computation to obtain a target data result, and returning the target data result to the FPGA global memory so that the host can read the target data result. This reduces the number of data migrations and improves the acceleration effect of data acceleration computing.

Description

Technical Field

[0001] This invention relates to the field of FPGA applications, and in particular to a data acceleration computing method, apparatus, device, and storage medium. Background Technology

[0002] Heterogeneous acceleration platforms are widely used in graphics, algorithm, and other acceleration scenarios. Currently, mainstream heterogeneous acceleration platforms utilize PCIe (Peripheral Component Interconnect Express) DMA (Direct Memory Access) to handle data transfer between the host and the FPGA accelerator card. Data transfer within the FPGA (Field Programmable Gate Array) is based on the AXI (Advanced eXtensible Interface) bus. When a heterogeneous acceleration platform accelerates a specific algorithm, frequent data migration occurs between the host memory and the global memory of the FPGA accelerator card. This frequent data migration between different memory locations incurs additional time overhead, reduces data transfer efficiency, and results in poor acceleration performance. Therefore, improving the acceleration effect of data acceleration computation is an urgent problem to be solved. Summary of the Invention

[0003] In view of this, the purpose of this invention is to provide a data acceleration computing method, apparatus, device, and storage medium that can reduce the number of data migrations between the host and the FPGA global memory, and further reduce the number of data migrations to the FPGA global memory by utilizing local memory, thereby reducing the time overhead caused by data migration, improving the efficiency of data transmission and migration, and thus improving the acceleration effect of data acceleration computing. The specific solution is as follows:

[0004] In a first aspect, this application provides a data acceleration computing method applied to an FPGA accelerator card, comprising:

[0005] Determine whether the preset data acceleration calculation conditions are met;

[0006] If the preset data acceleration calculation conditions are met, the first preset global memory management module is used to determine the memory status information, so as to obtain the data to be processed sent by the Host based on the memory status information, and migrate the data to be processed to the FPGA global memory.

[0007] The first computing kernel and the second preset global memory management module are used to read the data to be processed from the FPGA global memory for data calculation, and the preset local memory management module is used to cache the current kernel calculation result to the FPGA local memory.

[0008] The second computing kernel and the current kernel's computing results are used to perform data calculations to obtain the target data result, and the target data result is returned to the FPGA global memory so that the host can read the target data result from the FPGA global memory.

[0009] Optionally, determining whether the preset data acceleration calculation conditions are met includes:

[0010] Determine whether a Host request, determined based on the initial computation task, has been received from the Host.

[0011] If so, it is determined that the current conditions for accelerated data calculation are met.

[0012] Optionally, determining the memory status information using the first preset global memory management module includes:

[0013] The current address space information is determined using the first address mapping management unit in the first preset global memory management module;

[0014] The memory status information of the FPGA accelerator card is determined based on the current address space information and using the memory dynamic management unit in the first preset global memory management module.

[0015] Optionally, determining the memory status information using the first preset global memory management module includes:

[0016] The first preset global memory management module is used to obtain the current available memory and the maximum number of bytes of data in a single transaction of the FPGA acceleration card, so as to obtain memory status information;

[0017] Accordingly, obtaining the data to be processed sent by the Host based on the memory state information includes:

[0018] Obtain the data to be processed sent by the Host based on the memory status information; the data to be processed includes a data structure determined based on the memory status information.

[0019] Optionally, the step of using the first computing kernel and the second preset global memory management module to read the data to be processed from the FPGA global memory for data computation includes:

[0020] The global memory access path table is determined using the second address mapping management unit of the second preset global memory management module;

[0021] The data to be processed is read from the FPGA global memory using the first computing kernel and according to the global memory access path table for data computation.

[0022] Optionally, the step of using the second computing kernel and the current kernel's computing results to perform data computation to obtain the target data result includes:

[0023] The data is calculated using the second computing kernel and the calculation result of the current kernel to obtain the current calculation result to be judged;

[0024] Determine whether the current calculation result to be determined meets the preset local memory access conditions;

[0025] If the conditions are met, the current calculation result to be judged is cached in the FPGA local memory using the preset local memory management module, and the current kernel to be judged is determined. Data calculation is performed using the current kernel to be judged and the current calculation result to be judged, and the calculated result is determined as the new current calculation result to be judged. Then, the process jumps to the step of judging whether the current calculation result to be judged meets the preset local memory call conditions, until the current calculation result to be judged does not meet the preset local memory call conditions.

[0026] If the conditions are not met, the current calculation result to be judged will be determined as the target data result.

[0027] Optionally, before caching the current kernel calculation result to the FPGA local memory using the preset local memory management module, the method further includes:

[0028] Determine whether the current kernel calculation result satisfies the preset local memory call condition;

[0029] If the conditions are met, the step of caching the current kernel calculation result to the FPGA local memory using the preset local memory management module is triggered.

[0030] If the conditions are not met, the current kernel calculation result is determined as the target data result, and the step of returning the target data result to the FPGA global memory is triggered.

[0031] Secondly, this application provides a data acceleration computing device applied to an FPGA accelerator card, comprising:

[0032] The accelerated calculation condition judgment module is used to determine whether the preset data accelerated calculation conditions are met.

[0033] The pending data acquisition module is used to determine memory status information using the first preset global memory management module if the current preset data acceleration calculation conditions are met, so as to obtain the pending data sent by the Host based on the memory status information and migrate the pending data to the FPGA global memory.

[0034] The first data calculation module is used to read the data to be processed from the FPGA global memory using the first calculation kernel and the second preset global memory management module, and to cache the current kernel calculation result to the FPGA local memory using the preset local memory management module.

[0035] The second data calculation module is used to perform data calculations using the second calculation kernel and the calculation results of the current kernel to obtain the target data result, and return the target data result to the FPGA global memory so that the host can read the target data result from the FPGA global memory.

[0036] Thirdly, this application provides an electronic device, comprising:

[0037] Memory, used to store computer programs;

[0038] A processor for executing the computer program to implement the aforementioned data acceleration computing method.

[0039] Fourthly, this application provides a computer-readable storage medium for storing a computer program, which, when executed by a processor, implements the aforementioned data acceleration calculation method.

[0040] In this application, it is determined whether the current conditions for accelerated data computation are met. If the conditions are met, the first preset global memory management module is used to determine memory status information to obtain the data to be processed sent by the host based on the memory status information, and the data to be processed is migrated to the FPGA global memory. The first computing kernel and the second preset global memory management module are used to read the data to be processed from the FPGA global memory for data computation, and the preset local memory management module is used to cache the current kernel computation result in the FPGA local memory. The second computing kernel and the current kernel computation result are used to perform data computation to obtain the target data result, and the target data result is returned to the FPGA global memory so that the host can read the target data result from the FPGA global memory. Through the above scheme, this application can migrate the data to be processed sent by the host to the FPGA global memory, use the second preset global memory management module to read the data and perform computation, and use the preset local memory management module to call the FPGA local memory to assist in computation until the target data result is obtained. This reduces the number of data migrations between the host and the FPGA global memory, and avoids migrating data to the FPGA global memory after each calculation. By utilizing local memory to reduce the number of data migrations to the FPGA global memory, the time overhead caused by data migration is reduced, and the efficiency of data transmission and migration is improved, thereby enhancing the acceleration effect of data acceleration computation. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0042] Figure 1 A flowchart of a data acceleration computing method provided in this application;

[0043] Figure 2 A schematic diagram of a heterogeneous acceleration platform provided in this application;

[0044] Figure 3 A schematic diagram of a data acceleration computing system framework provided in this application;

[0045] Figure 4 A schematic diagram of a data acceleration computing device provided in this application;

[0046] Figure 5 This application provides a structural diagram of an electronic device. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] Currently, when heterogeneous acceleration platforms perform accelerated computation, data frequently migrates between the host and the global memory of the FPGA accelerator card. This frequent data migration between different memory locations incurs additional time overhead, reduces data transfer efficiency, and consequently leads to poor acceleration performance. Therefore, this application discloses a data acceleration computation method that can reduce the number of data migrations between the host and the FPGA global memory. Furthermore, it utilizes local memory to further reduce the number of data migrations within the FPGA global memory, thereby reducing the time overhead caused by data migration, improving data transfer efficiency, and ultimately enhancing the acceleration performance of data acceleration computation.

[0049] See Figure 1 As shown, this embodiment of the invention discloses a data acceleration computing method applied to an FPGA accelerator card, comprising:

[0050] Step S11: Determine whether the preset data acceleration calculation conditions are met.

[0051] In this embodiment, it should be noted that determining whether the preset data acceleration calculation conditions are met can specifically include: determining whether a Host request determined based on the initial calculation task has been received from the Host terminal; if so, it is determined that the preset data acceleration calculation conditions are met. That is, after the user issues the initial calculation task, the Host terminal will send a Host request to the FPGA acceleration card according to the initial calculation task. When the FPGA acceleration card receives the Host request, it determines that the preset data acceleration calculation conditions are met and executes step S12.

[0052] Step S12: If the preset data acceleration calculation conditions are met, the first preset global memory management module is used to determine the memory status information, so as to obtain the data to be processed sent by the Host based on the memory status information, and the data to be processed is migrated to the FPGA global memory.

[0053] In this embodiment, it should be noted that the step of determining memory status information using the first preset global memory management module may specifically include: determining the current address space information using the first address mapping management unit in the first preset global memory management module; and determining the memory status information of the FPGA accelerator card based on the current address space information and using the memory dynamic management unit in the first preset global memory management module.

[0054] It is understood that determining memory status information using the first preset global memory management module can specifically include: using the first preset global memory management module to obtain the current available memory and the maximum number of bytes of data per transaction of the FPGA accelerator card, in order to obtain memory status information. In this way, the host can determine the corresponding data structure based on the memory status information, and then use the aforementioned data structure to send the determined data to be processed to the FPGA accelerator card. The FPGA accelerator card then migrates the data to be processed to the FPGA global memory.

[0055] Step S13: Use the first computing kernel and the second preset global memory management module to read the data to be processed from the FPGA global memory for data calculation, and use the preset local memory management module to cache the current kernel calculation result to the FPGA local memory.

[0056] In this embodiment, it should be noted that the step of using the first computing kernel and the second preset global memory management module to read the data to be processed from the FPGA global memory for data calculation may specifically include: using the second address mapping management unit of the second preset global memory management module to determine the global memory access path table; and using the first computing kernel and the global memory access path table to read the data to be processed from the FPGA global memory for data calculation.

[0057] Step S14: Perform data calculation using the second computing kernel and the current kernel calculation result to obtain the target data result, and return the target data result to the FPGA global memory so that the Host can read the target data result from the FPGA global memory.

[0058] In this embodiment, it should be noted that the step of using the second computing kernel and the current kernel's calculation result to perform data calculation to obtain the target data result may specifically include: using the second computing kernel and the current kernel's calculation result to perform data calculation to obtain the current calculation result to be judged; determining whether the current calculation result to be judged meets the preset local memory call conditions; if it does, then using the preset local memory management module to cache the current calculation result to be judged in the FPGA local memory and determine the current computing kernel; using the current computing kernel to be judged and the current calculation result to perform data calculation, determining the calculated result as the new current calculation result to be judged, and jumping to the step of determining whether the current calculation result to be judged meets the preset local memory call conditions, until the current calculation result to be judged does not meet the preset local memory call conditions; if it does not meet the conditions, then determining the current calculation result to be judged as the target data result.

[0059] It is understandable that before caching the current kernel calculation result to the FPGA local memory using the preset local memory management module, the process may further include: determining whether the current kernel calculation result meets the preset local memory access conditions; if it does, then triggering the step of caching the current kernel calculation result to the FPGA local memory using the preset local memory management module; if it does not, then determining the current kernel calculation result as the target data result and triggering the step of returning the target data result to the FPGA global memory. That is, if the current calculation result meets the preset local memory access conditions, then the initial calculation task is performed using local memory; if the current calculation result does not meet the preset local memory access conditions, then the current calculation result is considered the target data result, and the target data result can be directly returned to the FPGA global memory for the host to read. This improves flexibility and avoids resource waste.

[0060] In this embodiment, it is determined whether the current conditions for accelerated data computation are met. If the conditions are met, the first preset global memory management module determines the memory status information to obtain the data to be processed sent by the host based on the memory status information, and migrates the data to be processed to the FPGA global memory. The first computing kernel and the second preset global memory management module read the data to be processed from the FPGA global memory for data computation, and the preset local memory management module caches the current kernel computation result in the FPGA local memory. The second computing kernel and the current kernel computation result are used to perform data computation to obtain the target data result, and the target data result is returned to the FPGA global memory so that the host can read the target data result from the FPGA global memory. Through the above scheme, this application can migrate the data to be processed sent by the host to the FPGA global memory, use the second preset global memory management module to read the data and perform computation, and use the preset local memory management module to call the FPGA local memory to assist in computation until the target data result is obtained. This reduces the number of data migrations between the host and the FPGA global memory, and avoids migrating data to the FPGA global memory after each calculation. By utilizing local memory to reduce the number of data migrations to the FPGA global memory, the time overhead caused by data migration is reduced, and the efficiency of data transmission and migration is improved, thereby enhancing the acceleration effect of data acceleration computation.

[0061] The following is combined with Figure 2 and Figure 3 This application describes the specific implementation process of a data acceleration computing method disclosed in this application.

[0062] like Figure 2 and Figure 3 As shown, Figure 2 This is a schematic diagram of a heterogeneous acceleration platform disclosed in this application. Figure 3This is a schematic diagram of a data acceleration computing system framework disclosed in this application. It is understood that this application, based on the OpenCL programming framework, PCIeDMA, and AXI bus technology, utilizes the programmable characteristics of an FPGA to construct a first preset global memory management module, a second preset global memory management module, and a preset local memory management module. The first preset global memory management module includes an H2C (Host to Card) global memory management module, the second preset global memory management module includes a C2C (Card to Card) global memory management module, and the preset local memory management module includes a C2C (Card to Card) local memory management module. When the host receives the acceleration task, it generates a corresponding host instruction and sends it to the FPGA acceleration card. The global memory dynamic management unit in the first preset global memory management module within the FPGA accelerate card sends the host instruction to the first address mapping management unit. The first address mapping management unit determines the current address space information and sends it to the global memory dynamic management unit. The global memory dynamic management unit calculates the currently available memory resources and allocates them reasonably to avoid related data being stored across global memory. It then determines the memory status information and notifies the host to query and obtain the memory status information of the FPGA acceleration card through the interrupt management unit. The memory status information includes the resource status of the FPGA global memory and the maximum burst bytes of a single data transmission. Based on the memory status information, the host migrates the data to be processed from the HostMemory to the FPGA global memory through the first bus matrix unit using a suitable data structure.

[0063] After the data to be processed is migrated to the FPGA global memory, the second address mapping management unit is activated. Different algorithm kernels deployed on the FPGA accelerator card access the FPGA global memory in parallel through the second bus matrix unit via the global memory access path table determined by the second address mapping management unit. The data to be processed is read and the result data generated by the calculation kernel after execution is returned to the FPGA global memory.

[0064] When intermediate calculation results are interrelated between kernel algorithm modules—that is, the current kernel calculation result is not the final calculation result required by the user (e.g., when calculating the population of a place five years from now based on the annual population growth rate, the results obtained from the first four calculations are all intermediate calculation results)—directly putting the intermediate calculation results back into the FPGA global memory would result in unnecessary memory waste and bus occupation, thereby reducing the efficiency of global memory access. Therefore, the intermediate calculation result can be determined as the current calculation result to be judged. If the current calculation result to be judged meets the preset local memory call conditions, the serial address management unit in the preset local memory management module is activated to obtain the FPGA local memory access path table. Then, the current calculation result to be judged is passed to the next-level kernel through the serial bus unit to perform data calculation using the current kernel to be calculated and the current calculation result to be judged. This process continues until the final target data result is generated and stored in the FPGA global memory. Finally, the host is notified to read the target data result from the FPGA global memory, completing this acceleration task.

[0065] See Figure 4 As shown, this application provides a data acceleration computing device applied to an FPGA accelerator card, comprising:

[0066] The accelerated calculation condition judgment module 11 is used to determine whether the preset data accelerated calculation conditions are met.

[0067] The pending data acquisition module 12 is used to determine the memory status information using the first preset global memory management module if the current preset data acceleration calculation conditions are met, so as to obtain the pending data sent by the Host based on the memory status information and migrate the pending data to the FPGA global memory.

[0068] The first data calculation module 13 is used to read the data to be processed from the FPGA global memory using the first calculation kernel and the second preset global memory management module, and to cache the current kernel calculation result obtained by the calculation to the FPGA local memory using the preset local memory management module.

[0069] The second data calculation module 14 is used to perform data calculations using the second calculation kernel and the calculation results of the current kernel to obtain the target data result, and return the target data result to the FPGA global memory so that the Host can read the target data result from the FPGA global memory.

[0070] In this application, it is determined whether the current conditions for accelerated data computation are met. If the conditions are met, the first preset global memory management module is used to determine memory status information to obtain the data to be processed sent by the host based on the memory status information, and the data to be processed is migrated to the FPGA global memory. The first computing kernel and the second preset global memory management module are used to read the data to be processed from the FPGA global memory for data computation, and the preset local memory management module is used to cache the current kernel computation result in the FPGA local memory. The second computing kernel and the current kernel computation result are used to perform data computation to obtain the target data result, and the target data result is returned to the FPGA global memory so that the host can read the target data result from the FPGA global memory. Through the above scheme, this application can migrate the data to be processed sent by the host to the FPGA global memory, use the second preset global memory management module to read the data and perform computation, and use the preset local memory management module to call the FPGA local memory to assist in computation until the target data result is obtained. This reduces the number of data migrations between the host and the FPGA global memory, and avoids migrating data to the FPGA global memory after each calculation. By utilizing local memory to reduce the number of data migrations to the FPGA global memory, the time overhead caused by data migration is reduced, and the efficiency of data transmission and migration is improved, thereby enhancing the acceleration effect of data acceleration computation.

[0071] In some specific embodiments, the accelerated computing condition judgment module 11 may specifically include:

[0072] The request receiving unit is used to determine whether a Host request, determined based on the initial computation task, has been received from the Host.

[0073] The result determination unit is used to determine whether the preset data acceleration calculation conditions are met if so.

[0074] In some specific embodiments, the data acquisition module 12 may specifically include:

[0075] The address information determination unit is used to determine the current address space information using the first address mapping management unit in the first preset global memory management module;

[0076] The status information determination unit is used to determine the memory status information of the FPGA accelerator card based on the current address space information and by utilizing the memory dynamic management unit in the first preset global memory management module.

[0077] In some specific embodiments, the data acquisition module 12 may specifically include:

[0078] The available memory acquisition unit is used to obtain the current available memory and the maximum number of bytes of data per transaction of the FPGA acceleration card using the first preset global memory management module, so as to obtain memory status information.

[0079] In some specific embodiments, the first data calculation module 13 may specifically include:

[0080] The access path table determination unit is used to determine the global memory access path table using the second address mapping management unit of the second preset global memory management module;

[0081] A global memory data reading unit is used to read the data to be processed from the FPGA global memory using the first computing kernel and according to the global memory access path table for data calculation.

[0082] In some specific embodiments, the second data calculation module 14 may specifically include:

[0083] The unit for obtaining the calculation result to be judged is used to perform data calculation using the second calculation kernel and the calculation result of the current kernel to obtain the current calculation result to be judged.

[0084] The calculation result judgment unit is used to determine whether the current calculation result to be judged meets the preset local memory call conditions;

[0085] The local memory computation execution unit is configured to, if the conditions are met, cache the current computation result to be judged in the FPGA local memory using the preset local memory management module, and determine the current kernel to be calculated; perform data computation using the current kernel to be calculated and the current computation result to be judged, determine the calculated result as the new current computation result to be judged, and jump to the step of judging whether the current computation result to be judged meets the preset local memory call conditions, until the current computation result to be judged does not meet the preset local memory call conditions;

[0086] The target data result determination unit is used to determine the current calculation result to be judged as the target data result if the condition is not met.

[0087] In some specific embodiments, the data acceleration computing device may further include:

[0088] The local memory call condition judgment module is used to determine whether the current kernel calculation result meets the preset local memory call condition;

[0089] The first step triggering module is used to trigger the step of caching the current kernel calculation result calculated by the preset local memory management module to the FPGA local memory if the conditions are met.

[0090] The second step triggering module is used to determine the current kernel calculation result as the target data result if the condition is not met, and to trigger the step of returning the target data result to the FPGA global memory.

[0091] Furthermore, embodiments of this application also disclose an electronic device, Figure 5 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application.

[0092] Figure 5 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of this application. Specifically, the electronic device 20 may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the data acceleration computing method disclosed in any of the foregoing embodiments. Furthermore, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0093] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0094] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0095] The operating system 221 is used to manage and control the various hardware devices on the electronic device 20 and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including computer programs capable of performing the data acceleration computing method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, the computer program 222 may further include computer programs capable of performing other specific tasks.

[0096] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned data acceleration computing method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0097] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0098] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0099] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0100] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0101] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A data acceleration computing method, characterized in that, Applications in FPGA accelerator cards, including: Determine whether the preset data acceleration calculation conditions are met; If the preset data acceleration calculation conditions are met, the first preset global memory management module is used to determine the memory status information, so as to obtain the data to be processed sent by the Host based on the memory status information, and migrate the data to be processed to the FPGA global memory. The first computing kernel and the second preset global memory management module are used to read the data to be processed from the FPGA global memory for data calculation, and the preset local memory management module is used to cache the current kernel calculation result to the FPGA local memory. The second computing kernel and the current kernel's computing results are used to perform data calculations to obtain the target data result, and the target data result is returned to the FPGA global memory so that the host can read the target data result from the FPGA global memory; The step of determining memory status information using the first preset global memory management module includes: The current address space information is determined using the first address mapping management unit in the first preset global memory management module; the memory status information of the FPGA acceleration card is determined based on the current address space information and the memory dynamic management unit in the first preset global memory management module. Specifically, this includes: using the first preset global memory management module to obtain the current available memory and the maximum number of bytes of data per transaction of the FPGA acceleration card, so as to obtain memory status information; The step of using a first computing kernel and a second preset global memory management module to read the data to be processed from the FPGA global memory for data computation includes: The second address mapping management unit of the second preset global memory management module determines the global memory access path table; the first computing kernel reads the data to be processed from the FPGA global memory according to the global memory access path table and performs data calculation; The step of using the second computing kernel and the computing results of the current kernel to perform data calculations to obtain the target data result includes: The data is calculated using the second computing kernel and the calculation result of the current kernel to obtain the current calculation result to be judged; Determine whether the current calculation result to be determined meets the preset local memory access conditions; If the conditions are met, the current calculation result to be judged is cached in the FPGA local memory using the preset local memory management module, and the current kernel to be judged is determined. Data calculation is performed using the current kernel to be judged and the current calculation result to be judged, and the calculated result is determined as the new current calculation result to be judged. Then, the process jumps to the step of judging whether the current calculation result to be judged meets the preset local memory call conditions, until the current calculation result to be judged does not meet the preset local memory call conditions. If the conditions are not met, the current calculation result to be judged will be determined as the target data result.

2. The data acceleration computing method according to claim 1, characterized in that, The determination of whether the preset data acceleration calculation conditions are met includes: Determine whether a Host request, determined based on the initial computation task, has been received from the Host. If so, it is determined that the current conditions for accelerated data calculation are met.

3. The data acceleration computing method according to claim 1, characterized in that, The step of obtaining the data to be processed sent by the host based on the memory state information includes: Obtain the data to be processed sent by the Host based on the memory status information; the data to be processed includes a data structure determined based on the memory status information.

4. The data acceleration computing method according to claim 1, characterized in that, Before caching the current kernel calculation result to the FPGA local memory using the preset local memory management module, the method further includes: Determine whether the current kernel calculation result satisfies the preset local memory call condition; If the conditions are met, the step of caching the current kernel calculation result to the FPGA local memory using the preset local memory management module is triggered. If the conditions are not met, the current kernel calculation result is determined as the target data result, and the step of returning the target data result to the FPGA global memory is triggered.

5. A data acceleration computing device, characterized in that, Applications in FPGA accelerator cards, including: The accelerated calculation condition judgment module is used to determine whether the preset data accelerated calculation conditions are met. The pending data acquisition module is used to determine memory status information using the first preset global memory management module if the current preset data acceleration calculation conditions are met, so as to obtain the pending data sent by the Host based on the memory status information and migrate the pending data to the FPGA global memory. The first data calculation module is used to read the data to be processed from the FPGA global memory using the first calculation kernel and the second preset global memory management module, and to cache the current kernel calculation result to the FPGA local memory using the preset local memory management module. The second data calculation module is used to perform data calculations using the second calculation kernel and the calculation results of the current kernel to obtain the target data result, and return the target data result to the FPGA global memory so that the Host can read the target data result from the FPGA global memory; The data acquisition module includes: The address information determination unit is used to determine the current address space information using the first address mapping management unit in the first preset global memory management module; the status information determination unit is used to determine the memory status information of the FPGA acceleration card based on the current address space information and using the memory dynamic management unit in the first preset global memory management module. The data acquisition module is specifically used to: obtain the current available memory and the maximum number of bytes of data per transaction of the FPGA acceleration card using the first preset global memory management module, so as to obtain memory status information; The first data calculation module includes: The access path table determination unit is used to determine the global memory access path table using the second address mapping management unit of the second preset global memory management module; the global memory data reading unit is used to read the data to be processed from the FPGA global memory using the first computing kernel and according to the global memory access path table for data calculation. The second data calculation module includes: The unit for obtaining the calculation result to be judged is used to perform data calculation using the second calculation kernel and the calculation result of the current kernel to obtain the current calculation result to be judged. The calculation result judgment unit is used to determine whether the current calculation result to be judged meets the preset local memory call conditions; The local memory computation execution unit is configured to, if the conditions are met, cache the current computation result to be judged in the FPGA local memory using the preset local memory management module, and determine the current kernel to be calculated; perform data computation using the current kernel to be calculated and the current computation result to be judged, determine the calculated result as the new current computation result to be judged, and jump to the step of judging whether the current computation result to be judged meets the preset local memory call conditions, until the current computation result to be judged does not meet the preset local memory call conditions; The target data result determination unit is used to determine the current calculation result to be judged as the target data result if the condition is not met.

6. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the data acceleration computing method as described in any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, Used to store a computer program, which, when executed by a processor, implements the data acceleration computing method as described in any one of claims 1 to 4.

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