电路仿真方法及设备
By simulating the parameters of the power bus and switches, the problem of evaluating the power bus performance in high-clock-frequency and small-area memory chips was solved, ensuring that the power bus meets the performance requirements of the memory chip and improving the stability and efficiency of the circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-02-27
- Publication Date
- 2026-07-17
AI Technical Summary
Existing technologies make it difficult to accurately assess the performance of power buses in high-clock-frequency and small-area memory chips, resulting in power buses failing to meet the performance requirements of memory chips.
By acquiring the parameters of the power bus, the device parameters of the switches, and the device parameters of the load, simulation is performed using netlists and standard parasitic parameter format files to evaluate whether the performance of the power bus meets the requirements of the circuit to be simulated. Based on the simulation results, the width of the power bus, the number of switches, or the distribution of capacitors are adjusted to meet the performance requirements.
This enables accurate evaluation of the power bus performance, ensuring it meets the performance requirements of the memory chip and improving circuit stability and efficiency.
Smart Images
Figure CN116227410B_ABST