Circuit simulation method and apparatus

Abstract

This disclosure provides a circuit simulation method and apparatus, relating to the field of semiconductor technology, applied to a circuit to be simulated. The circuit to be simulated includes a power bus, on which a power circuit is connected. The power circuit provides internal power to multiple first nodes of the power bus based on an external power supply. The method includes: obtaining a netlist and SPF file corresponding to the circuit to be simulated from a design database of the circuit to be simulated. The SPF file includes parameters corresponding to the power bus, and the netlist includes input voltage information at the multiple first nodes. Simulation is performed on the circuit to be simulated based on the netlist and SPF file. Based on the simulation results of the circuit to be simulated, it is determined whether the performance of the power bus meets the performance requirements of the circuit to be simulated. This disclosure can accurately evaluate the performance of the power bus to ensure that the power bus meets the performance requirements of the circuit to be simulated.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a circuit simulation method and apparatus. Background Technology

[0002] The design process for integrated circuits typically includes circuit design, pre-simulation, layout design, and post-simulation. Post-simulation refers to performing simulations after the layout design is completed, taking into account the circuit's parasitic parameters and the interconnections between various circuit units. The simulation results are then used to analyze the circuit to ensure it meets design requirements.

[0003] Currently, as memory chips become increasingly faster and smaller in size, accurately evaluating the performance of the power bus to ensure it meets the performance requirements of the memory chips is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] This disclosure provides a circuit simulation method and apparatus that can accurately evaluate the performance of a power bus, enabling the power bus to meet the performance requirements of the circuit to be simulated.

[0005] In a first aspect, embodiments of this disclosure provide a circuit simulation method applied to a circuit to be simulated, the circuit including a power bus, a power circuit connected to the power bus, the power circuit being used to provide internal power to a plurality of first nodes of the power bus according to an external power supply; the method includes:

[0006] Based on the design database of the circuit to be simulated, obtain the netlist and standard parasitic parameter format file corresponding to the circuit to be simulated. The standard parasitic parameter format file includes the parameters corresponding to the power bus. The netlist includes the input voltage information at the plurality of first nodes.

[0007] The circuit to be simulated is simulated based on the netlist and the standard parasitic parameter format file.

[0008] Based on the simulation results of the circuit to be simulated, determine whether the performance of the power bus meets the performance requirements of the circuit to be simulated.

[0009] In some feasible implementations, the parameters corresponding to the power bus include the power bus's own resistance and / or parasitic capacitance.

[0010] In some feasible implementations, the circuit to be simulated also includes a capacitor connected to the power bus;

[0011] The standard parasitic parameter format file also includes parameter information for the capacitor.

[0012] In some feasible implementations, the circuit to be simulated also includes at least one load connected to the power bus;

[0013] The standard parasitic parameter format file also includes device parameters for all the loads.

[0014] In some feasible implementations, the device parameters of the load include the resistance and capacitance of the devices in the load.

[0015] In some feasible implementations, determining whether the performance of the power bus meets the performance requirements of the circuit to be simulated based on the simulation results of the circuit to be simulated includes:

[0016] Based on the simulation results of the circuit to be simulated, determine the voltage value at the second node where the load and the power bus are connected;

[0017] Based on the voltage value, determine whether the performance of the power bus meets the performance requirements of the circuit to be simulated.

[0018] In some feasible implementations, determining whether the performance of the power bus meets the performance requirements of the circuit to be simulated based on the voltage value includes:

[0019] Based on the voltage value, determine whether the width of the power bus in the layout meets the performance requirements of the circuit to be simulated.

[0020] In some feasible implementations, determining whether the performance of the power bus meets the performance requirements of the circuit to be simulated based on the voltage value includes:

[0021] Based on the voltage value, determine whether the number of capacitors connected to the power bus meets the performance requirements of the circuit to be simulated.

[0022] In some feasible implementations, determining whether the performance of the power bus meets the performance requirements of the circuit to be simulated based on the voltage value includes:

[0023] Based on the impact of the voltage value change on the signal timing of the circuit to be simulated, the voltage threshold at the first node where the load and the power bus are connected is determined.

[0024] Based on the voltage value and the voltage threshold, determine whether the performance of the power bus meets the performance requirements of the circuit to be simulated.

[0025] In some feasible implementations, it also includes:

[0026] If the performance of the power bus does not meet the performance requirements of the circuit to be simulated, then the width of the power bus in the layout is increased.

[0027] In some feasible implementations, it also includes:

[0028] If the performance of the power bus does not meet the performance requirements of the circuit to be simulated, then increase the number of capacitors connected to the power bus.

[0029] In some feasible implementations, it also includes:

[0030] If the performance of the power bus does not meet the performance requirements of the circuit to be simulated, then adjust the capacitance value of the capacitor or adjust the distribution position of the capacitor.

[0031] Secondly, embodiments of this disclosure provide a circuit simulation apparatus applied to a circuit to be simulated, the circuit to be simulated including a power bus, a power supply circuit connected to the power bus, the power supply circuit being used to provide internal power to a plurality of first nodes of the power bus according to an external power supply; the apparatus includes:

[0032] The acquisition module is used to acquire the netlist and standard parasitic parameter format file corresponding to the circuit to be simulated based on the design database of the circuit to be simulated. The standard parasitic parameter format file includes the parameters corresponding to the power bus. The netlist includes the input voltage information at the plurality of first nodes.

[0033] The simulation module is used to simulate the circuit to be simulated based on the netlist and the standard parasitic parameter format file.

[0034] The processing module is used to determine whether the performance of the power bus meets the performance requirements of the circuit to be simulated based on the simulation results of the circuit to be simulated.

[0035] Thirdly, embodiments of this disclosure provide an electronic device, including: at least one processor and a memory;

[0036] The memory stores computer-executed instructions;

[0037] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the circuit simulation method as provided in the first aspect.

[0038] Fourthly, embodiments of this disclosure provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a computer, implement the circuit simulation method provided in the first aspect.

[0039] The circuit simulation method and apparatus provided in this disclosure, during post-simulation, obtain the netlist and standard parasitic parameter format file corresponding to the circuit to be simulated based on the design database of the circuit to be simulated. The standard parasitic parameter format file includes parameters corresponding to the power bus, and the netlist includes input voltage information at the multiple first nodes. Based on the netlist and SPF file, the circuit to be simulated is simulated, which makes the simulation process closer to the actual working condition of the circuit to be simulated. Furthermore, based on the simulation results, the performance of the power bus can be accurately evaluated, so that the power bus can meet the performance requirements of the circuit to be simulated. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of a circuit to be simulated provided in an embodiment of this disclosure. Figure 1 ;

[0041] Figure 2 This is a flowchart illustrating the steps of a circuit simulation method provided in an embodiment of this disclosure;

[0042] Figure 3 This is a schematic diagram of the structure of a circuit to be simulated provided in an embodiment of this disclosure. Figure 2 ;

[0043] Figure 4 This is a schematic flowchart of another step of a circuit simulation method provided in this embodiment of the disclosure;

[0044] Figure 5 This is a schematic diagram of the program modules of a circuit simulation device provided in an embodiment of the present disclosure;

[0045] Figure 6 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. Furthermore, although the disclosure in this disclosure is based on one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation method on its own.

[0047] It should be noted that the brief descriptions of terms in this disclosure are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this disclosure. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0048] The terms "first," "second," etc., used in this disclosure, the specification, claims, and the accompanying drawings are used to distinguish similar or related objects or entities and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms can be used interchangeably where appropriate, for example, in situations where implementation can proceed in an order other than those given in the illustrations or description of embodiments of this disclosure.

[0049] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclude inclusion. For example, a product or device that includes a series of components is not necessarily limited to those components that are explicitly listed, but may include other components that are not explicitly listed or that are inherent to such product or device. When an element is referred to in this disclosure as being “connected” to another element, it may be directly connected to the other element, or there may be an intermediate element through which the connection to the other element takes place.

[0050] The term "module" as used in the embodiments of this disclosure refers to any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code capable of performing the functions associated with that element.

[0051] The embodiments disclosed herein can be applied to the field of semiconductor technology, for example, to the design process of integrated circuits.

[0052] In some implementations, the design flow of integrated circuits typically includes circuit design, pre-simulation, layout design, and post-simulation. Circuit design involves designing the circuit based on its function; pre-simulation simulates the circuit's function, including parameters such as power consumption, current, voltage, temperature, and input / output characteristics; layout design generates the circuit layout based on the designed circuit; and post-simulation, after the layout design is completed, extracts parasitic parameters from the circuit and adds these parameters to the circuit for simulation.

[0053] Currently, post-simulation using the Standard Parasitic Format (SPF) file does not include parasitic parameters of the power bus. All power supply output voltages use ideal voltage values, meaning that the power supply is assumed to have no internal resistance or parasitic impedance. As a result, the power supply terminal of the simulation device cannot obtain the voltage drop (IRdrop) of the power bus, and therefore cannot accurately evaluate the performance of the power bus.

[0054] The parasitic parameters mentioned above can include parasitic capacitance, parasitic resistance, and parasitic inductance. Parasitic capacitance itself is not a capacitor; the term "parasitic" means that no capacitor was originally designed into that location, but due to the presence of many adjacent metal conductors at different potentials, a certain capacitance inevitably exists between them. Since these conductors were not intentionally created to generate such capacitance, these accidentally appearing capacitors are called "parasitic capacitances." Such capacitances have no independent value; they are "parasitic" on the metal conductors that perform other functions. According to the principle of capacitance, a capacitor consists of two plates and an insulating medium. Therefore, parasitic capacitance is unavoidable. For example, in a circuit with many wires, parasitic capacitance will form between the wires. Parasitic capacitance affects the circuit's ability to operate at high speeds, sometimes causing circuit instability, parasitic oscillations, or even unwanted AC signal short circuits.

[0055] Parasitic resistance is an excess resistance generated in integrated circuit design. Moreover, parasitic resistance is cumulative. As the integration density increases, the parasitic resistance will increase, which will lead to a decrease in the performance of integrated circuits.

[0056] Parasitic inductance is inductance that is generated in wires or other components. Generally speaking, parasitic inductance will exist wherever there are wires. The magnitude of parasitic inductance not only affects the transient voltage and current of integrated circuits, but also affects the losses of integrated circuits.

[0057] In this context, an SPF file refers to a file with the ".spf" extension used in simulation. An SPF file can contain information such as the interconnect resistance, parasitic capacitance, and interconnect logic relationships between circuit units.

[0058] IR drop refers to the phenomenon of voltage drop and rise on the power and ground networks in integrated circuits. With the continuous evolution of semiconductor technology, the width of metal interconnects is becoming narrower, and the resistance is increasing (while the supply voltage is decreasing), making the IR drop effect more and more pronounced. IR drop is mainly divided into two types: static IR drop and dynamic IR drop. Static IR drop is mainly caused by voltage division in the metal interconnects of the power network, due to the inherent resistance of the interconnects themselves. Current flowing through the internal power interconnects generates a voltage drop, so static IR drop is primarily related to the structure and wiring details of the power network. Dynamic IR drop is caused by voltage drop due to current fluctuations during circuit switching. This phenomenon occurs at the clock edge. The clock edge transition not only triggers a large number of transistor switching but also causes transitions in combinational logic circuits, often generating a large current across the entire chip in a short period. This instantaneous large current causes the IR drop phenomenon. Furthermore, the more transistors that switch, the easier it is to trigger dynamic IR drop.

[0059] In the existing technology, taking Dynamic Random Access Memory (DRAM) as an example, as the clock frequency of DRAM becomes higher and the area becomes smaller, how to accurately evaluate the performance of the power bus so that the power bus can meet the performance requirements of the memory chip is a technical problem that urgently needs to be solved.

[0060] To address the aforementioned technical problems, this disclosure provides a circuit simulation method and apparatus. During post-simulation, the parameters of the power bus and the input voltage information at multiple first nodes on the power bus are included, enabling the post-simulation process to more closely approximate the actual operating conditions of the circuit to be simulated. This facilitates accurate evaluation of the power bus performance, ensuring that the power bus meets the performance requirements of the memory chip. Detailed procedures can be found in the following embodiments.

[0061] The circuit simulation method provided in this embodiment is applied to the circuit to be simulated, which can be understood as the aforementioned memory chip, or as a circuit module within the aforementioned memory chip.

[0062] In some embodiments, the circuit to be simulated may include various components, wires, power buses, etc. The power bus employs power bus technology, with each component suspended on the power bus; this is also known as a suspended bus.

[0063] In some embodiments, a power supply circuit is connected to the power bus described above. This power supply circuit is used to provide internal power to multiple first nodes of the power bus according to an external power supply (the voltage value of the internal power supply is not equal to the voltage value of the external power supply). For example, in addition to the externally supplied power, a DRAM chip has many newly generated voltage sources inside the chip to control the operation of word lines WL, common source (CS), etc.

[0064] Reference Figure 1 , Figure 1 This is a schematic diagram of the structure of a circuit to be simulated provided in an embodiment of this disclosure. Figure 1 .

[0065] In some embodiments, the circuit to be simulated includes a power bus 100 and a power circuit 101 connected to the power bus 100; wherein the power circuit 101 is used to provide internal power to a plurality of first nodes X of the power bus 100 according to the external power supply VCC and VSS.

[0066] Optionally, the circuit to be simulated may also include at least one load 102 connected to the power bus 100.

[0067] In some embodiments, no capacitors may be connected to the power bus 100, thereby enabling the power bus 100 to power on quickly enough after a power outage. Alternatively, a certain number of capacitors may be connected to the power bus 100, thereby reducing the IR drop of the power bus 100 and improving its performance.

[0068] Reference Figure 2 , Figure 2 This is a flowchart illustrating the steps of a circuit simulation method provided in this embodiment of the disclosure. This circuit simulation method can be applied to, for example... Figure 1 The circuit to be simulated is shown. In some embodiments of this disclosure, the circuit simulation method includes:

[0069] S201. Based on the design database of the circuit to be simulated, obtain the netlist and SPF file corresponding to the circuit to be simulated. The SPF file includes the parameters corresponding to the power bus, and the netlist includes the input voltage information at the above-mentioned multiple first nodes.

[0070] In circuit design, netlists are typically used to describe the interconnections between circuit components. Generally, they are text files that follow a certain tagging syntax.

[0071] Optionally, the netlist may include circuit description statements of the circuit to be simulated, such as the circuit connection method, the attributes, parameters, and identification information of the components, devices, power nodes, etc. that make up the circuit.

[0072] In some embodiments of this disclosure, the netlist may also include information that needs to be output during simulation (i.e., which nodes in the circuit to be simulated should be output as output terminals to output simulation results), as well as information about the circuit to be simulated that needs to be input during simulation.

[0073] In some embodiments of this disclosure, the parameters corresponding to the power bus include the power bus's own resistance and / or parasitic capacitance.

[0074] The inherent resistance and parasitic capacitance of the power bus are related to its width and length. In some embodiments, the parameters of the power bus can be its width, length, etc., and the simulation equipment determines the inherent resistance and / or parasitic capacitance of the power bus based on these parameters during simulation.

[0075] In some implementations, the SPF file includes parameters of each complete power bus in the circuit to be simulated. That is, the power buses in the circuit to be simulated are not segmented, and the self-resistance and / or parasitic capacitance of the power buses are the self-resistance and / or parasitic capacitance of each complete power bus. This ensures that the parameters corresponding to the power buses obtained are accurate.

[0076] In some implementations, the SPF file may also include device parameters for all loads connected to the power bus. These device parameters may refer to the characteristic dimension information of each device within the load.

[0077] The aforementioned feature dimensions can be the smallest dimensions in a semiconductor device. For example, in CMOS processes, a typical feature dimension is the width of the "gate," which is also the channel length of a MOS device.

[0078] S202. Based on the netlist and SPF file, simulate the circuit to be simulated.

[0079] In some implementations, after generating the circuit layout based on the circuit to be simulated, post-simulation is performed based on the acquired netlist and SPF file to obtain the simulation results of the circuit to be simulated.

[0080] In the post-simulation process, the power supply circuit is shut down to provide internal power to multiple first nodes of the power bus based on external power supply. The input voltages at the multiple first nodes recorded in the netlist are used as the ideal input voltages of the power bus. In other words, during the post-simulation of the circuit to be simulated, the input voltages at the multiple first nodes recorded in the netlist are used to replace the internal voltages provided by the power supply circuit to the multiple first nodes of the power bus based on external power supply.

[0081] S203. Based on the simulation results of the circuit to be simulated, determine whether the performance of the power bus meets the performance requirements of the circuit to be simulated.

[0082] In some implementations, the voltage value at the second node where the load and power bus are connected in the circuit to be simulated can be determined based on the simulation results of the circuit to be simulated. Then, based on the voltage value and the input voltage values ​​at multiple first nodes recorded in the netlist, the IR drop at the second node where the load and power bus are connected can be calculated. Based on the calculated IR drop, it can be determined whether the performance of the power bus meets the performance requirements of the circuit to be simulated.

[0083] In some embodiments of this disclosure, the IR drop described above may be a dynamic IR drop.

[0084] Understandably, a decrease in the power bus voltage slows down the switching speed of transistors in the circuit, leading to a degraded circuit performance. Therefore, for high-performance circuit designs, IR drop must be kept within a very small range. If the global IR drop is too high, logic gates will malfunction, causing the circuit to fail completely, even if logic simulation shows the design is correct. Local IR drop is more sensitive and only occurs under specific conditions, such as when all bus data is synchronously toggling; therefore, the circuit will intermittently exhibit some functional failures.

[0085] In some implementations, if the calculated IR drop is greater than a preset threshold, it can be determined that the performance of the power bus cannot meet the performance requirements of the circuit to be simulated; if the calculated IR drop is less than or equal to the preset threshold, it can be determined that the performance of the power bus can meet the performance requirements of the circuit to be simulated.

[0086] The circuit simulation method provided in this disclosure, during post-simulation, obtains the netlist and SPF file corresponding to the circuit to be simulated from the design database of the circuit to be simulated. The SPF file includes parameters corresponding to the power bus, and the netlist includes input voltage information at multiple first nodes on the power bus. Based on the netlist and SPF file, the circuit to be simulated is simulated, which makes the simulation process closer to the actual working condition of the circuit to be simulated. Furthermore, based on the simulation results, the performance of the power bus can be accurately evaluated, so that the power bus can meet the performance requirements of the circuit to be simulated.

[0087] Based on the content described in the above embodiments, referring to Figure 3 , Figure 3 This is a schematic diagram of the structure of a circuit to be simulated provided in an embodiment of this disclosure. Figure 2 .

[0088] In some embodiments of this disclosure, the circuit to be simulated includes a power bus 100, on which a power circuit 101 is connected. The power circuit 101 is used to provide internal power to a plurality of first nodes X of the power bus 100 according to the external power supply VCC and VSS; VCC is an ideal voltage.

[0089] The power supply circuit 101 can be used to provide internal voltage to the power bus 100 based on the externally provided voltage source (VCC and VSS) when the circuit to be simulated is in working state.

[0090] In some embodiments of this disclosure, the circuit to be simulated further includes a load 102 connected to the power bus 100.

[0091] Optionally, the load 102 may include devices such as inverters and NAND gates. The SPF file includes the device parameters of the load 102. Optionally, these device parameters include the resistance and capacitance of each device in the load 102.

[0092] In some embodiments of this disclosure, to improve the performance of the power bus, the circuit to be simulated may further include a capacitor Cap connected to the power bus. The SPF file may also include parameter information for the capacitor Cap.

[0093] In some embodiments of this disclosure, the SPF file may also include feature size information of the remaining effective devices in the circuit to be simulated, excluding the load 102 and the capacitor Cap, as well as the self-resistance and / or parasitic capacitance of the remaining wires in the circuit to be simulated, excluding the power bus 100.

[0094] Optionally, the number of power supply circuits 101 turned on may vary depending on the operating mode of the circuit to be simulated.

[0095] The driving signal source for the power bus 100 is the signal "Y" output by the power supply circuit 101 when it is working.

[0096] In some implementations, the IR drop at the second node connecting the load and the power bus can be calculated under different operating modes of the circuit to be simulated, and the performance of the power bus under different operating modes can be determined based on the calculated IR drop to determine whether it meets the performance requirements of the circuit to be simulated.

[0097] Reference Figure 4 , Figure 4 This is a schematic flowchart illustrating another step of a circuit simulation method provided in an embodiment of this disclosure. In some embodiments of this disclosure, the circuit simulation method includes:

[0098] S401. Obtain the design database of the circuit to be simulated.

[0099] The structure of the circuit to be simulated can be referred to as follows. Figure 1 or Figure 3 The circuit to be simulated will not be described in detail here.

[0100] In some implementations, the design database described above is a design database based on LVS clean.

[0101] In the integrated circuit design process, the verification work after the layout design is completed includes Design Rule Check (DRC), layout and schematic verification. Figure 1 Consistency checks (LVS), etc. DRC's main purpose is to check the physical verification process of all potential open circuits, short circuits, or adverse effects caused by violations of design rules in the layout. It uses graphical operation functions to identify those violations. LVS's main purpose is to verify whether the circuit structure of the layout is consistent with the circuit schematic, including whether the electrical connections of all signals are consistent, whether the device types and sizes are consistent, etc. It compares the netlist of the original circuit schematic with the netlist of the circuit schematic extracted from the layout.

[0102] In some embodiments of this disclosure, the design database can be obtained after the designed layout has passed through DRC and LVS.

[0103] S402. Obtain the netlist corresponding to the circuit to be simulated based on the above design database.

[0104] The netlist includes input voltage information at multiple first nodes on the power bus.

[0105] S403. Obtain the SPF file corresponding to the circuit to be simulated based on the above design database.

[0106] The SPF file mentioned above includes parameters corresponding to the power bus.

[0107] Optionally, the parameters corresponding to the power bus mentioned above include the power bus's own resistance and / or parasitic capacitance.

[0108] In some implementations, the circuit to be simulated also includes a capacitor connected to the power bus; the SPF file also includes parameter information of the capacitor.

[0109] S404. Based on the above netlist and SPF file, simulate the circuit to be simulated.

[0110] After generating the circuit layout based on the circuit to be simulated, post-simulation is performed based on the netlist and SPF file mentioned above to obtain the simulation results of the circuit to be simulated.

[0111] S405. Based on the simulation results of the circuit to be simulated, determine whether the performance of the power bus meets the performance requirements of the circuit to be simulated. If yes, end the process; otherwise, the power bus needs to be improved, and return to modify the design database mentioned above.

[0112] In some embodiments of this disclosure, the voltage value at the second node where the load and power bus are connected can be determined based on the simulation results of the circuit to be simulated; and based on the voltage value and the input voltage information at the first node, it can be determined whether the performance of the power bus meets the performance requirements of the circuit to be simulated.

[0113] Specifically, the IR drop at the second node connecting the load and the power bus can be calculated based on the voltage value at the second node and the input voltage information at the first node. Based on the calculated IR drop, it can be determined whether the performance of the power bus meets the performance requirements of the circuit to be simulated.

[0114] Optionally, the width of the power bus in the layout can be determined based on the calculated IR drop at the second node of each load and power bus connection to determine whether it meets the performance requirements of the circuit to be simulated.

[0115] It is understandable that the wider the power bus is in the layout, the smaller the IR drop generated by the power bus. Therefore, when the calculated IR drop is greater than a certain threshold, it can be determined that the width of the power bus in the layout does not meet the performance requirements of the circuit to be simulated; when the calculated IR drop is less than or equal to the above threshold, it can be determined that the width of the power bus in the layout meets the performance requirements of the circuit to be simulated.

[0116] Optionally, the number of capacitors connected to the power bus can be determined based on the calculated IR drop at the second node of each load and power bus connection to determine whether the number of capacitors connected to the power bus meets the performance requirements of the circuit to be simulated.

[0117] It is understandable that the more capacitors connected to the power bus, the smaller the IR drop generated by the power bus. Therefore, when the calculated IR drop is greater than a certain threshold, it can be determined that the number of capacitors does not meet the performance requirements of the circuit to be simulated; when the calculated IR drop is less than or equal to the threshold, it can be determined that the number of capacitors meets the performance requirements of the circuit to be simulated.

[0118] In some implementations, the voltage threshold at the second node connecting the load and the power bus can be determined based on the impact of the voltage change at the second node on the signal timing of the circuit to be simulated. Then, based on the voltage value at the second node connecting the load and the power bus and the voltage threshold, it can be determined whether the performance of the power bus meets the performance requirements of the circuit to be simulated.

[0119] Understandably, the delay of a standard cell in an integrated circuit depends on the actual input voltage of that cell; if the voltage decreases, the delay increases. This increase in standard cell delay can impact chip design performance. If the available voltage for a standard cell falls below a certain level, the cell may stop working entirely, potentially causing the chip design to malfunction. Even when the IR drop is within limits, an increase in cell delay can still affect the chip design's setup and hold timing, sometimes leading to setup and hold timing failures.

[0120] In some implementations, the impact of voltage changes at the second node connecting the load and the power bus on the signal timing of the circuit to be simulated can be analyzed to determine the voltage threshold at the second node. Then, based on the voltage values ​​at the second node and the voltage threshold in the simulation results, it can be determined whether the performance of the power bus meets the performance requirements of the circuit to be simulated. For example, if the voltage value at the second node is greater than or equal to the voltage threshold, the power bus performance is determined to meet the performance requirements of the circuit to be simulated; if the voltage value is less than the voltage threshold, the power bus performance is determined to not meet the performance requirements of the circuit to be simulated.

[0121] In some implementations, if the performance of the power bus does not meet the performance requirements of the circuit to be simulated, the circuit to be simulated can be improved, and the design database of the circuit to be simulated can be updated according to the improvement scheme after the circuit to be simulated is improved.

[0122] Optionally, ways to improve the circuit to be simulated include, but are not limited to:

[0123] Increasing the width of the power bus in the layout; increasing the number of capacitors connected to the power bus; or adjusting the capacitance value of the capacitors connected to the power bus; or adjusting the distribution position of the capacitors connected to the power bus are not limited in the embodiments of this disclosure.

[0124] The circuit simulation method provided in this disclosure, during post-simulation, obtains the netlist and SPF file corresponding to the circuit to be simulated from the design database of the circuit to be simulated. The SPF file includes parameters corresponding to the power bus, and the netlist includes input voltage information at multiple first nodes on the power bus. Based on the netlist and SPF file, the circuit to be simulated is simulated, which makes the simulation process closer to the actual working condition of the circuit to be simulated. Furthermore, based on the simulation results, the performance of the power bus can be accurately evaluated. When the performance of the power bus does not meet the performance requirements of the circuit to be simulated, the power bus can be made to meet the performance requirements of the circuit to be simulated by improving the circuit to be simulated.

[0125] Based on the content described in the above embodiments, this disclosure also provides a circuit simulation device applied to a circuit to be simulated. The circuit to be simulated includes a power bus, on which a power circuit is connected. The power circuit is used to provide internal power to a plurality of first nodes of the power bus according to an external power supply.

[0126] Reference Figure 5 , Figure 5 This is a schematic diagram of the program modules of a circuit simulation device provided in an embodiment of this disclosure. In some embodiments of this disclosure, the circuit simulation device includes:

[0127] The acquisition module 501 is used to acquire the netlist and SPF file corresponding to the circuit to be simulated based on the design database of the circuit to be simulated. The SPF file includes the parameters corresponding to the power bus; the netlist includes the input voltage information at the plurality of first nodes.

[0128] The simulation module 502 is used to simulate the circuit to be simulated based on the netlist and SPF file.

[0129] The processing module 503 is used to determine whether the performance of the power bus meets the performance requirements of the circuit to be simulated based on the simulation results of the circuit to be simulated.

[0130] The circuit simulation apparatus provided in this embodiment obtains the netlist and SPF file corresponding to the circuit to be simulated from the design database of the circuit to be simulated during post-simulation. The SPF file includes parameters corresponding to the power bus, and the netlist includes input voltage information at multiple first nodes on the power bus. Based on the netlist and SPF file, the circuit to be simulated is simulated, which makes the simulation process closer to the actual working condition of the circuit to be simulated. Furthermore, based on the simulation results, the performance of the power bus can be accurately evaluated, so that the power bus can meet the performance requirements of the circuit to be simulated.

[0131] In one feasible implementation, the parameters corresponding to the power bus include the power bus's own resistance and / or parasitic capacitance.

[0132] In one feasible implementation, the circuit to be simulated further includes a capacitor connected to the power bus; the standard parasitic parameter format file also includes parameter information of the capacitor.

[0133] In one feasible implementation, the circuit to be simulated further includes at least one load connected to the power bus; the standard parasitic parameter format file also includes device parameters for all the loads.

[0134] In one feasible implementation, the device parameters of the load include the resistance and capacitance of the devices in the load.

[0135] In one feasible implementation, the processing module 503 is used to:

[0136] Based on the simulation results of the circuit to be simulated, determine the voltage value at the second node where the load and the power bus are connected; based on the voltage value, determine whether the performance of the power bus meets the performance requirements of the circuit to be simulated.

[0137] In one feasible implementation, the processing module 503 is used to:

[0138] Based on the voltage value, determine whether the width of the power bus in the layout meets the performance requirements of the circuit to be simulated.

[0139] In one feasible implementation, the processing module 503 is used to:

[0140] Based on the voltage value, determine whether the number of capacitors connected to the power bus meets the performance requirements of the circuit to be simulated.

[0141] In one feasible implementation, the processing module 503 is used to:

[0142] Based on the impact of the voltage value change on the signal timing of the circuit to be simulated, the voltage threshold at the first node where the load and the power bus are connected is determined.

[0143] Based on the voltage value and the voltage threshold, determine whether the performance of the power bus meets the performance requirements of the circuit to be simulated.

[0144] In one feasible implementation, the processing module 503 is further configured to:

[0145] If the performance of the power bus does not meet the performance requirements of the circuit to be simulated, then the width of the power bus in the layout is increased.

[0146] In one feasible implementation, the processing module 503 is further configured to:

[0147] If the performance of the power bus does not meet the performance requirements of the circuit to be simulated, then increase the number of capacitors connected to the power bus.

[0148] In one feasible implementation, the processing module 503 is further configured to:

[0149] If the performance of the power bus does not meet the performance requirements of the circuit to be simulated, then adjust the capacitance value of the capacitor or adjust the distribution position of the capacitor.

[0150] It should be noted that the specific execution of the acquisition module 501, simulation module 502, and processing module 503 in this embodiment can be found in the [reference needed]. Figures 1 to 4 The relevant content in the illustrated embodiments will not be repeated here.

[0151] Furthermore, based on the content described in the above embodiments, this disclosure also provides an electronic device, which includes at least one processor and a memory; wherein the memory stores computer execution instructions; the at least one processor executes the computer execution instructions stored in the memory to implement the various steps in the circuit simulation method described in the above embodiments, which will not be repeated here.

[0152] To better understand the embodiments of this disclosure, please refer to... Figure 6 , Figure 6 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure.

[0153] like Figure 6 As shown, the electronic device 60 of this embodiment includes: a processor 601 and a memory 602; wherein:

[0154] Memory 602 is used to store instructions executed by the computer;

[0155] The processor 601 is used to execute computer execution instructions stored in the memory to implement the various steps in the circuit simulation method described in the above embodiments, and for details, please refer to the relevant descriptions in the foregoing method embodiments.

[0156] Alternatively, the memory 602 can be either standalone or integrated with the processor 601.

[0157] When the memory 602 is set up independently, the device also includes a bus 603 for connecting the memory 602 and the processor 601.

[0158] Furthermore, based on the content described in the above embodiments, this disclosure also provides a computer-readable storage medium storing computer-executable instructions. When the processor executes the computer-executable instructions, it implements the various steps in the circuit simulation method described in the above embodiments. This embodiment will not repeat the details here.

[0159] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0160] The modules described above as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0161] Furthermore, the functional modules in the various embodiments of this disclosure can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The unit integrating the above modules can be implemented in hardware or in the form of hardware plus software functional units.

[0162] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A circuit simulation method, characterized in that, The method is applied to a circuit to be simulated, the circuit including a power bus, a power circuit connected to the power bus, and the power circuit providing internal power to multiple first nodes of the power bus according to an external power supply; the method includes: Based on the design database of the circuit to be simulated, obtain the netlist and standard parasitic parameter format file corresponding to the circuit to be simulated. The standard parasitic parameter format file includes parameters corresponding to the power bus. The parameters corresponding to the power bus include the power bus's own resistance and / or parasitic capacitance. The netlist includes input voltage value information at the plurality of first nodes. The circuit to be simulated is simulated based on the netlist and the standard parasitic parameter format file. Based on the simulation results of the circuit to be simulated, determine whether the performance of the power bus meets the performance requirements of the circuit to be simulated.

2. The method according to claim 1, characterized in that, The circuit to be simulated also includes a capacitor connected to the power bus; The standard parasitic parameter format file also includes parameter information for the capacitor.

3. The method according to claim 2, characterized in that, The circuit to be simulated also includes at least one load connected to the power bus; The standard parasitic parameter format file also includes device parameters for all the loads.

4. The method according to claim 3, characterized in that, The device parameters of the load include the resistance and capacitance of the devices in the load.

5. The method according to claim 3, characterized in that, The step of determining whether the performance of the power bus meets the performance requirements of the circuit to be simulated based on the simulation results of the circuit to be simulated includes: Based on the simulation results of the circuit to be simulated, determine the voltage value at the second node where the load and the power bus are connected; Based on the voltage value, determine whether the performance of the power bus meets the performance requirements of the circuit to be simulated.

6. The method according to claim 5, characterized in that, The step of determining whether the performance of the power bus meets the performance requirements of the circuit to be simulated based on the voltage value includes: Based on the voltage value, determine whether the width of the power bus in the layout meets the performance requirements of the circuit to be simulated.

7. The method according to claim 5, characterized in that, The step of determining whether the performance of the power bus meets the performance requirements of the circuit to be simulated based on the voltage value includes: Based on the voltage value, determine whether the number of capacitors connected to the power bus meets the performance requirements of the circuit to be simulated.

8. The method according to claim 5, characterized in that, The step of determining whether the performance of the power bus meets the performance requirements of the circuit to be simulated based on the voltage value includes: Based on the impact of the voltage value change on the signal timing of the circuit to be simulated, the voltage threshold at the first node where the load and the power bus are connected is determined. Based on the voltage value and the voltage threshold, determine whether the performance of the power bus meets the performance requirements of the circuit to be simulated.

9. The method according to claim 6, characterized in that, Also includes: If the performance of the power bus does not meet the performance requirements of the circuit to be simulated, then the width of the power bus in the layout is increased.

10. The method according to claim 7, characterized in that, Also includes: If the performance of the power bus does not meet the performance requirements of the circuit to be simulated, then increase the number of capacitors connected to the power bus.

11. The method according to claim 7, characterized in that, Also includes: If the performance of the power bus does not meet the performance requirements of the circuit to be simulated, then adjust the capacitance value of the capacitor or adjust the distribution position of the capacitor.

12. A circuit simulation device, characterized in that, The device is applied to a circuit to be simulated, the circuit including a power bus, a power supply circuit connected to the power bus, the power supply circuit being used to provide internal power to multiple first nodes of the power bus according to an external power supply; the device includes: The acquisition module is used to acquire the netlist and standard parasitic parameter format file corresponding to the circuit to be simulated based on the design database of the circuit to be simulated. The standard parasitic parameter format file includes parameters corresponding to the power bus. The parameters corresponding to the power bus include the self-resistance and / or parasitic capacitance of the power bus. The netlist includes input voltage value information at the plurality of first nodes. The simulation module is used to simulate the circuit to be simulated based on the netlist and the standard parasitic parameter format file. The processing module is used to determine whether the performance of the power bus meets the performance requirements of the circuit to be simulated based on the simulation results of the circuit to be simulated.

13. An electronic device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the circuit simulation method as described in any one of claims 1 to 11.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a computer, implement the circuit simulation method as described in any one of claims 1 to 11.

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