Point-to-point resistance calculation method, device and equipment of interconnection line network and medium

Abstract

The application provides a point-to-point resistance calculation method and device for an interconnection line network in an integrated circuit, electronic equipment and a storage medium, and is applied to the technical field of integrated circuits.The method comprises the following steps: taking a metal line as a side and the reciprocal of the resistance of the metal line as the weight of the side to construct a weighted undirected graph and a Laplacian matrix of the weighted undirected graph; performing Cholesky decomposition on the Laplacian matrix to obtain a Cholesky factor matrix; calculating a sparse approximate inverse of the Cholesky factor matrix; and calculating the equivalent resistance between any two nodes based on the sparse approximate inverse of the Cholesky factor matrix. The method can quickly respond to the query demand of the user for the resistance between the node pairs.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a method, apparatus, electronic device, and storage medium for calculating the point-to-point resistance of interconnect networks in integrated circuits. Background Technology

[0002] In the back-end design of integrated circuits, connecting semiconductor components with metal interconnects is called wiring. The result of wiring is the creation of various nets, which, depending on their function, include clock nets, power nets, signal nets, and so on. Because the number of semiconductor components in an integrated circuit is extremely large, sometimes reaching hundreds of millions, the size of a single net can be very large, such as including hundreds of millions of metal segments, making its wiring design very difficult and the related calculations very time-consuming.

[0003] In the wiring design process, to verify whether the design meets the circuit performance specifications, it is often necessary to calculate the resistance between certain points on a network. Based on these values, the topology and geometry of the network are continuously adjusted until certain design and performance constraints are met, achieving optimal electrical performance. This process of calculating the resistance between two points on an interconnect network is called point-to-point resistance calculation. However, related technologies lack a solution for quickly calculating point-to-point resistance. Summary of the Invention

[0004] The main objective of this invention is to provide a method, apparatus, electronic device, and storage medium for calculating point-to-point resistance of interconnect networks in integrated circuits, aiming to solve the technical problem of how to quickly perform point-to-point resistance calculations.

[0005] To achieve the above objective, a first aspect of the present invention provides a method for calculating the point-to-point resistance of an interconnect network in an integrated circuit, the interconnect network including multiple nodes and metal lines connecting the nodes, the method comprising:

[0006] Using the metal wire as an edge and the reciprocal of the resistance of the metal wire as the edge weight, construct a weighted undirected graph and the Laplace matrix of the weighted undirected graph;

[0007] Perform Joulesk decomposition on the Laplace matrix to obtain the Joulesk submatrix;

[0008] Calculate the sparse approximate inverse of the Joles gene submatrix;

[0009] The equivalent resistance between any two nodes is calculated based on the sparse approximate inverse of the Joles gene submatrix.

[0010] Optionally, the Jouleskiy decomposition of the Laplace matrix includes:

[0011] Obtain the number of nodes;

[0012] If the number of nodes is greater than a first preset threshold, perform an incomplete Jouleskiy decomposition on the Laplacian matrix;

[0013] If the number of nodes is not greater than a first preset threshold, perform a complete Jouleschi decomposition on the Laplace matrix.

[0014] Optionally, let the Laplace matrix be A and the Joles gene submatrix be L, then: A = L L T .

[0015] Optionally, let the number of nodes be n, and the Joles gene submatrix L be an n×n matrix, with the sparse approximate inverse of L being... Including column vectors for In the j-th column, the calculation of the sparse approximate inverse of the Joles gene submatrix includes:

[0016] calculate e j L is the j-th column of the identity matrix. i，j Let L be the element in the i-th row and j-th column. for In the i-th row, when j = n, the summation result is 0;

[0017] Get The number of non-zero elements;

[0018] exist If the number of non-zero elements exceeds the second preset threshold, The non-zero elements that meet the preset conditions are set to 0 to obtain

[0019] Optionally, the method further includes:

[0020] exist If the number of non-zero elements does not exceed the second preset threshold, then...

[0021] Optionally, let any two nodes be node p and node q, and the equivalent resistance between any two nodes be R(p, q). The calculation of the equivalent resistance between any two nodes based on the sparse approximate inverse of the Joles gene submatrix includes:

[0022]

[0023] in, The sparse approximate inverse of the Joles gene submatrix The p-th column, The sparse approximate inverse of the Joles gene submatrix The qth column.

[0024] Optionally, the will The non-zero elements that meet the preset conditions are set to 0 to obtain include:

[0025] right The non-zero elements in the sequence are arranged in ascending order of their absolute values ​​to form a sequential queue.

[0026] The result is obtained by retrieving all non-zero elements of the target from the ordered queue in ascending order and setting them to 0. All the target non-zero elements make and The degree of approximation meets the preset standard.

[0027] A second aspect of this invention provides a device for calculating the point-to-point resistance of an interconnect network in an integrated circuit, the device comprising:

[0028] A construction module is used to construct a weighted undirected graph and the Laplace matrix of the weighted undirected graph, using the metal wire as the edge and the reciprocal of the resistance of the metal wire as the edge weight.

[0029] The decomposition module is used to perform Joulesk decomposition on the Laplacian matrix to obtain the Joulesk submatrix.

[0030] The first calculation module is used to calculate the sparse approximate inverse of the Joles gene submatrix;

[0031] The second calculation module is used to calculate the equivalent resistance between any two nodes based on the sparse approximate inverse of the Joles gene submatrix.

[0032] A third aspect of the present invention provides an electronic device, comprising:

[0033] One or more processors;

[0034] Storage device for storing one or more programs.

[0035] When the one or more programs are executed by the one or more processors, the one or more processors execute the point-to-point resistance calculation method for interconnect networks in an integrated circuit provided by the second aspect of the present invention.

[0036] The fourth aspect of the present invention provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the point-to-point resistance calculation method for interconnect networks in an integrated circuit provided in the second aspect of the present invention.

[0037] As can be seen from the above embodiments of the present invention, the point-to-point resistance calculation method, apparatus, electronic device, and storage medium of the interconnect network in the integrated circuit provided by the present invention include multiple nodes and metal lines connecting the nodes. The method includes: constructing a weighted undirected graph and its Laplace matrix using the metal line as an edge and the reciprocal of the resistance of the metal line as the edge weight; performing Joulesky decomposition on the Laplace matrix to obtain the Joulesky submatrix; calculating the sparse approximate inverse of the Joulesky submatrix; and calculating the equivalent resistance between any two nodes based on the sparse approximate inverse of the Joulesky submatrix. By treating the resistance circuit corresponding to the interconnect network of the integrated circuit as a weighted undirected graph, performing Joulesky decomposition on its corresponding Laplace matrix, and then calculating the inverse matrix of the Joulesky submatrix, the equivalent resistance between any two nodes can be quickly responded to by the user's input query request for the resistance between node pairs using the inverse matrix. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1A A schematic diagram of an interconnect network of an integrated circuit according to an embodiment of the present invention is shown.

[0040] Figure 1B The schematic diagram illustrates a method for calculating the point-to-point resistance of an interconnect network in an integrated circuit according to an embodiment of the present invention.

[0041] Figure 2 This schematic diagram illustrates the structure of a point-to-point resistance calculation device for a small interconnect network of integrated circuits according to an embodiment of the present invention.

[0042] Figure 3 A block diagram of an electronic device illustrating a method for calculating the point-to-point resistance of an interconnect network in an integrated circuit according to an embodiment of the present invention is shown schematically. Detailed Implementation

[0043] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms "comprising," "including," etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0045] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0046] When using expressions such as "at least one of A, B, and C", they should generally be interpreted in accordance with the meaning that is commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc.).

[0047] This invention provides a method, apparatus, electronic device, and storage medium for calculating the point-to-point resistance of an interconnect network in an integrated circuit. The interconnect network includes multiple nodes and metal lines connecting the nodes. The method includes: constructing a weighted undirected graph and its Laplace matrix using the metal lines as edges and the reciprocal of the resistance of the metal lines as the edge weights; performing Joulesky decomposition on the Laplace matrix to obtain a Joulesky submatrix; calculating the sparse approximate inverse of the Joulesky submatrix; and calculating the equivalent resistance between any two nodes based on the sparse approximate inverse of the Joulesky submatrix. By treating the resistance circuit corresponding to the interconnect network of the integrated circuit as a weighted undirected graph, performing Joulesky decomposition on its corresponding Laplace matrix, and then calculating the inverse matrix of the Joulesky submatrix, the equivalent resistance between any two nodes can be quickly responded to by the user's input query request for the resistance between node pairs.

[0048] Figure 1A A schematic diagram of an interconnect network in an integrated circuit according to an embodiment of the present invention is shown.

[0049] An internetwork is a two-dimensional or three-dimensional interconnected structure made up of segments of metal wires, such as... Figure 1A The interconnect network shown is an interconnect network connecting four semiconductor components. In this integrated circuit, the nodes of the interconnect network refer to the points where the metal lines connecting the semiconductor components intersect, such as node A, node B, node C, node D, etc. This is understandable. Figure 1A The diagram only shows a portion of the nodes in the interconnect network.

[0050] Point-to-point resistance refers to the voltage difference between two nodes when 1 ampere of current flows into a resistive network from one node and 1 ampere of current flows out from another node. For example... Figure 1A As shown, the resistance value between points can be the resistance value from node A to node B, the resistance value from node B to node C, and so on.

[0051] Figure 1B The schematic diagram illustrates a method for calculating the point-to-point resistance of an interconnect network in an integrated circuit according to an embodiment of the present invention.

[0052] like Figure 1B As shown, the integrated circuit of this embodiment includes multiple nodes and metal lines connecting the nodes, and the method includes operations S101 to S104.

[0053] In operation S101, a weighted undirected graph and its Laplace matrix are constructed using the metal line as an edge and the reciprocal of the metal line's resistance as the edge weight.

[0054] In operation S102, the Laplace matrix is ​​subjected to Joulesky decomposition to obtain the Joulesky submatrix.

[0055] In operation S103, the sparse approximate inverse of the Joles gene submatrix is ​​calculated.

[0056] In operation S104, the equivalent resistance between any two nodes is calculated based on the sparse approximate inverse of the Joles gene submatrix.

[0057] An integrated circuit's complex network is a three-dimensional interconnected structure composed of segments of metal wires. The resistance of each metal wire segment is easily calculated, thus the complex network corresponds to a resistor network. Therefore, the point-to-point resistance is the voltage difference between two nodes when 1 ampere of current flows into the resistor network from one node and 1 ampere of current flows out from another node.

[0058] Specifically, in this operation S101, the description of the resistor network corresponding to a complex wire network is read in, and the resistor network corresponding to the integrated circuit is mapped to a weighted undirected graph, that is, each metal line is an edge of the graph, and the reciprocal of the resistance (conductance) of the metal line is the weight of the edge in the graph. The Laplace matrix of this weighted undirected graph is constructed.

[0059] In one embodiment of the present invention, operation S102, performing Joleskal decomposition on the Laplace matrix, includes: obtaining the number of nodes in the integrated circuit; performing incomplete Joleskal decomposition on the Laplace matrix when the number of nodes is greater than a first preset threshold; and performing complete Joleskal decomposition on the Laplace matrix when the number of nodes is not greater than the first preset threshold.

[0060] Understandably, incomplete Jouleskie decomposition is used when the number of nodes in the resistive network is particularly large. This invention does not specifically limit the first preset threshold; those skilled in the art can set it according to the actual situation.

[0061] In one embodiment of the present invention, let the Laplace matrix be A and the Jolais gene submatrix be L, then: A = L L T .

[0062] In one embodiment of the present invention, let the number of nodes in the integrated circuit be n, and the Joles gene submatrix L be an n×n matrix, with the sparse approximate inverse of L being... Including column vectors for In the j-th column, operation S103 calculates the sparse approximate inverse of the Joles gene submatrix, including operations S1-S4:

[0063] Operation S1, calculate e j L is the j-th column of the identity matrix. i，j Let L be the element in the i-th row and j-th column. for In the i-th row, when j = n, the summation result is 0.

[0064] Operation S2, obtain The number of non-zero elements.

[0065] Operation S3, in If the number of non-zero elements exceeds the second preset threshold, The non-zero elements that meet the preset conditions are set to 0 to obtain

[0066] Operation S4, in If the number of non-zero elements does not exceed the second preset threshold, then...

[0067] This invention does not specifically limit the second preset threshold; those skilled in the art can set it according to actual circumstances. For example, the second preset threshold = logn.

[0068] Specifically, operating S3 will The non-zero elements that meet the preset conditions are set to 0 to obtain Including: Arrange the non-zero elements in the array in ascending order of their absolute values ​​to obtain a sequential queue. Then, extract all the target non-zero elements from this sequential queue in ascending order and set them to 0. All non-zero elements of the target make and The degree of approximation meets the preset criteria. The preset criteria are, for example... and The following relationship is satisfied.

[0069]

[0070] Where ε is a preset arbitrary value, such as 10 -3 .

[0071] In one embodiment of the present invention, let the arbitrary two nodes be node p and node q, and the equivalent resistance between the arbitrary two nodes be R(p, q). Operation S104, based on the sparse approximate inverse of the Joles gene submatrix, calculates the equivalent resistance between the arbitrary two nodes, including:

[0072]

[0073] in, This is the sparse approximate inverse of the Joles gene submatrix. The p-th column, This is the sparse approximate inverse of the Joles gene submatrix. The qth column.

[0074] Figure 2 The schematic diagram illustrates the structure of a point-to-point resistance calculation device for an interconnect network in an integrated circuit according to an embodiment of the present invention.

[0075] The interconnect network of the integrated circuit includes multiple nodes and metal lines connecting the nodes, such as... Figure 2 As shown, the device includes a construction module 210, a decomposition module 220, a first calculation module 230, and a second calculation module 240.

[0076] The construction module 210 is used to construct a weighted undirected graph and the Laplace matrix of the weighted undirected graph using the metal line as the edge and the reciprocal of the resistance of the metal line as the edge weight. In one embodiment, the construction module 210 can be used to perform the operation S101 described above, which will not be repeated here.

[0077] The decomposition module 220 is used to perform Joulesk decomposition on the Laplacian matrix to obtain the Joulesk submatrix; in one embodiment, the decomposition module 220 can be used to perform the operation S102 described above, which will not be repeated here.

[0078] The first calculation module 230 is used to calculate the sparse approximate inverse of the Joles gene submatrix; in one embodiment, the first calculation module 230 can be used to perform the operation S103 described above, which will not be repeated here.

[0079] The second calculation module 240 is used to calculate the equivalent resistance between any two nodes based on the sparse approximate inverse of the Joles gene submatrix. In one embodiment, the second calculation module 240 can be used to perform the operation S104 described above, which will not be repeated here.

[0080] In one embodiment of the present invention, the decomposition module 220 includes:

[0081] The first acquisition submodule is used to acquire the number of nodes in the integrated circuit.

[0082] The first decomposition submodule is used to perform an incomplete Joleskia decomposition on the Laplacian matrix when the number of nodes is greater than a first preset threshold.

[0083] The second decomposition submodule is used to perform a complete Jouleschi decomposition on the Laplacian matrix when the number of nodes is not greater than a first preset threshold.

[0084] In one embodiment of the present invention, let the Laplace matrix be A and the Jolais gene submatrix be L, then: A = L L T .

[0085] In one embodiment of the present invention, let the number of nodes in the integrated circuit be n, and the Joles gene submatrix L be an n×n matrix, with the sparse approximate inverse of L being... Including column vectors for The first calculation module 230 includes the following in the j-th column:

[0086] The calculation submodule is used for calculation. e j L is the j-th column of the identity matrix.i，j Let L be the element in the i-th row and j-th column. for In the i-th row, when j = n, the summation result is 0;

[0087] The second acquisition submodule is used to acquire... The number of non-zero elements;

[0088] The first reset submodule is used to... If the number of non-zero elements exceeds the second preset threshold, The non-zero elements that meet the preset conditions are set to 0 to obtain

[0089] In one embodiment of the present invention, the device further includes:

[0090] The second reset submodule is used to... If the number of non-zero elements does not exceed the second preset threshold, then...

[0091] In one embodiment of the present invention, let the arbitrary two nodes be node p and node q, and the equivalent resistance between the arbitrary two nodes be R(p, q). The second calculation module 240 includes:

[0092]

[0093] in, This is the sparse approximate inverse of the Joles gene submatrix. The p-th column, This is the sparse approximate inverse of the Joles gene submatrix. The qth column.

[0094] In one embodiment of the present invention, the [subject] The non-zero elements that meet the preset conditions are set to 0 to obtain include:

[0095] right The non-zero elements in the sequence are arranged in ascending order of their absolute values ​​to form a sequential queue.

[0096] To obtain the result, retrieve all non-zero elements of the target from the ordered queue in ascending order and set them to 0. All non-zero elements of the target make and The degree of approximation meets the preset standard.

[0097] According to embodiments of the present invention, any plurality of modules among the construction module 210, decomposition module 220, first calculation module 230, and second calculation module 240 can be merged into one module, or any one of these modules can be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules can be combined with at least part of the functionality of other modules and implemented in one module. According to embodiments of the present invention, at least one of the construction module 210, decomposition module 220, first calculation module 230, and second calculation module 240 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or any other reasonable means of integrating or packaging circuitry, or implemented in software, hardware, or firmware, or in any appropriate combination of any of these three implementation methods. Alternatively, at least one of the construction module 210, decomposition module 220, first calculation module 230, and second calculation module 240 can be at least partially implemented as a computer program module, which, when run, can perform corresponding functions.

[0098] Figure 3 A block diagram of an electronic device illustrating a method for calculating the point-to-point resistance of an interconnect network in an integrated circuit according to an embodiment of the present invention is shown schematically.

[0099] like Figure 3 As shown, an electronic device 300 according to an embodiment of the present invention includes a processor 301, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 302 or a program loaded from a storage portion 308 into a random access memory (RAM) 303. The processor 301 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 301 may also include onboard memory for caching purposes. The processor 301 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0100] RAM 303 stores various programs and data required for the operation of electronic device 300. Processor 301, ROM 302, and RAM 303 are interconnected via bus 304. Processor 301 executes various operations of the method flow according to embodiments of the present invention by executing programs in ROM 302 and / or RAM 303. It should be noted that the programs may also be stored in one or more memories other than ROM 302 and RAM 303. Processor 301 may also execute various operations of the method flow according to embodiments of the present invention by executing programs stored in said one or more memories.

[0101] According to an embodiment of the present invention, the electronic device 300 may further include an input / output (I / O) interface 305, which is also connected to a bus 304. The electronic device 300 may also include one or more of the following components connected to the I / O interface 305: an input section 306 including a keyboard, mouse, etc.; an output section 307 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 308 including a hard disk, etc.; and a communication section 309 including a network interface card such as a LAN card, modem, etc. The communication section 309 performs communication processing via a network such as the Internet. A drive 310 is also connected to the I / O interface 305 as needed. A removable medium 311, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 310 as needed so that computer programs read from it can be installed into the storage section 308 as needed.

[0102] The present invention also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0103] According to embodiments of the present invention, a computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of the present invention, a computer-readable storage medium may include ROM 302 and / or RAM 303 and / or one or more memories other than ROM 302 and RAM 303 described above.

[0104] Embodiments of the present invention also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to cause the computer system to implement the item recommendation method provided in the embodiments of the present invention.

[0105] When the computer program is executed by the processor 301, it performs the functions defined in the system / apparatus of this invention. According to embodiments of the invention, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0106] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and downloaded and installed via communication section 309, and / or installed from removable medium 311. The program code contained in the computer program can be transmitted using any suitable network medium, including, but not limited to, wireless, wired, etc., or any suitable combination thereof.

[0107] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 309, and / or installed from the removable medium 311. When the computer program is executed by the processor 301, it performs the functions defined in the system of this embodiment of the invention. According to embodiments of the invention, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0108] According to embodiments of the present invention, program code for executing the computer programs provided in the embodiments of the present invention can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0109] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0110] Those skilled in the art will understand that the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0111] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A method for calculating the point-to-point resistance of an interconnect network in an integrated circuit, characterized in that, The interconnect network includes multiple nodes and metal wires connecting the nodes, and the method includes: Using the metal wire as an edge and the reciprocal of the resistance of the metal wire as the edge weight, construct a weighted undirected graph and the Laplace matrix of the weighted undirected graph. Perform Joulesk decomposition on the Laplace matrix to obtain the Joulesk submatrix; Calculate the sparse approximate inverse of the Joles gene submatrix; Based on the sparse approximate inverse of the Joles gene submatrix, calculate the equivalent resistance between any two nodes. Let any two nodes be node p and node q, and the equivalent resistance between any two nodes be... The calculation of the equivalent resistance between any two nodes based on the sparse approximate inverse of the Joles gene submatrix includes: ； in, The sparse approximate inverse of the Joles gene submatrix The p-th column, The sparse approximate inverse of the Joles gene submatrix The qth column.

2. The method for calculating the point-to-point resistance of an interconnect network in an integrated circuit according to claim 1, characterized in that, The Jouleskiy decomposition of the Laplace matrix includes: Obtain the number of nodes in the integrated circuit; If the number of nodes is greater than a first preset threshold, perform an incomplete Jouleskiy decomposition on the Laplacian matrix; If the number of nodes is not greater than a first preset threshold, perform a complete Jouleschi decomposition on the Laplace matrix.

3. The method for calculating the point-to-point resistance of an interconnect network in an integrated circuit according to claim 1 or 2, characterized in that, Let the Laplace matrix be A, and the Joles gene submatrix be L, then: A = LL T .

4. The method for calculating the point-to-point resistance of interconnect networks in integrated circuits according to claim 1, characterized in that, Let the number of nodes in the integrated circuit be n, and the Joles gene submatrix L be an n×n matrix, with the sparse approximate inverse of L being... , Including column vectors , j = n, n-1, ..., 1 for In the j-th column, the calculation of the sparse approximate inverse of the Joles gene submatrix includes: calculate e j L is the j-th column of the identity matrix. i,j Let L be the element in the i-th row and j-th column. for In the i-th row, when j=n, the summation result is 0; Get The number of non-zero elements; exist If the number of non-zero elements exceeds the second preset threshold, The non-zero elements that meet the preset conditions are set to 0 to obtain .

5. The method for calculating the point-to-point resistance of interconnect networks in integrated circuits according to claim 4, characterized in that, The method further includes: exist If the number of non-zero elements does not exceed the second preset threshold, then... = .

6. The method for calculating the point-to-point resistance of an interconnect network in an integrated circuit according to claim 4, characterized in that, The The non-zero elements that meet the preset conditions are set to 0 to obtain include: right The non-zero elements in the sequence are arranged in ascending order of their absolute values ​​to form a sequential queue. The result is obtained by retrieving all non-zero elements of the target from the ordered queue in ascending order and setting them to 0. All the target non-zero elements make and The degree of approximation meets the preset standard.

7. A device for calculating the point-to-point resistance of an interconnect network in an integrated circuit, characterized in that, The interconnect network includes multiple nodes and metal wires connecting the nodes, and the device includes: A construction module is used to construct a weighted undirected graph and the Laplace matrix of the weighted undirected graph, using the metal wire as the edge and the reciprocal of the resistance of the metal wire as the edge weight. The decomposition module is used to perform Joulesk decomposition on the Laplacian matrix to obtain the Joulesk submatrix. The first calculation module is used to calculate the sparse approximate inverse of the Joles gene submatrix; The second calculation module is used to calculate the equivalent resistance between any two nodes based on the sparse approximate inverse of the Joles gene submatrix.

8. An electronic device, comprising: One or more processors; Storage device for storing one or more programs. Wherein, when the one or more programs are executed by the one or more processors, the one or more processors perform the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the method according to any one of claims 1 to 6.

Images