Sensing circuit and method of operation thereof

Abstract

A circuit includes a reference voltage node, first and second data lines, a sense amplifier, first and second switching components coupled between the first and second data lines and the first and second input terminals of the sense amplifier, third and fourth switching components coupled between the first and second data lines and the first and second nodes, fifth and sixth switching components coupled between the first and second nodes and the reference voltage node, and first and second capacitor components coupled between the first and second nodes and the first input terminal. In a first operating mode, the first to fourth switching components are all turned on, and the fifth and sixth switching components are all turned off. In a second operating mode, the first to fourth switching components are all turned off, and the fifth and sixth switching components are all turned on.

Description

Technical Field

[0001] The embodiments disclosed herein relate to a sensing amplifier circuit and its operation method. Background Technology

[0002] Integrated circuits (ICs) typically include memory arrays, where stored data can be accessed during read operations by sensing voltage differences generated from the stored data. Voltage-sensing amplifiers have various configurations that generate output data based on these voltage differences. Exemplary memory array types include random access memory (RAM), static random access memory (SRAM), and dynamic random access memory (DRAM). Summary of the Invention

[0003] According to some embodiments of this disclosure, a sensing circuit is provided, including a reference voltage node, a first data line and a second data line, a sensing amplifier including a first input terminal and a second input terminal, a first switching component coupled between the first data line and the first input terminal, a second switching component coupled between the second data line and the second input terminal, a third switching component coupled between the first data line and a first node, a fourth switching component coupled between the second data line and the second node, a fifth switching component coupled between the first node and the reference voltage node, a sixth switching component coupled between the second node and the reference voltage node, a first capacitor component coupled between the first node and the second input terminal, and a second capacitor component coupled between the second node and the first input terminal. The circuit is configured such that, in a first operating mode, each of the first to fourth switching components is turned on, and each of the fifth and sixth switching components is turned off; and in a second operating mode, each of the first to fourth switching components is turned off, and each of the fifth and sixth switching components is turned on.

[0004] According to some embodiments of this disclosure, a sensing circuit is provided including a ground node, a first data line and a second data line, a first component series coupled between the first data line and the second data line, wherein the first component series includes a first NMOS capacitor coupled between a first switching component and a second switching component, a second component series coupled between the first data line and the second data line, wherein the second component series includes a second NMOS capacitor coupled between a third switching component and a fourth switching component, a sensing amplifier including a first input terminal coupled to a first terminal of the first NMOS capacitor and a second input terminal coupled to a first terminal of the second NMOS capacitor, a first NMOS transistor coupled between a second terminal of the first NMOS capacitor and a ground node, and a second NMOS transistor coupled between a second terminal of the second NMOS capacitor and a ground node. The circuit is configured to, in a first portion of a read operation, turn off each of the first to fourth switching components and turn on each of the first and second NMOS transistors, and in a second portion of a read operation, turn on each of the first to fourth switching components and turn off each of the first and second NMOS transistors.

[0005] According to some embodiments of this disclosure, a method for operating a sense amplifier circuit includes, in a first operating mode, coupling a first terminal and a second terminal of a first capacitor component to a first data line and a second data line, respectively, wherein the second terminal of the first capacitor component includes a first input terminal of the sense amplifier; coupling a first terminal and a second terminal of a second capacitor component to a second data line and a first data line, respectively, wherein the second terminal of the second capacitor component includes a second input terminal of the sense amplifier; and in a second operating mode, decoupling the first terminal and the second terminal of each of the first capacitor component and the second capacitor component from each of the first data line and the second data line; coupling the first terminal of each of the first capacitor component and the second capacitor component to a reference voltage node; and using the sense amplifier to detect the voltage difference between the first data line and the second data line. Attached Figure Description

[0006] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of explanation.

[0007] Figure 1 This is a schematic diagram of a sense amplifier circuit according to some embodiments.

[0008] Figure 2 This is a schematic diagram of the operating parameters of a sense amplifier circuit according to some embodiments.

[0009] Figure 3 This is a schematic diagram of a sense amplifier circuit according to some embodiments.

[0010] Figure 4 This is a schematic diagram of a sense amplifier circuit according to some embodiments.

[0011] Figure 5 This is a schematic diagram of a sense amplifier circuit according to some embodiments.

[0012] Figure 6 This is a flowchart of the operation method of a sensing amplifier circuit according to some embodiments. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. Such repetition is for the sake of brevity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. In addition to the orientations depicted in the figures, these spatially relative terms are also intended to encompass different orientations of the device in use or operation. The equipment may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0015] In various embodiments, the sense amplifier circuitry includes capacitive components coupled between the data line pair and the differential input of the voltage sense amplifier. The circuitry includes switching components configured to charge each capacitive component to the voltage difference on the data line, and then couple the capacitive components to a reference voltage node to amplify the voltage difference input to the sense amplifier. Compared to methods that directly input the data line voltage difference to the sense amplifier, this circuitry thus improves sensing margin and speed, particularly when detecting data line voltage differences that are small relative to the original sense amplifier offset voltage.

[0016] According to the different embodiments discussed below, Figure 1 and 3 -5 are schematic diagrams of sensing amplifier circuits 100 and 300-500, also known as circuits 100 and 300-500; Figure 2 This is a schematic diagram of the operating parameters of the sensing amplifier circuit; and Figure 6 This is a flowchart of a method 600 for operating a sense amplifier circuit. In different embodiments, the sense amplifier circuit is an integrated circuit (IC), for example, part of a memory circuit. In some embodiments, the sense amplifier circuit is part of a RAM, SRAM, or DRAM circuit.

[0017] In each embodiment discussed below, the sense amplifier circuit is configured to operate in each of two operating modes corresponding to a read operation of the memory circuit. In the first operating mode, also referred to as the first part of the read operation, the switching component is switched on (closed) to charge the capacitor component to the voltage difference on the data line pair. In the second operating mode, also referred to as the second part of the read operation, the switching component is switched off (opened), the capacitor component is coupled to a shared reference terminal, and the sense amplifier is used to detect the voltage difference thus amplified by the capacitor component.

[0018] In the embodiments discussed below, in the second operating mode, the capacitor assembly is coupled to a voltage reference node represented by a simulated ground symbol in the various figures. In some embodiments, the voltage reference node is configured to have a grounded voltage level or a reference voltage level other than a grounded voltage level, such as a supply voltage level.

[0019] Two or more circuit components are considered to be coupled based on one or more direct signal connections and / or one or more indirect signal connections, including one or more resistive components and / or one or more logic components, such as inverters or logic gates, between the two or more circuit components. In some embodiments, signal communication between the two or more coupled circuit components can be modified by one or more logic components, for example, by inverting or forming conditional control. In some embodiments, two or more circuit components are considered to be coupled based on signal connections including one or more capacitive components; therefore, the two or more circuit components are referred to as capacitively coupled in some embodiments.

[0020] Figure 1 This is a schematic diagram of circuit 100 according to some embodiments. Circuit 100 includes a sense amplifier 110, data lines DL and DLB, capacitor components C1 and C2, switching components S1-S6, and a reference voltage node.

[0021] Sensing amplifier 110 is an electronic circuit including input terminals T1 and T2 and one or more output terminals (not shown). Sensing amplifier 110 is configured to receive a differential voltage at input terminals T1 and T2, and to generate one or more output signals (not shown) at one or more output terminals indicating the polarity of the differential voltage. In some embodiments, sensing amplifier 110 includes one or more latch circuits. In some embodiments, sensing amplifier 110 includes sensing amplifier 410 or 510, as described below... Figure 4 and Figure 5 Let's have a discussion.

[0022] Data lines DL and DLB, also referred to in some embodiments as data line pairs DL / DLB, are configured to be coupled to memory circuit signal lines of memory cells in the memory circuitry during read operations. In some embodiments, the data line pair DL / DLB is coupled to a selection circuit (not shown), such as a multiplexer, and the memory circuitry is configured to couple the data line pair DL / DLB to a selected memory cell via the selection circuitry during a read operation, for example, by generating one or more control signals. The data lines DL and DLB are thus configured to have their respective voltages VDL and VDLB during read operations.

[0023] A capacitor assembly, such as capacitor assembly C1 or C2, is a two-terminal circuit assembly comprising one or more IC structures (e.g., capacitors) configured to have a predetermined capacitance value between two terminals. In various embodiments, the capacitor assembly is an IC structure comprising two or more electrodes separated by respective dielectric layers, an n-type transistor having a gate coupled to one of the two terminals and a source / drain coupled to each other and to the other of the two terminals. The capacitor assembly is thus configured to provide a predetermined capacitance value between the two terminals during operation.

[0024] A switching assembly, such as switching assemblies S1-S6, is an active circuit assembly comprising one or more IC structures, such as transistors, configured to selectively couple and decouple two terminals in response to one or more control signals received at one or more additional terminals, thereby providing a low-resistance path in the on (conducting) state and a high-resistance path in the off (cutoff) state during operation.

[0025] In some embodiments, the switching assembly includes an n-type transistor coupled between two terminals and having a gate configured to receive a control signal, and is thus configured to provide a low-resistance path between the two terminals in response to a control signal having a logically high level, and to provide a high-resistance path between the two terminals in response to a control signal having a logically low level.

[0026] In some embodiments, the switching assembly includes a p-type transistor coupled between two terminals and has a gate configured to receive and control signals, and is thus configured to provide a low-resistance path between the two terminals in response to a control signal having a logically low level, and to provide a high-resistance path between the two terminals in response to a control signal having a logically high level.

[0027] In some embodiments, the switching assembly includes a transmission gate coupled between two terminals, the transmission gate including two gates configured to receive complementary (inverted) control signals, and thus configured to provide a low-resistance path between the two terminals in operation in response to a control signal having a first logic level combination, and to provide a high-resistance path between the two terminals in response to a control signal having a second logic level combination.

[0028] exist Figure 1 and 3 In the embodiment shown in -5, each of the switching components S5 and S6 is an n-type metal-oxide-semiconductor (NMOS) transistor. In some embodiments, one or both of the switching components S5 or S6 are switching component types other than NMOS transistors, such as p-type metal-oxide-semiconductor (PMOS) transistors.

[0029] Circuit 100 includes a switching component S1 coupled between data line DL and input terminal T1, a switching component S2 coupled between data line DLB and input terminal T2, a switching component S3 coupled between data line DL and node N1, a switching component S4 coupled between data line DLB and node N2, a switching component S5 coupled between node N1 and reference voltage node, a switching component S6 coupled between node N2 and reference voltage node, a capacitor component C1 coupled between node N1 and input terminal T2, and a capacitor component C2 coupled between node N2 and input terminal T1.

[0030] Switching components S2 and S3, and capacitor component C1 coupled between switching components S2 and S3, are thus configured as a component series coupled between data lines DL and DLB, wherein input terminal T2 and node N1 correspond to the two terminals of capacitor component C1.

[0031] Switching components S1 and S4, and capacitor component C2 coupled between switching components S1 and S4, are thus configured as components coupled in series between data lines DL and DLB, wherein input terminal T1 and node N2 correspond to the two terminals of capacitor component C2.

[0032] Switching components S1-S4 are configured to receive one or more control signals. Figure 1(Not shown in the image), where switching components S1-S4 are configured to be turned on and off simultaneously, so that all four switching components S1-S4 have the same low-resistance path and high-resistance path within the same time interval. In different embodiments, switching components S1-S4 are all of the same type of switching component, such as NMOS or PMOS transistors, or include multiple types of switching components. In different embodiments, switching components S1-S4 are configured to receive the same control signal or multiple control signals.

[0033] exist Figure 1 In the embodiments depicted, each of the switching components S5 and S6 is configured to receive a control signal CP, wherein the switching components S5 and S6 are configured to turn on and off simultaneously, such that the switching components S5 and S6 have the same low and high resistance value paths within the same time interval. In some embodiments, the switching components S5 and S6 are configured to receive different control signals and are therefore configured to turn on and off simultaneously.

[0034] Circuit 100 is configured to control switching components S1-S6, for example, by including a control circuit configured to generate one or more control signals including a control signal CP, so that switching components S1-S4 have a low resistance path during the time interval when switching components S5 and S6 have a high resistance path, and switching components S1-S4 have a high resistance path during the time interval when switching components S5 and S6 have a low resistance path.

[0035] In the first operating mode, circuit 100 is configured to turn on each of the switching components S1-S4 and turn off each of the switching components S5 and S6, such that each of the capacitor components C1 and C2 is coupled to each of the data lines DL and DLB through two low-resistance paths and decoupled from the reference voltage node through the high-resistance paths of the switching components S5 and S6.

[0036] Based on the low-resistance paths of switching components S1 and S3, the voltage VDL on data line DL is displayed as voltage V1 at the terminal of capacitor component C1 corresponding to node N1, and as voltage VA at the terminal of capacitor component C2 corresponding to input terminal T1. Based on the low-resistance paths of switching components S2 and S4, the voltage VDLB on data line DLB is displayed as voltage V2 at the terminal of capacitor component C2 corresponding to node N2, and as voltage VB at the terminal of capacitor component C1 corresponding to input terminal T2.

[0037] The first operating mode is in Figure 2 This is described as Mode 1, where the control signal CP has a logic low level. Figure 2In the non-limiting embodiment depicted, the sensing amplifier 110 has an initialization state at the start of mode 1, such that voltages VA and VB (denoted as VA / VB) initially have the same voltage level represented by a single line. Since each of the capacitor components C1 and C2 is charged by the voltage levels on data lines DL and DLB, voltages VA and VB decrease to achieve a differential voltage value ΔV with an amplitude equal to |VDL – VDLB|. DL .

[0038] With the configuration of circuit 100, the differential voltage ΔV on capacitor component C1 is relative to the voltage V1 at node N1. DL The polarity of the differential voltage ΔV of capacitor component C2 relative to the voltage V2 at node N2. DL Their polarities are opposite.

[0039] In the second operating mode, Figure 2 In mode 2, circuit 100 is configured to turn off each of the switching components S1-S4, such that each of the capacitor components C1 and C2 is decoupled from each of the data lines DL and DLB through two high-resistance paths. The control signal CP transitions to a logic high level, thus turning on each of the switching components S5 and S6, and coupling each of nodes N1 (a terminal of capacitor component C1) and N2 (a terminal of capacitor component C2) to the reference voltage node through corresponding low-resistance paths.

[0040] Each terminal of capacitor components C1 and C2 is coupled to a reference voltage node, such that each of voltages V1 and V2 is driven to the reference voltage level. This is based on the differential voltage ΔV of capacitor component C1 relative to voltage V1. DL The differential voltage ΔV of capacitor component C2 relative to voltage V2 DL With opposite polarities, the difference between the voltages VA and VB at their respective input terminals T1 and T2 is thus driven to approximately equal to the differential voltage ΔV. DL The amplitude is twice that of the previous amplitude. This amplitude is... Figure 2 In this context, it is represented as nΔV DL , where n=2.

[0041] Therefore, circuit 100 is configured to charge each of capacitor components C1 and C2 to the voltage difference ΔV on the data line pair DL / DLB in the first operating mode. DL Then, in the second operating mode, capacitor components C1 and C2 are coupled to a reference voltage node to amplify the voltage difference between the voltages VA and VB input to the sensing amplifier 110. Compared to the method of directly inputting the data line voltage difference to the sensing amplifier, circuit 100 thus improves the sensing margin and speed, especially when detecting data line voltage differences that are small relative to the internal sensing amplifier offset voltage.

[0042] Figure 3 This is a schematic diagram of circuit 300 according to some embodiments. Circuit 300 includes a sense amplifier 110, data lines DL and DLB, capacitor components C1 and C2, switching components S1-S6, nodes N1 and N2, and a reference voltage node, each of which is described above with respect to... Figure 1 and Figure 2 The following discussion was conducted. Except that switching components S5 and S6 are not directly coupled to their respective nodes N1 and N2, the component configuration is the same as described above for circuit 100. Circuit 300 also includes capacitor components C3 and C4, switching components S7-S12, and nodes N3-N6.

[0043] Circuit 300 includes a switching component S7 coupled between nodes N1 and N3, a switching component S8 coupled between nodes N2 and N4, a switching component S9 coupled between data line DL and node N5, a switching component S10 coupled between data line DLB and node N6, a switching component S11 coupled between data line DL and node N4, a switching component S12 coupled between data line DLB and node N3, a capacitor component C3 coupled between nodes N3 and N5, and a capacitor component C4 coupled between nodes N4 and N6. Switching component S5 is coupled between node N5 and a reference voltage node, and switching component S6 is coupled between node N6 and the reference voltage node.

[0044] Switching components S9 and S12, and capacitor component C3 coupled between switching components S9 and S12, are configured as components coupled in series between data lines DL and DLB, wherein nodes N3 and N5 correspond to the two terminals of capacitor component C3.

[0045] Switching components S10 and S11, and capacitor component C4 coupled between switching components S10 and S11, are configured as components coupled in series between data lines DL and DLB, wherein nodes N4 and N6 correspond to two terminals of capacitor component C4.

[0046] As mentioned above Figure 1 The circuit 300 discussed is configured to control switch components S1-S6. Circuit 300 is also configured to control switch components S9-S12 to have low-resistance paths and high-resistance paths within the same time interval as switch components S1-S4, and to control switch components S7 and S8 to have low-resistance paths and high-resistance paths within the same time interval as switch components S5 and S6.

[0047] In the first operating mode, circuit 300 is configured to turn on each of the switching components S1-S4 and S9-S12 and turn off each of the switching components S5-S8, such that each of the capacitor components C1-C4 is coupled to each of the data lines DL and DLB through two low-resistance paths and is serially decoupled from the reference voltage node and adjacent components through the high-resistance paths of the switching components S5-S8.

[0048] Based on the low-resistance paths of switching components S9 and S11, the voltage VDL on data line DL is displayed as voltage V5 at the terminal of capacitor component C3 corresponding to node N5, and as voltage V4 at the terminal of capacitor component C4 corresponding to node N4. Based on the low-resistance paths of switching components S10 and S12, the voltage VDLB on data line DLB is displayed as voltage V6 at the terminal of capacitor component C4 corresponding to node N6, and as voltage V3 at the terminal of capacitor component C3 corresponding to node N3.

[0049] The differential voltage ΔV on the data line to DL / DLB DL Provided by capacitor components C3 and C4, and having opposite polarities relative to voltage V5 at node N1 and V6 at node N6.

[0050] In the second operating mode, circuit 300 is configured to turn off each of the switching components S1-S4 and S9-S12, thereby decoupling each of the capacitor components C1-C4 from each of the data lines DL and DLB, and to turn on each of the switching components S5-S8, thereby coupling each of nodes N1 to N3, nodes N2 to N4, and nodes N5 and N6 (corresponding to the terminals of capacitor components C3 and C4) to the reference voltage node.

[0051] Capacitor C1 is coupled between input terminal T2 and capacitor C3, capacitor C2 is coupled between input terminal T1 and capacitor C4, and the terminals of capacitors C3 and C4 are coupled to a reference voltage node. Therefore, voltage V1 is set to be equal to voltage V3, voltage V2 is set to be equal to voltage V4, and each of voltages V5 and V6 is driven to the reference voltage level. Based on the polarity of the differential voltages of capacitor C1 relative to voltage V1 / V3, capacitor C3 relative to voltage V5, capacitor C2 relative to voltage V2 / V4, and capacitor C4 relative to voltage V6, the difference between voltages VA and VB between each input terminal T1 and T2 is thus driven to approximately equal to the differential voltage ΔV. DL The amplitude is four times the size of the amplitude. Figure 2 In this context, it is represented as nΔV DL In the case of n=4.

[0052] exist Figure 3In the illustrated embodiment, circuit 300 includes a total of four components serially coupled between data lines DL and DLB, therefore voltage ΔV DL The voltage is amplified four times at the input of the sensing amplifier 110. In some embodiments, the circuit 300 includes a number of components in series other than four, such that the voltage ΔV DL The amplification factor at the input of the sensing amplifier 110 is increased by a corresponding factor, instead of four times, for example, six times. As the total number of components in series increases, the circuit sensitivity increases with the increase in circuit size and complexity.

[0053] Circuit 300 is configured to charge each of a plurality of capacitor components, such as capacitor components C1-C4, onto the data line pair DL / DLB in a first operating mode to generate a voltage difference ΔV. DL Then, in the second operating mode, the capacitor assembly is coupled to the reference voltage node to amplify the voltage difference between voltage VA and voltage VB input to the sensing amplifier 110, thereby obtaining the advantages of circuit 100 mentioned above.

[0054] Figure 4 and 5 These are schematic diagrams of circuits 400 and 500 according to some embodiments. Each of circuits 400 and 500 includes data lines DL and DLB, capacitor components C1 and C2, switching components S1-S6, nodes N1 and N2, and a reference voltage node, each of which is described above in relation to... Figure 1-3 The following description is provided. Circuit 400 also includes a sense amplifier 410 that can be used as a sense amplifier 110, while circuit 500 includes a sense amplifier 510 that can be used as a sense amplifier 110. Each of circuits 400 and 500 includes non-limiting examples of various components discussed below, with the same components as those in circuit 100 configured as described above.

[0055] exist Figure 4 and 5 In the embodiments depicted, each of circuits 400 and 500 includes each of switching components S1-S4 comprising a PMOS transistor, each of switching components S5 and S6 comprising an NMOS transistor, each of capacitor components C1 and C2 comprising an NMOS transistor, and each of switching components S1-S6 configured to receive the same control signal PGB. Each of circuits 400 and 500 includes: a series of components comprising capacitor component C1 and switching components S2 and S3, and a series of components comprising capacitor component C2 and switching components S1 and S4, the series of components configured to generate differential voltages VA / VB at inputs T1 and T2 according to the operating modes discussed above with respect to circuit 100. In addition... Figure 4 and Figure 5In addition to the components depicted in series, in some embodiments, one or both of circuits 400 or 500 include one or more components in series (not shown). Thus, differential voltages VA / VB are generated at inputs T1 and T2 according to the operating modes discussed above with respect to circuit 300.

[0056] exist Figure 4 In the depicted embodiment, the sense amplifier 410 includes transistors M1-M8, a power supply node configured to have a supply voltage VDD, output nodes Q and QB, and a reference node voltage. Transistors M1-M4 are PMOS transistors, and transistors M5-M8 are NMOS transistors.

[0057] Transistors M2 and M6 are coupled in series between the power supply node and the reference voltage node, and their drains are connected at the output node QB. Transistors M3 and M7 are coupled in series between the power supply node and the reference voltage node, and their drains are connected at the output node Q. The gate of transistor M6 is connected to the output node Q, and the gate of transistor M7 is connected to the output node QB. The gate of transistor M3 includes an input terminal T1 configured to receive voltage VA, and the gate of transistor M2 includes an input terminal T2 configured to receive voltage VB.

[0058] Transistors M2, M3, M6 and M7 are configured as latch circuits that generate voltages at output nodes Q and QB in response to voltages VA and VB, and based on the supply voltage VDD and the reference voltage level.

[0059] Transistor M1 is coupled between the supply voltage node and the gate of transistor M2; transistor M4 is coupled between the supply voltage node and the gate of transistor M3; transistor M5 is coupled between the output node QB and the reference voltage node; and transistor M8 is coupled between the output node Q and the reference voltage node. The gates of transistors M5 and M8 are configured to receive a control signal PR, and the gates of transistors M1 and M4 are configured to receive a control signal PRB that is complementary to (inverted) the control signal PR.

[0060] Transistors M1, M4, M5, and M8 are configured to perform an initialization operation, wherein each of transistors M1, M4, M5, and M8 is turned on, thereby causing each of voltages VA and VB to have the value of the supply voltage VDD, and each of output nodes Q and QB to have a reference voltage level.

[0061] exist Figure 5In the illustrated embodiment, the sense amplifier 510 includes transistors M1-M8, a power supply node, output nodes Q and QB, and a reference voltage node. Compared to sense amplifier 410, sense amplifier 510 includes the gate of transistor M2 connected to the gate of transistor M6 and the gate of output node Q, and the gate of transistor M3 connected to the gate of transistor M7 and the gate of output node QB. Output node Q includes an input terminal T1 configured to receive voltage VA, and output node QB includes an input terminal T2 configured to receive voltage VB.

[0062] Transistor pairs M2 / M6 and M3 / M7 are configured as cross-coupled inverters and set as latch circuits to generate voltages at output nodes Q and QB in response to voltages VA and VB, and based on the supply voltage VDD and the reference voltage level.

[0063] Transistors M1, M4, M5, and M8 are configured to perform the above-mentioned... Figure 4 The initialization operations discussed.

[0064] With the configuration discussed above, each of circuits 400 and 500 can be executed according to the read operation discussed above, thus enabling the benefits of circuits 100 and 300 discussed above to be realized.

[0065] Figure 6 This is a flowchart of a method 600 for operating a sense amplifier circuit according to one or more embodiments. Method 600 can be used with sense amplifier circuits, such as those described above. Figure 1-5 The circuits discussed are 100 or 300-500.

[0066] Figure 6 The order of operations in Method 600 is for illustrative purposes only; the operations of Method 600 can be performed in conjunction with... Figure 6 The different orders described herein are executed. In some embodiments, in addition to Figure 6 In addition to the operations described in the text, there are also Figure 6 The operations described herein are performed before, between, during, and / or after. In some embodiments, the operation of method 600 is an operation on a portion of memory circuitry, such as a RAM, SRAM, or DRAM array.

[0067] In operation 610, in some embodiments, the sense amplifier of the memory circuit is initialized. Initializing the sense amplifier includes setting one or more voltages on one or more nodes and / or terminals to one or more predetermined voltage levels.

[0068] In some embodiments, initializing the sense amplifier includes setting each of the two differential inputs to the same voltage level. In some embodiments, setting each of the two differential inputs to the same voltage level includes setting inputs T1 and T2 of the sense amplifier 110 to the same voltage level, as described above regarding... Figure 1-3 The discussion continues. In some embodiments, setting each of the two differential inputs to the same voltage level includes setting the inputs T1 and T2 of the sense amplifier 410 or 510 to the supply voltage VDD, as discussed above. Figure 4 and 5 The discussion.

[0069] In operation 620, in the first operating mode, the first and second terminals of the first and second capacitor components are coupled to the first and second data lines. In some embodiments, coupling the first and second terminals of the first and second capacitor components to the first and second data lines includes coupling the terminals of capacitor components C1 and C2 to data lines DL and DLB, as described above. Figure 1-5 The discussion.

[0070] The first and second terminals of the first and second capacitor components are coupled to the first and second data lines, including the second terminals of the first and second capacitor components, and the first and second input terminals of the sense amplifier, as described above. Figure 1-3 The input terminals T1 and T2 of the sensing amplifier 110 are discussed.

[0071] Couple the first and second terminals of the first and second capacitor components to the first and second data lines, including turning on a switching component coupled between the first and second capacitor components and the data lines, such as the one described above. Figure 1-5 The switches S1-S4 are discussed.

[0072] In some embodiments, the first and second terminals of the first and second capacitor components are coupled to the first and second data lines in response to a first logic level of a control signal, such as those described above. Figure 4 and 5 The control signal PGB is under discussion.

[0073] In some embodiments, coupling the first and second terminals of the first and second capacitor components to the first and second data lines includes coupling the first and second terminals of the third and fourth capacitor components to the first and second data lines. In some embodiments, coupling the first and second terminals of the third and fourth capacitor components to the first and second data lines includes coupling the terminals of capacitor components C3 and C4 to data lines DL and DLB, as described above. Figure 3 The discussion.

[0074] In operation 630, in the second operating mode, the first and second terminals of each of the first and second capacitor components are decoupled from each of the first and second data lines, the first terminal of each of the first and second capacitor components is coupled to a reference voltage node, and the sensing amplifier is used to determine the voltage difference between the first and second data lines.

[0075] In some embodiments, decoupling the first and second terminals of the first and second capacitor components from the first and second data lines includes decoupling the terminals of capacitor components C1 and C2 from data lines DL and DLB, as described above. Figure 1-5 The discussion.

[0076] Decoupling the first and second terminals of each of the first and second capacitor components from each of the first and second data lines includes turning off the switching components coupled between the first and second capacitor components and the data lines, as described above. Figure 1-5 The switches S1-S4 are discussed.

[0077] In some embodiments, coupling a first terminal of each of the first capacitor assembly and the second capacitor assembly to a reference voltage node includes coupling terminals of capacitor assemblies C1 and C2 to the reference voltage node, such as... Figure 1-5 The discussion.

[0078] Coupling the first terminal of each of the first capacitor assembly and the second capacitor assembly to the reference voltage node includes an on / off switching assembly, such as those mentioned above. Figure 1-5 The switch components S5 and S6 are discussed.

[0079] In some embodiments, decoupling the first and second terminals of the first and second capacitor components from the first and second data lines, and coupling the first terminal of each of the first and second capacitor components to a reference voltage node, is a second logic level responsive to a control signal, such as the one described above. Figure 4 and Figure 5 The control signal PGB is under discussion.

[0080] In some embodiments, decoupling the first and second terminals of the first and second capacitor components from the first and second data lines includes decoupling the first and second terminals of each of the third and fourth capacitor components from each of the first and second data lines. Coupling the first terminal of the first capacitor component to a reference voltage node includes capacitively coupling the first terminal of the first capacitor component to the reference voltage node via the third capacitor component, and coupling the first terminal of the second capacitor component to a reference voltage node includes capacitively coupling the first terminal of the second capacitor component to the reference voltage node via the fourth capacitor component.

[0081] In some embodiments, decoupling the first and second terminals of the first and second capacitor components from the first and second data lines includes decoupling each terminal of capacitor components C3 and C4 from each of the data lines DL and DLB, capacitively coupling the terminals of the first capacitor component C1 to a reference voltage via capacitor component C3, and as described above regarding Figure 3 The discussed method involves capacitively coupling the terminals of capacitor component C2 to the reference voltage node via capacitor component C4.

[0082] In some embodiments, determining the voltage difference between the first data line and the second data line using a sensing amplifier includes using sensing amplifier 110 to determine the differential voltage ΔV on data lines DL and DLB. DL As mentioned above Figure 1-3 The discussion.

[0083] In some embodiments, using a sense amplifier to determine the voltage difference between the first data line and the second data line includes based on a first voltage at the first input terminal, including the gate of the first PMOS transistor, and a second voltage at the second input terminal, including the gate of the second PMOS transistor. For example, a latch operation is performed using sense amplifier 410, as described above. Figure 4 The subject of discussion.

[0084] In some embodiments, determining the voltage difference between the first data line and the second data line using a sensing amplifier includes performing a latch operation based on a first voltage at a first input terminal including a first node of the sensing amplifier and a second voltage at a second input terminal including a second node of the sensing amplifier. For example, the latch operation is performed using sensing amplifier 510, as described above. Figure 5 The discussion.

[0085] By performing part or all of the operations of method 600, the sense amplifier circuit readout operation includes charging a capacitor assembly coupled between the data line pair and the differential input of the voltage sense amplifier, and then coupling the capacitor assembly to a reference voltage node to amplify the voltage difference input to the sense amplifier, thereby obtaining the benefits of circuits 100 and 300-500 as discussed above.

[0086] In some embodiments, the circuit includes a reference voltage node, a first data line and a second data line, a sense amplifier including a first input terminal and a second input terminal, a first switching component coupled between the first data line and the first input terminal, a second switching component coupled between the second data line and the second input terminal, a third switching component coupled between the first data line and the first node, a fourth switching component coupled between the second data line and the second node, a fifth switching component coupled between the first node and the reference voltage node, a sixth switching component coupled between the second node and the reference voltage node, a first capacitor component coupled between the first node and the second input terminal, and a second capacitor component coupled between the second node and the first input terminal. The circuit is configured to, in a first operating mode, turn on each of the first to fourth switching components and turn off each of the fifth and sixth switching components, and in a second operating mode, turn off each of the first to fourth switching components and turn on each of the fifth and sixth switching components. In some embodiments, each of the first and second capacitor components includes an n-type metal-oxide-semiconductor (NMOS) transistor configured as a capacitor. In some embodiments, each of the first to sixth switching components includes a gate configured to receive the same control signal. In some embodiments, each of the first through fourth switching components includes a p-type metal-oxide-semiconductor transistor, and each of the fifth and sixth switching components includes an n-type metal-oxide-semiconductor transistor. In some embodiments, the reference voltage node is configured to have a grounded voltage level. In some embodiments, the sense amplifier includes a latch circuit, wherein the latch circuit includes: a first p-type metal-oxide-semiconductor (PMOS) transistor and a second p-type metal-oxide-semiconductor (PMOS) transistor; a gate of the first PMOS transistor including a first input terminal; and a gate of the second PMOS transistor including a second input terminal. In some embodiments, the sense amplifier includes a latch circuit consisting of a first latch node and a second latch node, the first latch node including the first input terminal, and the second latch node including the second input terminal.In some embodiments, the circuit further includes: a seventh switching component coupled between the first node and the third node; an eighth switching component coupled between the second node and the fourth node; a ninth switching component coupled between the first data line and the fifth node; a tenth switching component coupled between the second data line and the sixth node; an eleventh switching component coupled between the first data line and the fourth node; a twelfth switching component coupled between the second data line and the third node; a third capacitor component coupled between the third node and the fifth node; and a fourth capacitor component coupled between the fourth node and the sixth node, wherein the fifth switching component is coupled between the fifth node and the reference voltage node, the sixth switching component is coupled between the sixth node and the reference voltage node, and the circuit is configured to turn on each of the seventh to twelfth switching components in a first operating mode and to turn off each of the seventh to twelfth switching components in a second operating mode.

[0087] In some embodiments, the circuit includes a ground node, a first data line and a second data line, a first component series coupled between the first data line and the second data line, wherein the first component series includes a first NMOS capacitor coupled between a first switching component and a second switching component, a second component series coupled between the first data line and the second data line, wherein the second component series includes a second NMOS capacitor coupled between a third switching component and a fourth switching component, a sense amplifier including a first input terminal coupled to a first terminal of the first NMOS capacitor and a second input terminal coupled to a first terminal of the second NMOS capacitor, a first NMOS transistor coupled between a second terminal of the first NMOS capacitor and a ground node, and a second NMOS transistor coupled between a second terminal of the second NMOS capacitor and a ground node. The circuit is configured to, in a first portion of a read operation, turn off each of the first to fourth switching components and turn on each of the first and second NMOS transistors, and in a second portion of a read operation, turn on each of the first to fourth switching components and turn off each of the first and second NMOS transistors. In some embodiments, each of the first to fourth switching components includes a p-type metal-oxide-semiconductor (PMOS) transistor. In some embodiments, each of the PMOS transistors, as well as the first NMOS transistor and the second NMOS transistor, includes a gate configured to receive the same control signal. In some embodiments, the sense amplifier includes: a first p-type metal-oxide-semiconductor (PMOS) transistor coupled in series with a third NMOS transistor between a power supply node and a ground node; and a second PMOS transistor coupled in series with a fourth NMOS transistor between the power supply node and the ground node, wherein the gate of the first PMOS transistor includes the first input terminal, and the gate of the second PMOS transistor includes the second input terminal. In some embodiments, the sense amplifier includes a cross-coupled first inverter and a second inverter, the input terminal of the first inverter including the first input terminal, and the input terminal of the second inverter including the second input terminal.In some embodiments, the circuit further includes: a third component serial coupled between the first data line and the second data line, wherein the third component serial includes a third NMOS capacitor coupled between a fifth switching component and a sixth switching component; a fourth component serial coupled between the first data line and the second data line, wherein the fourth component serial includes a fourth NMOS capacitor coupled between a seventh switching component and an eighth switching component; a ninth switching component coupled between a second terminal of the first NMOS capacitor and a first terminal of the third NMOS capacitor; and a tenth switching component coupled between a second terminal of the second NMOS capacitor and a first terminal of the fourth NMOS capacitor, wherein a first NMOS transistor is coupled between a second terminal of the third NMOS capacitor and a ground node, the second NMOS transistor is coupled between a second terminal of the fourth NMOS capacitor and a ground node, and the circuit is configured to turn off each of the fifth to tenth switching components in a first portion of a read operation and to turn on each of the fifth to tenth switching components in a second portion of a read operation.

[0088] In some embodiments, a method of operating a sense amplifier circuit includes, in a first operating mode, coupling a first terminal and a second terminal of a first capacitor component to a first data line and a second data line, respectively, wherein the second terminal of the first capacitor component includes a first input terminal of the sense amplifier; coupling a first terminal and a second terminal of a second capacitor component to a second data line and a first data line, respectively, wherein the second terminal of the second capacitor component includes a second input terminal of the sense amplifier; and in a second operating mode, decoupling the first and second terminals of each of the first and second capacitor components from each of the first and second data lines; coupling the first terminal of each of the first and second capacitor components to a reference voltage node; and using the sense amplifier to detect a voltage difference between the first and second data lines. In some embodiments, wherein in the first operating mode, the coupling of the first and second terminals of each of the first and second capacitor components is responsive to a first logic level of a control signal; and in the second operating mode, the coupling of the first and second terminals of each of the first and second capacitor components is decoupling from each of the first and second data lines; and the coupling of the first terminal of each of the first and second capacitor components to the reference voltage node is responsive to a second logic level of the control signal. In some embodiments, coupling the first terminal of the first capacitor assembly to the reference voltage node and coupling the first terminal of the second capacitor assembly to the reference voltage node each include turning on an n-type metal-oxide-semiconductor (NMOS) transistor. In some embodiments, using the sense amplifier includes performing a latching operation based on a first voltage at the first input terminal and a second voltage at the second input terminal, wherein the first input terminal includes the gate of a first p-type metal-oxide-semiconductor (PMOS) transistor. In some embodiments, using the sense amplifier includes performing a latching operation based on a first voltage at the first input terminal of a first node including the sense amplifier and a second voltage at the second input terminal of a second node including the sense amplifier.In some embodiments, the method further includes: in the first operating mode, coupling the first terminal and the second terminal of each of the third capacitor assembly and the fourth capacitor assembly to the first data line and the second data line; and in the second operating mode, decoupling the first terminal and the second terminal of each of the third capacitor assembly and the fourth capacitor assembly from the first data line and the second data line, wherein the coupling of the first terminal of the first capacitor assembly to the reference voltage node includes capacitively coupling the first terminal of the first capacitor assembly to the reference voltage node through the third capacitor assembly, and the coupling of the first terminal of the second capacitor assembly to the reference voltage node includes capacitively coupling the first terminal of the second capacitor assembly to the reference voltage node through the fourth capacitor assembly.

[0089] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of this disclosure.

[0090] [Explanation of Symbols]

[0091] 100, 300, 300-500, 400, 500: Circuit

[0092] 110, 410, 510: Sensing amplifiers

[0093] 600: Method

[0094] 610, 620, 630: Operation

[0095] C1~C4: Capacitor assembly

[0096] CP, PGB, PR, PRB: Control signals

[0097] DL, DLB: Data cable

[0098] M1~M8: Transistors

[0099] N1~N6: Nodes

[0100] Q, QB: Output nodes

[0101] S1~S12: Switching components

[0102] T1, T2: Input terminals

[0103] V1~V6, VA, VB, VDL, VDLB: Voltage

[0104] VDD: Supply voltage

[0105] ΔV DL Differential voltage value

Claims

1. A sensing circuit, comprising: Reference voltage node; First data line and second data line; A sensing amplifier, including a first input terminal and a second input terminal; A first switching component is coupled between the first data line and the first input terminal; A second switch assembly is coupled between the second data line and the second input terminal; A third switch component is coupled between the first data line and the first node; The fourth switch component is coupled between the second data line and the second node; A fifth switching component is coupled between the first node and the reference voltage node; A sixth switching component is coupled between the second node and the reference voltage node; A first capacitor assembly is coupled between the first node and the second input terminal; as well as The second capacitor assembly is coupled between the second node and the first input terminal. The circuit is configured as follows: In the first operating mode, each of the first to fourth switch components is turned on, and each of the fifth and sixth switch components is turned off. In the second operating mode, each of the first to fourth switch components is turned off and each of the fifth and sixth switch components is turned on.

2. The circuit of claim 1, wherein each of the first capacitor assembly and the second capacitor assembly includes an NMOS transistor configured as a capacitor.

3. The circuit of claim 1, wherein, Each of the first to the sixth switching components includes a gate configured to receive the same control signal.

4. The circuit of claim 3, wherein each of the first to fourth switching components includes a PMOS transistor, and each of the fifth and sixth switching components includes an NMOS transistor.

5. The circuit of claim 1, wherein the reference voltage node is configured to have a grounded voltage level.

6. The circuit of claim 1, wherein The sensing amplifier includes a latch circuit. The latch circuit mentioned above includes: First PMOS transistor and second PMOS transistor The gate of the first PMOS transistor includes the first input terminal; and The gate of the second PMOS transistor includes the second input terminal.

7. The circuit of claim 1, wherein The sensing amplifier includes a latch circuit composed of a first latch node and a second latch node. The first latch node includes the first input terminal, and The second latch node includes the second input terminal.

8. The circuit of claim 1, further comprising: The seventh switch component is coupled between the first node and the third node; The eighth switch assembly is coupled between the second node and the fourth node; The ninth switch component is coupled between the first data line and the fifth node; The tenth switch component is coupled between the second data line and the sixth node; The eleventh switch component is coupled between the first data line and the fourth node; A twelfth switch assembly is coupled between the second data line and the third node; A third capacitor assembly is coupled between the third node and the fifth node; as well as The fourth capacitor assembly is coupled between the fourth node and the sixth node. in The fifth switching assembly is coupled between the fifth node and the reference voltage node. The sixth switching assembly is coupled between the sixth node and the reference voltage node, and The circuit is configured to turn on each of the seventh to twelfth switch components in the first operating mode and to turn off each of the seventh to twelfth switch components in the second operating mode.

9. A sensing circuit comprising: A grounding node; First data line and second data line; A first component is serially coupled between the first data line and the second data line, wherein the first component serially includes a first switching component, a second switching component, and a first NMOS capacitor coupled between the first switching component and the second switching component; A second component is serially coupled between the first data line and the second data line, wherein the second component serially includes a third switch component, a fourth switch component, and a second NMOS capacitor coupled between the third switch component and the fourth switch component; The sensing amplifier includes a first input terminal coupled to a first terminal of the first NMOS capacitor and a second input terminal coupled to a first terminal of the second NMOS capacitor; The first NMOS transistor is coupled between the second terminal of the first NMOS capacitor and the ground node; as well as The second NMOS transistor is coupled between the second terminal of the second NMOS capacitor and the ground node. The circuit is configured as follows In the first part of the read operation, each of the first to fourth switching components is turned off, and each of the first and second NMOS transistors is turned on. In the second part of the read operation, the first switch assembly to the fourth switch assembly is turned on, and the first NMOS transistor and the second NMOS transistor are turned off.

10. The circuit of claim 9, wherein each of the first to fourth switching components comprises a PMOS transistor.

11. The circuit of claim 10, wherein each of the PMOS transistors, the first NMOS transistor, and the second NMOS transistor includes a gate configured to receive the same control signal.

12. The circuit of claim 9, wherein The sensing amplifier includes: The first PMOS transistor is coupled in series with the third NMOS transistor between the power supply node and the ground node; as well as The second PMOS transistor is coupled in series with the fourth NMOS transistor between the power supply node and the ground node. The gate of the first PMOS transistor includes the first input terminal, and The gate of the second PMOS transistor includes the second input terminal.

13. The circuit of claim 9, wherein The sensing amplifier includes a cross-coupled first inverter and a second inverter. The input terminal of the first inverter includes the first input terminal, and The input terminal of the second inverter includes the second input terminal.

14. The circuit of claim 9, further comprising: A third component is serially coupled between the first data line and the second data line, wherein the third component serially includes a fifth switch component, a sixth switch component, and a third NMOS capacitor coupled between the fifth switch component and the sixth switch component; A fourth component is serially coupled between the first data line and the second data line, wherein the fourth component serially includes a seventh switch component, an eighth switch component, and a fourth NMOS capacitor coupled between the seventh switch component and the eighth switch component; A ninth switching component is coupled between the second terminal of the first NMOS capacitor and the first terminal of the third NMOS capacitor; as well as The tenth switching component is coupled between the second terminal of the second NMOS capacitor and the first terminal of the fourth NMOS capacitor, wherein... The first NMOS transistor is coupled between the second terminal of the third NMOS capacitor and the ground node, the second NMOS transistor is coupled between the second terminal of the fourth NMOS capacitor and the ground node, and the circuit is configured to turn off each of the fifth to tenth switching components in a first part of a read operation and turn on each of the fifth to tenth switching components in a second part of a read operation.

15. A method of operating a sensing circuit, the method comprising: In the first operating mode: The first terminal and the second terminal of the first capacitor assembly are coupled to the first data line and the second data line, respectively, wherein the second terminal of the first capacitor assembly includes the first input terminal of the sense amplifier; The first terminal and the second terminal of the second capacitor assembly are coupled to the second data line and the first data line, respectively, wherein the second terminal of the second capacitor assembly includes the second input terminal of the sensing amplifier; as well as In the second operating mode: Decouple the first terminal and the second terminal of each of the first capacitor assembly and the second capacitor assembly from the first data line and the second data line; The first terminal of each of the first capacitor assembly and the second capacitor assembly is coupled to the reference voltage node; as well as The voltage difference between the first data line and the second data line is detected using the sensing amplifier.

16. The method of claim 15, wherein in the first operating mode, the first and second terminals of each of the first and second capacitor components are coupled in response to a first logic level of a control signal, and in the second operating mode, the first and second terminals of each of the first and second capacitor components are decoupled from each of the first and second data lines, and the first terminal of each of the first and second capacitor components is coupled to the reference voltage node in response to a second logic level of the control signal.

17. The method of claim 15, wherein Each of coupling the first terminal of the first capacitor assembly to the reference voltage node and coupling the first terminal of the second capacitor assembly to the reference voltage node includes turning on an NMOS transistor.

18. The method of claim 15, wherein Using the sense amplifier includes performing a latching operation based on a first voltage at the first input terminal and a second voltage at the second input terminal, wherein the first input terminal includes the gate of a first PMOS transistor.

19. The method of claim 15, wherein using the sensing amplifier includes performing a latching operation based on a first voltage at the first input terminal of a first node including the sensing amplifier and a second voltage at the second input terminal of a second node including the sensing amplifier.

20. The method of claim 15, further comprising: In the first operating mode, the first terminal and the second terminal of each of the third capacitor assembly and the fourth capacitor assembly are coupled to the first data line and the second data line. as well as In the second operating mode, the first and second terminals of each of the third and fourth capacitor components are decoupled from the first and second data lines, wherein... The coupling of the first terminal of the first capacitor assembly to the reference voltage node includes capacitively coupling the first terminal of the first capacitor assembly to the reference voltage node via the third capacitor assembly, and The coupling of the first terminal of the second capacitor assembly to the reference voltage node includes capacitively coupling the first terminal of the second capacitor assembly to the reference voltage node through the fourth capacitor assembly.

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