Data receiving circuit

Abstract

A data receiving circuit is provided. The data receiving circuit includes a data input circuit, a latch circuit, and a current source. The data input circuit is configured to receive an input signal. The latch circuit is configured to output an output signal in response to the input signal. The current source is configured to provide a current to the latch circuit. The current source is different from the data input circuit.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application Nos. 17 / 541,801 and 17 / 544,574 (i.e., priority dates of December 3, 2021 and December 7, 2021), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a data receiving circuit, and more particularly to a data receiving circuit having an inductive amplifier. Background Technology

[0003] In memory elements, input receivers are widely used to receive input signals. However, as the demands on the operating speed of memory elements increase, the performance of input receivers may fail to keep up, resulting in a smaller margin for correctly interpreting input data. In cases where input data is misinterpreted, the memory element may crash or malfunction.

[0004] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a data receiving circuit. The data receiving circuit includes a data input circuit, a latch circuit, and a current source. The data input circuit is configured to receive an input signal. The latch circuit is configured to output an output signal in response to the input signal. The current source is configured to provide current to the latch circuit. The current source is different from the data input circuit.

[0006] Another embodiment of this disclosure provides a data receiving circuit. The data receiving circuit includes a first transistor, a second transistor, a third transistor, and a latching circuit. The first transistor has a gate configured to receive an input signal. The latching circuit is configured to output an output signal in response to the input signal. The second transistor has a gate and a drain, the gate being configured to receive a first signal, and the drain being connected to the latching circuit. The third transistor has a gate and a drain, the gate being configured to receive the first signal, and the drain being connected to the latching circuit. The second and third transistors are configured to provide a current to the latching circuit in response to the first signal.

[0007] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or designs of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0008] When referring to the embodiments and claims in conjunction with the drawings, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0009] Figure 1A This is a circuit diagram illustrating a data receiving circuit according to some embodiments of this disclosure.

[0010] Figure 1B This is a timing diagram illustrating some embodiments of this disclosure. Figure 1A Timing waveforms of the data receiving circuit at different nodes.

[0011] Figure 1C These are circuit diagrams illustrating some embodiments of this disclosure. Figure 1A The equivalent circuit of the data receiving circuit.

[0012] Figure 1D These are circuit diagrams illustrating some embodiments of this disclosure. Figure 1A The equivalent circuit of the data receiving circuit.

[0013] Figure 2A This is a circuit diagram illustrating a data receiving circuit according to some embodiments of this disclosure.

[0014] Figure 2B This is a timing diagram illustrating some embodiments of this disclosure. Figure 2A The waveforms of the data receiving circuit at different nodes.

[0015] Figure 2C This is a timing diagram illustrating some embodiments of this disclosure. Figure 2A The waveforms of the data receiving circuit at different nodes.

[0016] Figure 2D These are circuit diagrams illustrating some embodiments of this disclosure. Figure 2A The equivalent circuit of the data receiving circuit.

[0017] The reference numerals in the attached figures are explained as follows:

[0018] 100: Data receiving circuit

[0019] 110: Input Circuit

[0020] 120: Latch circuit

[0021] 130: Isostat

[0022] 200: Data receiving circuit

[0023] 410: Input Circuit

[0024] 420: Latch circuit

[0025] 430: Isostat

[0026] 440: Current source (or current draw)

[0027] 450: Pulse Generator

[0028] A: signal

[0029] B: Output signal

[0030] G1: Inverter

[0031] G2: Delay circuit

[0032] G3: OR gate

[0033] I11: Current

[0034] I12: Current

[0035] I13: Current

[0036] I14: Current

[0037] IN1: Inverter

[0038] IN2: Inverter

[0039] P1: Period

[0040] P2: Period

[0041] T1: Time

[0042] T2: Time

[0043] T3: Time

[0044] T4: Time

[0045] T11: Transistor

[0046] T12: Transistor

[0047] T13: Transistor

[0048] T21: Transistor

[0049] T22: Transistor

[0050] T23: Transistor

[0051] T24: Transistor

[0052] T31: Transistor

[0053] T32: Transistor

[0054] T33: Transistor

[0055] T34: Transistor

[0056] T35: Transistor

[0057] T41: Transistor

[0058] T42: Transistor

[0059] T43: Transistor

[0060] T51: Transistor

[0061] T52: Transistor

[0062] T53: Transistor

[0063] T54: Transistor

[0064] T61: Transistor

[0065] T62: Transistor

[0066] T63: Transistor

[0067] T64: Transistor

[0068] T65: Transistor

[0069] T71: Transistor

[0070] T72: Transistor

[0071] TG1: Time

[0072] TG2: Time

[0073] V1: Clock signal

[0074] V2: Reference signal

[0075] V3: Signal

[0076] V4: Signal

[0077] V5: Reference Signal

[0078] Vcom1: Voltage

[0079] Vcom2: Voltage

[0080] Vcom3: Voltage

[0081] Vcom4: Voltage

[0082] Vdd: Power supply voltage

[0083] Veq: Equalized signal

[0084] Veq1: Equalized signal

[0085] Vin: Input signal

[0086] Vin1: Input signal

[0087] Vout1: Output

[0088] Vout2: Output

[0089] Vout3: Output

[0090] Vout4: Output

[0091] Vtop: Voltage

[0092] Vtop1: Voltage Detailed Implementation

[0093] The embodiments or examples of this disclosure illustrated in the accompanying drawings will now be described in specific language. It should be understood that this is not intended to limit the scope of the disclosure. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as things that would normally be done by one of ordinary skill in the art in relation to the content of this disclosure. Reference numerals may be repeated throughout the embodiments, but this does not mean that a feature of one embodiment is applicable to another embodiment, even if they share the same reference numerals.

[0094] It should be understood that although the terms first, second, third, etc., can be used to describe various elements, components, regions, layers, or parts, these elements, components, regions, layers, or parts are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer, or part from another. Therefore, the first element, component, region, layer, or part discussed below can be referred to as the second element, component, region, layer, or part without departing from the teachings of the present invention.

[0095] The terminology used herein is for describing specific embodiments only and is not intended to limit one to the concepts of the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context specifically indicates otherwise. It should be further understood that the terms “comprising” and “including” as used in this specification indicate the presence of the stated feature, integer, step, operation, element, or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0096] Figure 1A This is a circuit diagram illustrating a data receiving circuit 100 (or data receiver) according to some embodiments of the present disclosure. The data receiving circuit 100 includes an input circuit 110, a latch circuit 120, and an equalizer 130. In some embodiments, the data receiving circuit 100 may be or may include a sense amplifier. In some embodiments, the input circuit 110 and the latch circuit 120 may be collectively referred to as the sense amplifier.

[0097] Input circuit 110 includes transistors T11, T12, and T13. In some embodiments, transistors T11, T12, and T13 are P-type metal-oxide-semiconductor (PMOS) transistors. The source of transistor T11 is connected to receive a power supply voltage Vdd. The gate of transistor T11 is connected to receive a clock signal V1. In some embodiments, the clock signal V1 is the same as the equalization signal Veq. For example, the clock signal V1 and the equalization signal Veq have the same clock. The drain of transistor T11 is connected to the sources of transistors T12 and T13. The gate of transistor T12 is connected to receive a reference signal V2. The drain of transistor T12 is connected to latch circuit 120 (e.g., connected to the source of transistor T21). The gate of transistor T13 is connected to receive an input signal Vin. The drain of transistor T13 is connected to latch circuit 120 (e.g., connected to the source of transistor T23). In some embodiments, a voltage level of the reference signal V2 is in the range of about 0.1Vdd to about 0.42Vdd. In other embodiments, the reference signal V2 may have other voltage levels as required by design. In some embodiments, a voltage level of the input signal Vin is in the range of about -0.2V to about Vdd + 0.2V. In other embodiments, the input signal Vin may have other voltage levels as required by design.

[0098] The latch circuit 120 may include two inverters, with the output of one inverter connected to the input of the other inverter. For example... Figure 1AAs shown, the latch circuit 120 includes transistors T21, T22, T23, and T24. Transistors T21 and T22 define an inverter, while transistors T23 and T24 define another inverter. Transistors T21 and T23 are PMOS transistors, and transistors T22 and T24 are N-type metal-oxide-semiconductor (NMOS) transistors.

[0099] The source of transistor T21 is connected to the drain of transistor T12. The gate of transistor T21 is connected to the gate of transistor T22, the drain of transistor T23, and the drain of transistor T24. The drain of transistor T21 is connected to the drain of transistor T22. The source of transistor T22 is connected to a common voltage (e.g., ground). The drains of transistors T21 and T22 can serve as the output terminal Vout1 of the data receiving circuit 100.

[0100] The source of transistor T23 is connected to the drain of transistor T13. The drain of transistor T23 is connected to the drain of transistor T24. The source of transistor T24 is connected to a common voltage (e.g., ground). The drains of transistors T23 and T24 can serve as the output terminal Vout2 of the data receiving circuit 100.

[0101] Equalizer 130 includes transistors T31, T32, T33, T34, and T35. In some embodiments, transistors T31, T32, T33, T34, and T35 are NMOS transistors. The gates of transistors T31, T32, T33, T34, and T35 are interconnected to receive an equalization signal Veq. The source of transistor T31 is connected to a common voltage (e.g., ground). The source of transistor T33 is connected to a common voltage (e.g., ground). The source of transistor T34 is connected to a common voltage (e.g., ground). The source of transistor T35 is connected to a common voltage (e.g., ground). Transistor T32 is connected between transistors T31 and T33.

[0102] Figure 1B This is a timing diagram illustrating some embodiments of this disclosure. Figure 1A The timing waveforms of the data receiving circuit 100 at different nodes.

[0103] In some embodiments, prior to time T1, the data receiving circuit 100 is configured to operate in the equalization phase. In this phase, the equalizer 130 is enabled. An equalization signal Veq (equal to the clock signal V1) with a high logic level (e.g., logic value "1") is input to the gates of transistors T31, T32, T33, T34, and T35 to turn these transistors on. Therefore, the drain voltages Vcom1 of transistor T12, Vcom2, Vout1, and Vout2 of transistor T13 are pulled low to a common voltage (e.g., ground), as... Figure 1C As shown, the equivalent circuit of the data receiving circuit 100 operating in the equalization stage is illustrated.

[0104] After time T1, the equalization phase is completed, and an equalization signal Veq with a low logic level (e.g., logic value "0") is input to the gates of transistors T31, T32, T33, T34, and T35 to turn off these transistors. Equalizer 130 is turned off. Figure 1D The equivalent circuit of the data receiving circuit 100 of some embodiments of this disclosure during this operation phase is illustrated.

[0105] At time T1, equalizer 130 is off. At this time, clock signal V1 equals equalizer signal Veq, transistor T11 is turned on, and an input signal Vin with a high logic level (e.g., logic value "1") is input to the gate of transistor T13. The voltage Vtop at the drain of transistor T11 (or the source of transistor T12 or T13) begins to rise. For example, voltage Vtop is pulled high. The voltage Vcom1 at the drain of transistor T12 (or the source of transistor T21) also begins to rise. For example, voltage Vcom1 is pulled high. The voltage Vcom2 at the drain of transistor T13 (or the source of transistor T23) also begins to rise. For example, voltage Vcom2 is pulled high.

[0106] Because the gate voltage of transistor T13 (e.g., the input signal Vin) is higher than the gate voltage of transistor T12 (e.g., the reference signal V2), the current I11 flowing through transistor T12 is greater than the current I12 flowing through transistor T13. After a sufficiently long time, transistor T21 is fully turned on. Since the gate voltage Vout2 of transistors T21 and T22 has been pulled down to a common voltage (e.g., ground) during this equalization phase, transistors T21 and T24 are fully turned on, while transistors T22 and T23 are fully turned off. Therefore, the voltage Vout1 at the drain of transistors T21 and T22 (or the gate of transistors T23 and T24) begins to rise at time T2. For example, voltage Vout1 is pulled high at time T2.

[0107] In some embodiments, at time T2, the data receiving circuit 100 is configured to operate in a data development phase. At time T3, the voltage Vout1 of the drains of transistors T21 and T22 (or the gates of transistors T23 and T24) has been fully pulled high to that high logic level (e.g., logic value "1"). In some embodiments, during times T3 and T4, the data receiving circuit 100 is configured to operate in a data latching phase.

[0108] After the data input period (e.g., from time T1 to time T4) is completed, the data receiving circuit 100 is configured to operate again in the first-level phase at time T4.

[0109] During data input (e.g., from time T1 to time T4), if the voltage of the input signal Vin is higher than the voltage of the reference signal V2, the data receiving circuit 100 is configured to output a voltage Vout1 with a high logic level (e.g., logic value "1"); if the voltage of the input signal Vin is lower than the voltage of the reference signal V2, the data receiving circuit 100 is configured to output a voltage Vout1 with a low logic level (e.g., logic value "0"). However, due to parasitic elements (e.g., resistors, inductors, and / or capacitors) present at the drains of transistors T12 and T13, currents I11 and I12 must charge (or discharge) these parasitic elements to pull up (or pull down) voltages Vcom1 and Vcom2.

[0110] like Figure 1A and Figure 1D As shown, currents I11 and I12 are determined by transistors T12 and T13, respectively. For example, current I11 (or current I12) can be determined by the voltage difference (e.g., Vsg) between the source and gate of transistor T12 (or transistor T13). However, because the gate voltage V2 of transistor T12 (e.g., about 0.1Vdd to about 0.42Vdd) and the gate voltage Vin of transistor T13 (about Vdd + 0.2V) are relatively high, currents I11 and I12 will decrease, which will make the rise time (or fall time) of voltage Vout1 relatively longer. For example, as Figure 1B As shown, the voltage Vout1 rises slowly compared to the input signal Vin. This situation becomes more severe as the operating speed of the data receiving circuit 100 increases. In some cases, the voltage Vout1 will not accurately reflect the input signal Vin, causing the data receiving circuit 100 to malfunction.

[0111] Figure 2AThis is a circuit diagram illustrating a data receiving circuit 200 (or data receiver) according to some embodiments of the present disclosure. The data receiving circuit 200 includes an input circuit 410, a latch circuit 420, an equalizer 430, a current source (or current draw) 440, and a pulse generator 450. In some embodiments, the data receiving circuit 200 may be or may include a sensing amplifier.

[0112] The input circuit includes transistors T41, T42, and T43. In some embodiments, transistors T41, T42, and T43 are P-type metal-oxide-semiconductor (PMOS) transistors. The source of transistor T41 is connected to receive a power supply voltage Vdd. The gate of transistor T41 is connected to receive a signal V3 from pulse generator 450. The drain of transistor T41 is connected to the sources of transistors T42 and T43. The gate of transistor T42 is connected to receive a reference signal V5. The drain of transistor T42 is connected to latch circuit 420 (e.g., to the drain of transistor T51, the drain of transistor T52, the gate of transistor T53, and the gate of transistor T54). The drain of transistor T42 is also connected to equalizer 430. The gate of transistor T43 is connected to receive an input signal Vin1. The drain of transistor T43 is connected to latch circuit 420 (e.g., to the drain of transistor T53, the drain of transistor T54, the gate of transistor T51, and the gate of transistor T52). The drain of transistor T43 is also connected to equalizer 430.

[0113] In some embodiments, the voltage level of the reference signal V5 is in the range of approximately 0.1Vdd to approximately 0.42Vdd. In other embodiments, the reference signal V5 may have other voltage levels as required by design. In some embodiments, the voltage level of the input signal Vin1 is in the range of approximately -0.2V to approximately Vdd + 0.2V. In other embodiments, the input signal Vin1 may have other voltage levels as required by design.

[0114] The latch circuit 420 may include two inverters (e.g., such as...). Figure 2D The inverters shown are IN1 and IN2, where the output of one inverter is connected to the input of the other. Figure 2A As shown, the latch circuit 420 includes transistors T51, T52, T53, and T54. Transistors T51 and T52 define one inverter, while transistors T53 and T54 define another inverter. Transistors T51 and T53 are PMOS transistors, and transistors T52 and T54 are N-type metal-oxide-semiconductor (NMOS) transistors.

[0115] The source of transistor T51 is connected to current source 440 (e.g., to the drain of transistor T71). The gate of transistor T51 is connected to the gate of transistor T52, the drain of transistor T53, and the drain of transistor T54. The drain of transistor T51 is connected to the drain of transistor T52. The source of transistor T52 is connected to a common voltage (e.g., ground). The drains of transistors T51 and T52 can serve as the output terminal Vout3 of the data receiving circuit 200.

[0116] The source of transistor T53 is connected to a current source 440 (e.g., to the drain of transistor T72). The drain of transistor T53 is connected to the drain of transistor T54. The source of transistor T54 is connected to a common voltage (e.g., to ground). The drains of transistors T53 and T54 can serve as the output terminal Vout4 of the data receiving circuit 200.

[0117] Equalizer 430 includes transistors T61, T62, T63, T64, and T65. In some embodiments, transistors T61, T62, T63, T64, and T65 are NMOS transistors. The gates of transistors T61, T62, T63, T64, and T65 are interconnected to receive the equalization signal Veq1. The source of transistor T61 is connected to a common voltage (e.g., ground). The source of transistor T63 is connected to a common voltage (e.g., ground). The source of transistor T64 is connected to a common voltage (e.g., ground). The source of transistor T65 is connected to a common voltage (e.g., ground). Transistor T62 is connected between transistors T61 and T63.

[0118] Current source 440 includes transistors T71 and T72. In some embodiments, transistors T71 and T72 are PMOS transistors. The source of transistor T71 is connected to receive a power supply voltage Vdd. The gate of transistor T71 is connected to receive a signal V4. The drain of transistor T71 is connected to latch circuit 420. The source of transistor T72 is connected to receive a power supply voltage Vdd. The gate of transistor T72 is connected to receive a signal V4, and the drain of transistor T72 is connected to latch circuit 420.

[0119] The pulse generator 450 may include an inverter G1, a delay circuit (or buffer) G2, and an OR gate G3. Figure 2B This is a timing diagram illustrating the waveforms of a pulse generator 450 at different nodes in some embodiments of this disclosure.

[0120] In operation, the pulse generator 450 is configured to receive an input (e.g., signal V4) having a first logic value with a period of P1 and to generate an output (e.g., signal V3) having a second logic value with a period of P2. In some embodiments, the first logic value and the second logic value are the same. For example, as Figure 2B As shown, the first logic value is 0, and the second logic value is 0. In some embodiments, the period P2 is less than the period P1. For example, P2 equals n × P1, where 0 <n<1。

[0121] In some embodiments, n can be determined by the delay time of the delay circuit G2. For example... Figure 2B As shown, at time TG1, a signal V4 with a logic value of "0" (equivalent to the equivalent signal Veq) is input to pulse generator 450. Specifically, signal V4 with a logic value of "0" is input to one end of delay circuit G2 and OR gate G3 (i.e., signal A). Delay circuit G2 is configured to input the delayed signal to inverter G1. Inverter G1 is configured to generate an output signal B with a logic value of "1". The difference between time TG2 and time TG1 is the delay time of delay circuit G2. Therefore, during the period from time TG1 to time TG2, OR gate G3 is configured to generate signal V3 with a logic value of "0".

[0122] Figure 2C This is a timing diagram illustrating some embodiments of this disclosure. Figure 2A The waveforms of the data receiving circuit 200 at different nodes.

[0123] In some embodiments, prior to time T5, the data receiving circuit 200 is configured to operate in the equalization phase. During this phase, the equalizer 430 is enabled. An equalization signal Veq1 with a high logic level (e.g., logic value "1") is input to the gates of transistors T61, T62, T63, T64, and T65 to turn these transistors on. Consequently, voltages Vcom3, Vcom4, Vout3, and Vout4 are pulled low to a common voltage (e.g., ground).

[0124] After time T5, the equalization phase is completed, and an equalization signal Veq1 with a low logic level (e.g., logic value "0") is input to the gates of transistors T61, T62, T63, T64, and T65 to turn these transistors off. Equalizer 430 is turned off. Figure 2D The equivalent circuit of the data receiving circuit 200 in some embodiments of this disclosure is shown for operation at this stage.

[0125] At time T5, an input signal Vin1 with a high logic level (e.g., logic value "1") is input to the gate of transistor T43. Simultaneously, signals V3 and V4 with a logic value "0" (e.g., at time T5, the input signal Vin1 with a high logic level) are input to the gate of transistor T43. Figure 2B During times TG1 and TG2, the voltage Vtop1 at the drain of transistor T41, T71, and T72 is input to turn them on. For example, Vtop1 is pulled high. Similarly, Vcom3 at the drain of transistor T71 also begins to rise, for example, Vcom3 is pulled high. Finally, Vcom4 at the drain of transistor T72 also begins to rise, for example, Vcom4 is pulled high.

[0126] Because the gate voltage of transistor T43 (e.g., input signal Vin1) is higher than the gate voltage of transistor T42 (e.g., reference signal V5), the voltage Vout3 at the drains of transistors T51 and T52 (or the gates of transistors T53 and T54) also begins to rise. For example, voltage Vout3 is pulled high. After the data input cycle (e.g., from time T5 to time T6) is completed, the data receiving circuit 200 is configured to operate again in the first-leveling phase on time period T6.

[0127] During data input (e.g., from time T5 to time T6), if the voltage of the input signal Vin1 is higher than the voltage of the reference signal V5, the data receiving circuit 200 is configured to output a voltage Vout3 with a high logic level (e.g., logic value "1"); if the voltage of the input signal Vin1 is lower than the voltage of the reference signal V5, the data receiving circuit 200 is configured to output a voltage Vout3 with a low logic level (e.g., logic value "0"). This occurs after the input signal Vin1 is input to transistor T43 and before the data operation is completed by latching circuit 420 (e.g., as...). Figure 2B After the time TG4 shown, the pulse generator 450 is configured to generate a signal V3 with a logic value of "1" to turn off the transistor T41, thus preventing the circuit from being damaged by a short circuit between Vdd and ground.

[0128] According to some embodiments, such as Figures 2A to 2D As shown, during data input, the gates of transistors T41, T71, and T72 are connected to ground via a signal having a logic value of "0". In other words, during data input, the gates of transistors T41, T71, and T72 are connected to ground. Therefore, the voltage difference (e.g., Vsg) between the source and gate of transistor T71 (or transistor T72) is higher than that shown. Figure 1A The voltage difference (e.g., Vsg) between the source and gate of transistor T12 (or transistor T13) shown makes the currents I13 and I14 generated by transistors T71 and T72 greater than the currents I11 and I12 generated by transistors T12 and T13. (Compared to...) Figure 1ACompared to the data receiving circuit 100, the data receiving circuit 200 can charge or discharge parasitic elements (e.g., resistors, inductors, and / or capacitors) with larger currents I13 and I14, which can increase the response time of the output of the data receiving circuit 200 (e.g., voltage Vout3). In other words, the rise time (or fall time) of voltage Vout3 can be reduced. This can increase the tolerance and operating speed of the data receiving circuit 200.

[0129] While this disclosure and its advantages have been detailed, it should be understood that other changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined by the scope of the disclosed patent. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0130] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of this document that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used in accordance with this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the patent disclosed in this disclosure.

Claims

1. A data receiving circuit, comprising: A data input circuit, configured to receive an input signal; A latching circuit configured to output an output signal in response to the input signal; A current source configured to provide a current to the latch circuit, wherein the current source is different from the data input circuit. as well as A pulse generator is configured to receive a first signal and generate a second signal in response to the first signal, wherein a period of the first signal is greater than a period of the second signal; Wherein, when the data input circuit is configured to receive the input signal, the first signal is used to turn on the current source, and the second signal is used to turn on the data input circuit; and Specifically, the second signal is used to close the data input circuit before a latching operation of the latching circuit is completed.

2. The data receiving circuit of claim 1, wherein the data input circuit includes a first input terminal and a second input terminal, the first input terminal being configured to receive a reference voltage, and the second input terminal being configured to receive the input signal.

3. The data receiving circuit of claim 2, wherein the latch circuit is configured to output the output signal having a high logic value when a voltage of the input signal is greater than the reference voltage.

4. The data receiving circuit of claim 2, wherein the latch circuit is configured to output the output signal having a low logic value when a voltage of the input signal is less than the reference voltage.

5. The data receiving circuit as claimed in claim 1, wherein a logic value of the first signal is different from a logic value of the second signal.

6. The data receiving circuit of claim 1, wherein the period of the second signal is approximately one-third of the period of the first signal.

7. The data receiving circuit of claim 1, wherein the current source is configured to provide the current to the latch circuit without flowing through the data input circuit.

8. The data receiving circuit of claim 1 further includes an equalizer configured to connect an output of the latch circuit and an output of the current source to ground when the equalizer is enabled.

9. A data receiving circuit, comprising: A first transistor, wherein a gate is configured to receive an input signal; A latching circuit configured to output an output signal in response to the input signal; A second transistor having a gate and a drain, the gate being configured to receive a first signal, and the drain being connected to the latching circuit; as well as A third transistor having a gate and a drain, the gate being configured to receive the first signal and the drain being connected to the latch circuit; A fourth transistor, one of whose gates is configured to receive a reference signal; A fifth transistor has a gate and a drain, the gate being connected to receive a second signal, and the drain being connected to a source of the first transistor and a source of the fourth transistor; A pulse generator is configured to receive the first signal and generate the second signal in response to the first signal, wherein a period of the first signal is greater than a period of the second signal; The second transistor and the third transistor are configured to provide a current to the latch circuit in response to the first signal; Wherein, when the first transistor is configured to receive the input signal, the first signal is used to turn on the second and third transistors, and the second signal is used to turn on the fifth transistor; and Specifically, the second signal is used to turn off the fifth transistor before a latching operation of the latching circuit is completed.

10. The data receiving circuit of claim 9, wherein the latch circuit is configured to output the output signal having a high logic value when a voltage of the input signal is greater than a reference voltage.

11. The data receiving circuit of claim 9, wherein one period of the second signal is approximately one-third of one period of the first signal.

12. The data receiving circuit of claim 9, wherein the pulse generator comprises: An inverter having an input terminal to receive the first signal; A delay circuit having an input terminal to receive the first signal; as well as An OR gate has a first input, a second input, and an output. The first input is connected to an output of an inverter, the second input is connected to an output of a delay circuit, and the output of the OR gate is configured to generate the second signal.

13. The data receiving circuit of claim 12, wherein the input terminal of the inverter and the input terminal of the delay circuit are connected to the gate of the second transistor and the gate of the third transistor.

14. The data receiving circuit of claim 13, wherein the output terminal of the OR gate is connected to the gate of the fifth transistor.

15. The data receiving circuit of claim 9, wherein when the first transistor is configured to receive the input signal, the first signal is used to turn on the second transistor and the third transistor.

16. The data receiving circuit of claim 15, wherein when the first transistor is configured to receive the input signal, the first signal is used to turn on the fifth transistor.

17. The data receiving circuit of claim 16, wherein the first signal is used to turn off the fifth transistor before a latching operation of the latching circuit is completed.

18. The data receiving circuit of claim 9, wherein the latching circuit comprises: A sixth transistor, the source of which is connected to the drain of the second transistor; and A seventh transistor, one of whose sources is connected to the drain of the third transistor; The gate of the sixth transistor is connected to the drain of the first transistor.

19. The data receiving circuit of claim 18, wherein the latching circuit comprises: An eighth transistor has a drain and a gate, the drain being connected to the drain of the sixth transistor and the gate being connected to the gate of the sixth transistor. as well as A ninth transistor has a drain and a gate, the drain being connected to the drain of the seventh transistor and the gate being connected to the gate of the seventh transistor.

20. The data receiving circuit of claim 19, wherein the drains of the sixth transistor and the eighth transistor are configured to output the output signal.

21. The data receiving circuit of claim 9 further includes an equalizer configured to connect an output of the latch circuit to ground when the equalizer is enabled.

22. The data receiving circuit of claim 21, wherein the equalizer comprises: A tenth transistor has a source and a drain, the source being connected to ground and the drain being connected to the drain of the second transistor. as well as An eleventh transistor has a source and a drain, the source being connected to ground and the drain being connected to the drain of the third transistor.

23. The data receiving circuit of claim 22, wherein the equalizer includes a twelfth transistor having a gate, a source and a drain, the gate being connected to a gate of the tenth transistor and a gate of the eleventh transistor, the source being connected to ground, and the drain being connected to the drain of the first transistor.

24. The data receiving circuit of claim 9, wherein the first transistor is disconnected from the second transistor and the third transistor.

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