Memory device, operating method thereof, and memory system

Abstract

A memory device, an operating method thereof, and a memory system, the memory device including a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to the second bit line, a first multiplexer transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first multiplexer transistor.

Description

Technical Field

[0001] This disclosure relates to a memory device and its operation method, as well as a memory system, and particularly to a memory device including a common gate line, its operation method, and a memory system. Background Technology

[0002] Typically, memory devices can be volatile memory devices or non-volatile memory (NVM) devices. Volatile memory devices can store data while powered on, but may lose the stored data once power is off. One-time programmable (OTP) memory devices are a type of NVM and are typically used in read-only memory (ROM). Once an OTP memory device is programmed, it cannot be reprogrammed. Fuse-operated memory cells are a type of OTP memory device, consisting of a one-transistor, one-resistor (1T1R) configuration. With continuous technological advancements and adherence to Moore's Law, there is a growing demand for devices with small cell regions. Summary of the Invention

[0003] One embodiment of this disclosure provides a memory device including a plurality of memory cells, a first bit line, a second bit line, a first word line, a first control transistor, a second control transistor, a first multiplexer transistor, and a sense amplifier. The plurality of memory cells includes a first memory cell and a second memory cell. The first bit line is connected to the first memory cell. The second bit line is connected to the second memory cell. The first word line is connected to both the first memory cell and the second memory cell. The first control transistor is connected to the first bit line. The second control transistor is connected to the second bit line. The first multiplexer transistor is commonly connected to both the first control transistor and the second control transistor. The sense amplifier is connected to the first multiplexer transistor.

[0004] Another embodiment of this disclosure provides a method for operating a memory device, comprising the following steps: during a read operation of a first memory cell, activating a first word line connected to the first memory cell and a second memory cell; activating a first control gate line connected to the first memory cell; activating a multiplexer control line connected to a multiplexer transistor, the multiplexer transistor being connected to a sense amplifier; and activating a common gate signal line connected to the gate terminal of the first common gate transistor and the gate terminal of the second common gate transistor, the first common gate transistor being connected to the first memory cell and the second common gate transistor being connected to the second memory cell.

[0005] Another embodiment of this disclosure provides a memory system including a plurality of memory cells, a sense amplifier, and a controller. The plurality of memory cells include a first memory cell and a second memory cell. The sense amplifier is connected to the memory cells via a plurality of bit lines. The controller is connected to the memory cells. The controller is configured to: during a read operation of the first memory cell, activate a first word line connected to the first memory cell and the second memory cell; activate a first control gate line connected to the first memory cell; activate a multiplexer control line connected to a multiplexer transistor connected to the sense amplifier; and activate a common gate signal line connected to the gate terminals of a first common gate transistor and a second common gate transistor, the first common gate transistor being connected to the first memory cell and the second common gate transistor being connected to the second memory cell. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figure 1 This illustration shows a schematic block diagram of a memory device according to some embodiments;

[0008] Figure 2 This describes an exemplary configuration of a memory cell according to some embodiments;

[0009] Figure 3A A schematic diagram illustrating an exemplary memory device according to some embodiments;

[0010] Figure 3B Description of the read operation according to some embodiments Figure 3A An example memory device;

[0011] Figure 4 This describes an exemplary memory device according to some embodiments;

[0012] Figure 5 This describes an exemplary memory device including a hybrid sensing structure according to some embodiments;

[0013] Figure 6 A flowchart illustrating an exemplary method of operating a memory device according to some embodiments.

[0014] [Symbol Explanation]

[0015] 100: Memory device

[0016] 102: Controller

[0017] 103: Memory Unit

[0018] 104: Memory Array

[0019] 112: Character line driver

[0020] 114: Source line driver

[0021] 116: Bit line driver

[0022] 118: Sensing Amplifier

[0023] 202: Fuse Resistor

[0024] 204a: Cascaded Gate Transistor

[0025] 204b: Access transistor

[0026] 300: Memory device

[0027] 302, 302n, 304, 304n: Common gate transistors

[0028] 310: Sensing Amplifier

[0029] 312, 312n: Control transistors

[0030] 322, 322n, 324, 324n, 342, 342n, 344, 344n: Cascaded Gate Transistors

[0031] 332, 332n, 352, 352n: Word line transistors

[0032] 362, 362n, 364, 364n, 372, 372n, 374, 374n: Fuses

[0033] 382, 382n: Multiplexer transistor

[0034] 390: Control line

[0035] 392, 392n: Multiplexer control lines

[0036] 394: Control Line

[0037] 400: Memory device

[0038] 402, 404, 406, 408: SG transistors

[0039] 412: Control transistor

[0040] 432: Word Line Transistor

[0041] 452: WL transistor

[0042] 500: Memory device

[0043] 500a: First sensing structure

[0044] 500b: Second sensing structure

[0045] 502, 504: SG transistors

[0046] 510: Sensing Amplifier

[0047] 512: Control transistor

[0048] 522m: Third stacked transistor

[0049] 522n: First stacked transistor

[0050] 524m: Fourth stacked transistor

[0051] 524n: Second stacked transistor

[0052] 532m, 532n, 534m, 534n: Stacked transistors

[0053] 544, 546: Control signals

[0054] 582: Multiplexer transistor

[0055] 590, 592m, 592n: Control lines

[0056] 592: Multiplexer control line

[0057] 594: Control Line

[0058] 600: Method

[0059] 602, 604, 606, 608: Operations

[0060] BL[0]~BL[k] : Bit lines

[0061] BL0~BL7, ​​BLm, BLn: Bit lines

[0062] CG0~CG7, CGL~CGn, CGm: Cascaded gate lines

[0063] M1~M12: Memory units

[0064] SG: Common gate

[0065] SL[0]~SL[m] : Source lines

[0066] WL[0]~WL[m] : Character lines Detailed Implementation

[0067] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0068] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another illustrated in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0069] As integrated circuit (IC) technology advances, IC features (e.g., transistor gate length) continue to shrink, allowing for the implementation of more circuitry within ICs. Memory devices may include matrices of memory cells arranged in rows and columns. A typical memory cell may include a selection transistor and a storage unit such as a resistor (e.g., a fuse resistor) or a capacitor. Memory devices also use sense amplifiers to access and detect the stored logic state of selected memory cells. However, as transistors become smaller, current structures can cause voltage stress issues. Therefore, using stacked transistor structures, such as for accessing rows (e.g., word line transistors and cascaded gate transistors) and for accessing columns (e.g., bit line transistors and cascaded gate transistors), reduces voltage stress on the transistors. However, using stacked transistors increases the width of the transistors to provide the same drive capability, resulting in an increase in the overall area of ​​the memory device. Larger memory cells are also undesirable because parasitic resistance may increase, potentially leading to additional power and compensation requirements.

[0070] In this regard, some memory devices form a common word line transistor (or word line selector) to activate multiple columns (via word lines), instead of using a word line transistor for each memory cell. A common point between two adjacent memory cells serves as the drain of the word line transistor. This reduces the area used by the word line transistors, and because the number of word line transistors is reduced by how many memory cells share the word line selector, the effective cell area is reduced. However, while the area is reduced, the reliability of the memory device may be reduced due to additional bit line leakage through unselected memory cells. For example, when reading from memory cells in the second row and the first column of the memory device, the word line in the second row is activated (e.g., set to an on-state voltage such as VDD), while the word line in the first row is deactivated (e.g., set to an off-state voltage such as 0 V). Furthermore, a voltage can be activated to enable a sense amplifier for the selected column, allowing current to flow through the bit lines of two memory cells located in the first and second rows and the first column. Leakage current paths can occur from bit lines to memory cells in the first row and first column, potentially affecting reads from selected memory cells in the second row and first column. Additional leakage current paths can also form due to voltage differences in the cascaded transistors between the source and drain, potentially extending from the first row and first column of memory cells to the first row and second column. This additional bit line leakage leads to decreased read margins and read speeds, resulting in performance degradation. Therefore, it is necessary to reduce the leakage current that may originate from unselected memory cells.

[0071] In this disclosure, novel sensing structures and schemes can be used to provide several advantages over current technologies. For example, instead of each bit line having its own bit line transistor, a common bit line transistor can be formed, connecting multiple columns together. The common bit line transistor can be formed to connect to multiple cascaded transistors, which are then connected to the individual bit lines. At a common point where the bit line transistor is connected to the multiple cascaded transistors, another transistor that can be connected to ground can be formed, allowing leakage current to flow to ground. Because the cascaded transistors connected to the common bit line transistor are all turned on simultaneously, and there is no voltage difference between the source and drain of the cascaded transistors in the selected memory cell (the memory cell located in the first row and second column in the above example), leakage current can be advantageously reduced and / or eliminated, and the memory device can operate more reliably.

[0072] Figure 1 This illustration shows a schematic block diagram of a memory device 100 according to some embodiments. The memory device is an IC device. In at least one embodiment, the memory device is a separate IC device. In some embodiments, the memory device is part of a larger IC device that includes circuitry other than the memory device itself for other functions.

[0073] The memory device 100 includes at least one memory cell 103 and a controller (also referred to as "control circuitry") 102 coupled to control the operation of the memory cell 103. Figure 1 In an exemplary configuration, memory device 100 includes a plurality of memory cells 103 arranged in a plurality of columns and rows in memory array 104. Memory device 100 further includes a plurality of word lines WL[0] to WL[m] extending along the rows of memory cells 103, a plurality of source lines SL[0] to SL[m] extending along the rows, and a plurality of bit lines (also referred to as “data lines”) BL[0] to BL[k) extending along the columns. Each memory cell 103 is connected to controller 102 via at least one word line, at least one source line, and at least one bit line. Examples of word lines include, but are not limited to, read word lines for transmitting the address of a memory cell 103 to be read, write word lines for transmitting the address of a memory cell 103 to be written, etc. In at least one embodiment, a set of word lines is used as both read word lines and write word lines. Examples of bit lines include read bit lines for transmitting data read from memory cell 103 represented by a corresponding word line, write bit lines for transmitting data to be written to memory cell 103 represented by a corresponding word line, etc. In at least one embodiment, a set of bit lines is used as both read bit lines and write bit lines. In one or more embodiments, each memory cell 103 is coupled to a pair of bit lines called bit lines and bit line bars. Word lines are generally referred to herein as WL, source lines are generally referred to herein as SL, and bit lines are generally referred to herein as BL. Various numbers of word lines and / or bit lines and / or source lines in memory device 100 are within the scope of various embodiments. In at least one embodiment, the source lines SL are arranged in columns, rather than as... Figure 1 The arrangement shown is in rows. In at least one embodiment, the source line SL is omitted.

[0074] exist Figure 1 In the exemplary configuration, controller 102 includes word line driver 112, source line driver 114, bit line driver 116, and sense amplifier (SA) 118 for performing at least one of a read operation or a write operation. In at least one embodiment, controller 102 further includes one or more clock generators for providing clock signals to various elements of memory device 100, one or more input / output (I / O) circuits for exchanging data with external devices, and / or one or more controllers for controlling various operations in memory device 100. In at least one embodiment, source line driver 114 is omitted.

[0075] The word line driver 112 is coupled to the memory array 104 via word lines WL. The word line driver 112 is used to decode the row address of the memory cell 103 selected for access in a read or write operation. The word line driver 112 is used to supply voltage to the selected word line WL corresponding to the decoded row address, and to supply different voltages to the other unselected word lines WL.

[0076] Source line driver 114 is coupled to memory array 104 via source line SL. Source line driver 114 is used to supply voltage to selected source line SL corresponding to selected memory cell 103, and to supply different voltages to other unselected source lines SL.

[0077] Bit line driver 116 (also referred to as a "write driver") is coupled to memory array 104 via bit line BL. Bit line driver 116 is used to decode the column address of memory cell 103 selected for access in a read or write operation. Bit line driver 116 supplies voltage to the selected bit line BL corresponding to the decoded column address and supplies different voltages to other unselected bit lines BL. In a write operation, bit line driver 116 supplies write voltage (also referred to as "program voltage") to the selected bit line BL. In a read operation, bit line driver 116 supplies read voltage to the selected bit line BL.

[0078] SA 118 is coupled to memory array 104 via bit line BL. During a read operation, SA 118 is used to sense data read by the self-accessing memory cell 103 and retrieved via the corresponding bit line BL. The described memory device configuration is exemplary, and other memory device configurations are within the scope of various embodiments. In at least one embodiment, memory device 100 is an NVM, and memory cell 103 is an OTP memory cell. Other types of memory are within the scope of various embodiments. Exemplary memory types of memory device 100 include, but are not limited to, fuses, antifuse, magnetoresistive random-access memory (MRAM), etc.

[0079] The transistors shown in this disclosure are of a specific type (n-type or p-type), but the embodiments are not limited to this. The transistor can be any suitable type of transistor, including but not limited to metal oxide semiconductor field-effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, P-channel metal-oxide semiconductor (PMOS), N-channel metal-oxide semiconductor (NMOS), bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field-effect transistors (PFETs / NFETs), fin field-effect transistors (FinFETs), planar MOS transistors with convex origin / drain, nanosheet FETs, nanowire FETs, etc.

[0080] In some embodiments, the controller 102 includes a word line driver 112, a source line driver 114, a bit line driver 116, and a sense amplifier 118, as well as a plurality of other circuits, such as one or more multiplexers, one or more pass gate transistors (or pass transistors), and / or one or more level offsets, wherein each of these other circuits may include p-type or n-type transistors. The multiplexer, pass gate transistor, sense amplifier 118, and level offsets may typically be disposed on opposite sides of the word line driver 112, source line driver 114, and / or bit line driver 116. The controller 102 may be disposed on a substrate and connected to the memory array 104 via one or more bit lines BL, one or more source lines SL, and / or one or more word lines WL that may be disposed in one or more metallization layers and / or one or more via structures.

[0081] Figure 2 Description of memory cell 103 according to some embodiments ( Figure 1 Indicative configuration of ). In Figure 2In this embodiment, memory cell 103 includes an electric fuse cell configured as 2T1R, for example, a fuse resistor 202 connected in series with a stack of transistors including a cascodegate (CG) (or control gate) transistor 204a and an access transistor 204b. The CG transistor 204a can be provided to reduce voltage stress on both the access transistor 204b and the CG transistor 204b. However, it should be understood that memory cell 103 can use any of a variety of other fuse configurations exhibiting fuse characteristics, such as 1T1R, 2-diode-1-resistor (2D1R) configurations, many-transistors-one-resistor (manyT1R) configurations, etc., while remaining within the scope of this disclosure. Furthermore, the described techniques are not limited to electric fuse memory devices, but can be applied to any memory using transistors as selectors and storage elements such as resistors or capacitors.

[0082] According to various embodiments of this disclosure, the fuse resistor 202 is formed of one or more metal structures. For example, the fuse resistor 202 may be one of several interconnect structures disposed in one of several metallization layers above or below the CG transistor 204a and / or the access transistor 204b. Specifically, both the CG transistor 204a and the access transistor 204b are formed on the main surface of the semiconductor substrate, a process sometimes referred to as part of the front-end-of-line (FEOL) process. During the FEOL process, several metallization layers are typically formed, each metallization layer including several interconnect (e.g., metal) structures, a process sometimes referred to as part of the back-end-of-line (BEOL) process. During the BEOL process, or between the FEOL and BEOL processes, there may be processing steps that form local electrical connections between transistors and metal gate contacts during the MEOL process.

[0083] Since the fuse resistor 202 (of memory cell 103) is a metallic structure, it can exhibit, for example, the initial resistance value (or resistivity) manufactured. To program memory cell 103, both CG transistor 204a and access transistor 204b (if embodied as an n-type transistor) are turned on by applying a signal corresponding to a logic high state (e.g., voltage) via the CG line (CGL) or word line WL to the gate of access transistor 204b. Simultaneously or subsequently, a sufficiently high (e.g., voltage) signal is applied to one end of fuse resistor 202 via bit line BL. With CG transistor 204a and access transistor 204b turned on to provide a (e.g., program) path from bit line BL through fuse resistor 202, CG transistor 204a, and access transistor 204b to source line SL, this high-voltage signal can burn out a portion of the corresponding metal structure (fuse resistor 202), thereby transitioning fuse resistor 202 from a first state (e.g., short-circuited) to a second state (e.g., open-circuited). Therefore, memory cell 103 can irreversibly transition from a first logic state (e.g., logic 1) to a second logic state (e.g., logic 0), which can be sensed by applying a relatively low voltage signal to bit line BL and turning on CG transistor 204a and access transistor 204b to provide (e.g., read) a path.

[0084] Figure 3A The illustration shows an exemplary memory device 300 according to some embodiments. The memory device 300 includes CG transistors 322, 324…322n, 324n, 342, 344…342n, 344n (e.g., Figure 2 CG transistor 204a), shared gate (SG) transistors 302, 304…302n, 304n, and sense amplifier 310 (e.g., Figure 1 The memory device 300 includes a sense amplifier 118, control transistors 312…312n, and sense enable transistors (or multiplexer transistors) 382…382n. The memory device 300 may also include multiple rows of memory cells. Furthermore, the memory device 300 is provided with multiple signal lines carrying control signals, such as word lines WL0, WL1, bit lines BL0, BL1…BLn and BLm, and cascode gate (CG) lines CG0, CG1…CGn, CGm. Although only a certain number of signal lines are shown, there may be more or fewer signal lines. Furthermore, although the memory device 300 is shown as having… Figure 3AThe embodiment may be a circuit, but the embodiments are not limited thereto, and the described techniques can be applied to any memory circuit that uses a sense amplifier. For example, as described above, the memory cell may include an electric fuse, an antifuse, a metal-insulator-metal (MIM) memory, other one-time programmable (OTP) memory, dynamic random access memory (DRAM), and any other memory that uses resistors or capacitors as storage cells.

[0085] Fuse 362, 364…362n, 364n, CG transistor 322, 324…322n, 324n, and WL transistor 332…332n (e.g., Figure 2 The access transistor 204b can form multiple memory cells along bit lines BL0 and BL1. Fuse 362, CG transistor 322, and WL transistor 332 can form the first memory cell M1. Fuse 364, CG transistor 324, and WL transistor 332 can form the second memory cell M2. Fuse 372, CG transistor 342, and WL transistor 352 can form the third memory cell M3. Fuse 374, CG transistor 344, and WL transistor 352 can form the fourth memory cell M4. Fuses 372, 374…372n, 374n, CG transistors 342, 344…342n, 344n, and word line transistors 352…352n can form multiple memory cells along bit lines BLn and BLm. Fuse 362n, CG transistor 322n, and WL transistor 332n can form the fifth memory cell M5. Fuse 364n, CG transistor 324n, and WL transistor 332n can form a sixth memory cell M6. Fuse 372n, CG transistor 342n, and WL transistor 352n can form a seventh memory cell M7. Fuse 374n, CG transistor 344n, and WL transistor 352n can form an eighth memory cell M8. As described above, although this disclosure discusses memory cells with a 2T1R configuration of fuse (e.g., electric fuse) memory cells, the embodiments are not limited thereto, and the disclosed techniques can be applied to any memory device including a sense amplifier to detect the stored logic state in the memory cell.

[0086] The multiplexer transistors 382-382n can be controlled by multiplexer control signals provided on multiplexer control lines 392-392n. Although not shown, the controller (e.g., Figure 1The controller 102 may include a decoder that can be used to provide control signals to multiplexer control lines 392-392n. Each of the SG transistors 302-302n and 304-304n can be controlled by the same gate control signal provided on control line 390. Furthermore, the controller may include a decoder that can provide control signals to control line 390.

[0087] Each of the first to eighth memory cells M1 to M8 may operate similarly to memory cell 103. In some embodiments, a selector for a particular cell may include a CG transistor (e.g., CG transistor 204a) stacked with a WL transistor (e.g., WL transistor 204b) to divide the voltage at one end of fuse 362. For half-selected cases (e.g., selecting a row or column), this helps reduce voltage stress on the CG and WL transistors. For example, for the first memory cell, to program fuse 362, a control signal (e.g., a logic high signal) may be provided to CG transistor 322 so that when WL0 is turned on, a user can program (or write to) or read from fuse 362.

[0088] Figure 3B Description of the read operation according to some embodiments Figure 3A An example memory device 300. Although described with reference to memory cell reading including fuse 372. Figure 3A The embodiments are not limited thereto; this technology can be applied when reading from any other memory cell within the memory device 300. Furthermore, for convenience, Figure 3B The element symbols for certain logic signal lines are shown in parentheses by the logic signals provided to those signal lines.

[0089] When a read is made from memory cell M3, several signal lines can be activated (e.g., a logic high signal is provided). For example, after bit line BL0 has been pre-charged to a predetermined level, multiplexer control line 392 can receive a logic high signal, enabling the sensing of memory cells connected to two columns of bits BL0 and BL1. Multiplexer control line 392 and control line 390 can receive logic high signals. Control line 394 can receive a logic low signal. Word line WL1 can receive a logic high signal. Thus, a current path Icell from bit line BL0 to ground can be formed. If fuse 372 in memory cell M3 is not burned (e.g., short-circuited), the charge from bit line BL0 will flow to ground via fuse 372, CG transistor 342, and WL transistor 352. When the sense amplifier 310 senses bit line BL0, it senses or detects the absence of charge on bit line BL0 and provides a logic low signal back to the controller, indicating that memory cell M3 has logic 0. If the fuse 372 of memory cell M3 has burned out (e.g., open circuit), the charge on bit line BL0 will remain, and the sense amplifier 310 can detect that memory cell M3 has logic 1.

[0090] During a read operation of memory cell M3 with logic 1, memory cell M1 can be half-selected because a control signal can be activated on the CG line CG0 but not the word line WL0. However, since both the source and drain of CG transistor 324 are high, no leakage current path is formed in M2, and no voltage difference forms a current. For example, node N1, connecting CG transistor 322, CG transistor 324, and WL transistor 332, has a high voltage level, and node N2, connecting fuse 364 and CG transistor 324, also has a high voltage level. Furthermore, since CG transistor 324 has a gate terminal set to logic 0 and the voltage difference between its source and drain terminals is essentially 0 V, there is no leakage current on CG transistor 324. Therefore, leakage current is reduced.

[0091] Therefore, bit line BL leakage in memory cell M2 can be reduced and / or eliminated. In some embodiments, read margin and read speed can be improved. Furthermore, by using a common transistor or a set of common transistors to select all columns connected to the same multiplexer transistor, the memory cell area can be reduced without being affected by the decrease in read margin.

[0092] Figure 4 This describes an exemplary memory device 400 according to some embodiments. The memory device 400 is similar to... Figure 3AThe memory device 300 has four columns (e.g., corresponding to bit lines BL0, BL1, BL2, and BL3) connected to a word line transistor 432, SG transistors 402, 404, 406, and 408, and a control transistor 412. Similar descriptions are omitted for simplicity and clarity.

[0093] For example, memory device 400 has multiple memory cells M5, M6, M7, M8, M9, M10, M11, and M12. Memory cells M5 to M8 are connected to a WL transistor 432, which is selected by word line WL0, and memory cells M9 to M12 are connected to a WL transistor 452, which is selected by word line WL1. Furthermore, bit lines BL0 to BL3 are connected to SG transistors 402 to 408, which have gate terminals connected together, giving them a common gate terminal. This common gate terminal can receive a control signal that activates all SG transistors 402 to 408.

[0094] During a read operation of memory cell M9, word line WL1 is activated, but word line WL0 is not activated. Since the voltage difference between node N3 and node N4 is essentially 0 V, leakage current from bit line BL3 to memory cell M6 can be reduced or avoided.

[0095] Although memory device 400 shows each WL transistor connected to four memory cells (e.g., WL transistor 432 connected to memory cells M5-M8, and WL transistor 452 connected to memory cells M9-M12), the embodiment is not limited to this, and memory device 400 can have more configurations. For example, in another configuration, each WL transistor can be connected to a group of M memory cells and N groups of M memory cells each, for a total of M×N memory cells per row, where each of M and N is a positive integer. For example, in a row of 32 memory cells used for sensing by a sense amplifier, there may be 8 groups of memory cells, each with 4 memory cells. Therefore, multiple configurations of M and N are conceivable.

[0096] Figure 5 This describes an exemplary memory device 500 including a hybrid sensing structure according to some embodiments. The exemplary memory device 500 includes a first sensing structure 500a and a second sensing structure 500b. The first sensing structure 500a includes a structure similar to [see reference 1] Figures 3A to 4The same sensing structure is described. For example, sensing structure 500a may include SG transistor 502 (e.g., SG transistors 302, 402), SG transistor 504 (e.g., SG transistor 504), control transistor 512 (e.g., control transistor 312), and multiplexer transistor 582 (e.g., multiplexer transistor 382). Furthermore, SG transistors 502 and 504 may be selected by control line 590 (e.g., control line 390), control transistor 512 may be selected by control line 594 (e.g., control line 394), and multiplexer transistor 582 may be selected by multiplexer control line 592 (e.g., multiplexer control line 392). Therefore, similar descriptions are omitted.

[0097] The second sensing structure 500b may include a typical sensing structure in which each bit line BLn and BLm are connected in series to two stacked transistors for column access to sense memory cells connected to bit lines BLn and BLm. For example, bit line BLn may be connected to a first stacked transistor 522n and a second stacked transistor 524n, such that when the two transistors are turned on via a control line 592n with an active high signal and a cascaded gate line CGn, the voltage on bit line BLn can be sensed by sensing amplifier 510. Another set of stacked transistors 532n and 534n may be provided to ground, such that when the control signal 544 and the cascaded gate line CGn are active high, leakage current can flow to ground. Bit line BLm may be connected to a third stacked transistor 522m and a fourth stacked transistor 524m, such that when the two transistors are turned on via a control line 592m with an active high signal and a cascaded gate line CGm, the voltage on bit line BLm can be sensed by sensing amplifier 510. Another set of stacked transistors 532m and 534m can be grounded, so that when the control signal 546 and the cascaded gate line CGm are actively high, the leakage current can flow to ground.

[0098] Therefore, a memory device 500 with a hybrid sensing structure can be provided according to embodiments and design requirements. In some embodiments, sensing structures 500a and 500b can be used alternately in each group of memory devices. In some other embodiments, sensing structure 500a can be used in the first X columns, and sensing structure 500b can be used in the Y columns after the X columns, where X and Y are positive integers. Furthermore, any combination of sensing structures 500a and 500b can be used.

[0099] Figure 6A flowchart illustrating an exemplary method 600 for operating a memory device according to some embodiments is provided. Method 600 can be used for reading from a memory cell having a wide read margin. For example, at least some of the operations described in method 600 are used to operate memory devices 100, 300, 400, or 500. It should be noted that method 600 is merely an example and is not intended to limit the scope of this disclosure. Therefore, it should be understood that... Figure 6 Additional operations are provided before, during, and after Method 600, and some other operations are only briefly described in this document.

[0100] In summary, method 600 begins at operation 602: during a read operation of the first memory cell, a first word line connected to both the first and second memory cells is activated. Method 600 proceeds to operation 604: a first control gate line connected to the first memory cell is activated. Method 600 proceeds to operation 606: a multiplexer control line connected to a multiplexer transistor connected to a sense amplifier is activated. Method 600 proceeds to operation 608: a common gate signal line is activated, connected to the gate of the first common gate transistor connected to the first memory cell and to the gate of the second common gate transistor connected to the second memory cell.

[0101] Referring to operation 602, in the first memory cell (e.g., Figure 3B During a read operation of memory cell M3, a first word line (e.g., word line WL1) connected to both the first and second memory cells (e.g., memory cell M4) is activated by a controller (e.g., controller 102). A word line transistor (e.g., WL transistor 352) may be shared by both the first and second memory cells.

[0102] Referring to operation 604, a first control gate line (e.g., cascaded gate line CG0) can be activated. The first control gate line may extend in the same direction as the bit line.

[0103] Referring to operation 606, a multiplexer control line (e.g., multiplexer control line 392) connected to a multiplexer transistor (e.g., multiplexer transistor 382) can be activated. The multiplexer transistor can be connected to a sense amplifier (e.g., sense amplifier 310). The multiplexer control line can control whether the sense amplifier can sense current from the first memory cell during a read operation.

[0104] Referring to operation 608, a common gate signal line (e.g., control line 390) can be activated. The common gate signal can be connected to the gate terminal of a first common gate transistor (e.g., common gate transistor 302) connected to a first memory cell and to the gate terminal of a second common gate transistor connected to a second memory cell.

[0105] Therefore, during a read operation of a selected memory cell, leakage current from unselected memory cells can be reduced and / or eliminated. Furthermore, the sensing structure connected to the memory cell can have a reduced area while still maintaining good read margins, thereby optimizing area without sacrificing reliability and performance. The disclosed technique can be applied to various memory configurations with various sensing structures, enabling multiple memory cells on the same row to be activated by a single word line.

[0106] In one embodiment of this disclosure, a memory device is disclosed. The memory device includes: a plurality of memory cells including a first memory cell and a second memory cell; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first word line connected to the first and second memory cells; a first control transistor connected to the first bit line; a second control transistor connected to the second bit line; a first multiplexer transistor commonly connected to the first and second control transistors; and a sense amplifier connected to the first multiplexer transistor.

[0107] In some embodiments, the first control transistor and the second control transistor each have a gate terminal connected to a common gate control line.

[0108] In some embodiments, the memory device further includes a controller for: activating the first word line; activating a common gate control line; and activating a multiplexer control line connected to the gate terminal of the first multiplexer transistor during a read operation of the first memory cell connected to the first word line.

[0109] In some embodiments, the memory device further includes a third control transistor connected to the first control transistor, the second control transistor, and ground.

[0110] In some embodiments, during a read operation, the controller is further configured to disable the control line connected to the gate of the third control transistor.

[0111] In some embodiments, the memory device further includes a second word line connected to a third memory cell and a fourth memory cell of the memory unit.

[0112] In some embodiments, the controller is configured to disable the second character line during a read operation.

[0113] In some embodiments, each memory cell includes a storage unit, which includes a resistor or a capacitor.

[0114] In some embodiments, a first word line is connected to M memory cells, and a sense amplifier is connected to N multiplexer transistors, the multiplexer transistors including a first multiplexer transistor, wherein M and N are positive integers.

[0115] In some embodiments, the number of multiple control transistors and multiple bit lines is equal to M, the control transistors include a first control transistor and a second control transistor and are connected to a common gate line, and the bit lines include a first bit line and a second bit line and are connected to a multiplexer transistor.

[0116] In another embodiment of this disclosure, a method for operating a memory device is disclosed. The method includes the following steps: during a read operation of a first memory cell, activating a first word line connected to both the first and second memory cells; activating a first control gate line connected to the first memory cell; activating a multiplexer control line connected to a multiplexer transistor connected to a sense amplifier; and activating a common gate signal line connected to the gate terminal of a first common gate transistor connected to the first memory cell and to the gate terminal of a second common gate transistor connected to the second memory cell.

[0117] In some embodiments, the method further includes the step of: disabling a second word line having a drain terminal and a source terminal, the drain terminal being connected to a first control gate transistor and a second control gate transistor, and the source terminal being connected to ground.

[0118] In some embodiments, the method further includes the step of: disabling a second control gate line connected to a second memory cell.

[0119] In some embodiments, the memory cell includes a storage cell, which includes a resistor or a capacitor.

[0120] In some embodiments, the first common gate transistor and the second common gate transistor, the multiplexer transistor and the control transistor are interconnected at the node.

[0121] In another embodiment of this disclosure, a memory system is disclosed. The memory system includes: a plurality of memory cells, including a first memory cell and a second memory cell; a sense amplifier connected to the plurality of memory cells via a plurality of bit lines; and a controller connected to the plurality of memory cells. The controller is configured to: during a read operation of the first memory cell, activate a first word line connected to the first memory cell and the second memory cell; activate a first control gate line connected to the first memory cell; activate a multiplexer control line connected to a multiplexer transistor connected to the sense amplifier; and activate a common gate signal line connected to the gate terminal of a first common gate transistor connected to the first memory cell and connected to the gate terminal of a second common gate transistor connected to the second memory cell.

[0122] In some embodiments, the controller is further configured to disable a second word line having a drain terminal and a source terminal, the drain terminal being connected to a first control gate transistor and a second control gate transistor, and the source terminal being connected to ground.

[0123] In some embodiments, the controller is further configured to disable the second control gate line connected to the second memory cell.

[0124] In some embodiments, each memory cell includes a storage unit, and the storage unit includes a resistor or a capacitor.

[0125] In some embodiments, the first common gate transistor and the second common gate transistor, the multiplexer transistor and the control transistor are interconnected at the node.

[0126] As used herein, the terms “about” and “approximately” generally refer to plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0127] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, characterized in that, Include: Multiple memory units, including a first memory unit and a second memory unit; A first bit line is connected to the first memory cell; A second bit line is connected to the second memory cell; A first character line is connected to the first memory cell and the second memory cell; A first control transistor is connected to the first bit line; A second control transistor is connected to the second bit line; A first multiplexer transistor, which is connected to both the first control transistor and the second control transistor; and A sensing amplifier is connected to the first multiplexer transistor. The first memory cell includes a first transistor, which is connected between the second memory cell and the first bit line. The memory device further includes a third control transistor. One end of the third control transistor is directly connected at a node to each of the first control transistor, the second control transistor, and the first multiplexer transistor. The other end of the third control transistor is connected to ground.

2. The memory device as claimed in claim 1, characterized in that, The first control transistor and the second control transistor each have a gate terminal connected to a common gate control line.

3. The memory device as claimed in claim 2, characterized in that, It further includes a controller, which, during a read operation of the first memory cell connected to the first word line, is used to: Start the first character line; Start the common gate control line; and Start a multiplexer control line connected to a gate terminal of the first multiplexer transistor.

4. The memory device as claimed in claim 3, characterized in that, The first memory cell and the second memory cell share a word line transistor connected to the first word line, and one end of the word line transistor is connected to ground.

5. The memory device as claimed in claim 4, characterized in that, During the read operation, the controller is further used to disable a control line connected to a gate terminal of the third control transistor.

6. The memory device as claimed in claim 5, characterized in that, It further includes a second character line that connects to a third memory cell and a fourth memory cell of the plurality of memory cells.

7. The memory device as claimed in claim 6, characterized in that, The controller is used to disable the second character line during the read operation.

8. The memory device as claimed in claim 1, characterized in that, Each of the plurality of memory cells includes a storage unit, which includes a resistor or a capacitor.

9. The memory device as claimed in claim 1, characterized in that, The first character line is connected to M of the plurality of memory cells, and the sense amplifier is connected to N multiplexer transistors, the N multiplexer transistors including the first multiplexer transistor, where M and N are positive integers.

10. The memory device as claimed in claim 9, characterized in that, The plurality of control transistors and the plurality of bit lines are of a number equal to M. The plurality of control transistors include the first control transistor and the second control transistor and are connected to a common gate line. The plurality of bit lines include the first bit line and the second bit line and are connected to the multiplexer transistor.

11. A method for operating a memory device, characterized in that, Includes the following steps: During a read operation of a first memory cell, a first word line connected to the first memory cell and a second memory cell is activated; Start a first control gate line connected to the first memory cell; A multiplexer control line is activated, connected to a multiplexer transistor, which is connected to a sense amplifier; and A common gate signal line is activated, which is connected to a gate terminal of a first common gate transistor and a gate terminal of a second common gate transistor. The first common gate transistor is connected to the first memory cell, and the second common gate transistor is connected to the second memory cell. The common gate signal line is further connected to a gate terminal of a third common gate transistor. One end of a control transistor is directly connected at a node to each of the first common gate transistor, the second common gate transistor, and the third common gate transistor. The other end of the control transistor is connected to ground.

12. The method as described in claim 11, characterized in that, The method further includes the following steps: disabling a second word line connected to a second word line transistor shared by a third memory cell and a fourth memory cell, wherein the second word line transistor has a drain terminal and a source terminal, the drain terminal being connected to a first control gate transistor of the third memory cell and a second control gate transistor of the fourth memory cell, and the source terminal being connected to ground.

13. The method as described in claim 11, characterized in that, It further includes the following step: disabling a second control gate line connected to the second memory cell.

14. The method as described in claim 11, characterized in that, The memory cell includes a storage unit, which includes a resistor or a capacitor.

15. The method as described in claim 11, characterized in that, The first common gate transistor, the second common gate transistor, the multiplexer transistor, and the control transistor are interconnected at the node.

16. A memory system, characterized in that, Include: Multiple memory units, including a first memory unit and a second memory unit; A sense amplifier connected to the plurality of memory cells via a plurality of bit lines; and A controller is connected to the plurality of memory units, wherein the controller is used to: During a read operation of the first memory cell, a first word line is activated, which is connected to the first memory cell and the second memory cell; Start a first control gate line connected to the first memory cell; Start a multiplexer control line connected to a multiplexer transistor, which is connected to the sense amplifier; and A common gate signal line is activated, which is connected to a gate terminal of a first common gate transistor and a gate terminal of a second common gate transistor. The first common gate transistor is connected to the first memory cell, and the second common gate transistor is connected to the second memory cell. The plurality of bit lines includes a first bit line. A first stacked transistor and a second stacked transistor are connected in series between the first bit line and the sense amplifier. A third stacked transistor and a fourth stacked transistor are connected in series between the first element line and ground. Each of the gate terminals of the second stacked transistor and the fourth stacked transistor is connected to a cascaded gate line.

17. The memory system as claimed in claim 16, characterized in that, The controller is further used to disable a second word line connected to a second word line transistor shared by a third memory cell and a fourth memory cell. The second word line transistor has a drain terminal and a source terminal. The drain terminal is connected to a first control gate transistor of the third memory cell and a second control gate transistor of the fourth memory cell, and the source terminal is connected to ground.

18. The memory system as claimed in claim 16, characterized in that, The controller is further used to disable a second control gate line connected to the second memory cell.

19. The memory system as claimed in claim 16, characterized in that, Each of the plurality of memory cells includes a storage unit, which includes a resistor or a capacitor.

20. The memory system as claimed in claim 16, characterized in that, The first common gate transistor, the second common gate transistor, the multiplexer transistor, and a control transistor are interconnected at a node.

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