Semiconductor memory device

Abstract

A semiconductor memory device (100) includes a plurality of memory banks (10) having data storage units (20) and error correction code storage units (30), an error correction code generation unit (40), an error correction unit (50), a row counter (61) that determines a row address as a refresh target, a bank counter (63) that determines a bank address as an error correction target, and a column counter (62) that determines a column address as an error correction target. When a refresh command is received, the error correction unit performs error correction processing on data of an error correction target address determined based on the row counter, the bank counter, and the column counter.

Description

Technical Field

[0001] This disclosure relates to a semiconductor memory device. Background Technology

[0002] As a semiconductor memory device, for example, DRAM (Dynamic Random Access Memory) with ECC (Error Check and Correct) functionality can be used and autonomously performs data error correction processing. However, in such ECC-compatible DRAM, error correction is only performed on the data read when a request is received from a SoC (System on a Chip) or similar device, and the corrected read data is not written back to the DRAM; therefore, the error still exists in the DRAM.

[0003] In the semiconductor memory device of Patent Document 1 below, error correction processing is performed when the semiconductor memory device is refreshed, and the error-corrected data is written back to the semiconductor memory device, thereby reducing errors in the semiconductor memory device and suppressing the decrease in data reliability.

[0004] Existing technical documents [Patent Documents] Patent Document 1: JP-2020-71589-A Summary of the Invention

[0005] Some semiconductor memory devices have multiple data storage areas (hereinafter also referred to as "banks") to suppress performance degradation. However, Patent Document 1 does not describe refresh and error correction processing when the semiconductor memory device includes multiple banks. Therefore, Patent Document 1, specifically, does not describe the two features of refreshing and error correction processing on all banks or only on specific portions of the multiple banks. As mentioned above, refresh and error correction processing for semiconductor memory devices with multiple banks has not been adequately studied in the past, and therefore there is room for improvement.

[0006] This disclosure can be implemented as follows.

[0007] According to one embodiment of this disclosure, a semiconductor memory device is provided. The semiconductor memory device is a semiconductor memory device with a refresh function, and the semiconductor memory device includes: a plurality of memory banks, each having a data storage unit for storing data and an error correction code storage unit for storing error correction codes corresponding to the data stored in the data storage unit; an error correction code generation unit for generating error correction codes; an error correction unit for performing error correction processing on the data using the error correction codes; a row counter for determining a row address as a refresh target; a memory bank counter for determining a memory bank address as an error correction target; and a column counter for determining a column address as an error correction target, wherein: the error correction unit performs error correction processing on the data based on the error correction target addresses determined by the row counter, the memory bank counter, and the column counter when receiving a refresh instruction.

[0008] According to this feature of the semiconductor memory device, the semiconductor memory device includes multiple memory banks, and the error correction unit performs error correction processing on data based on the error correction target address determined by the row counter, the memory bank counter, and the column counter when it receives a refresh command. Therefore, it is possible to suppress the reliability degradation of data in a semiconductor memory device with multiple memory banks. Attached Figure Description

[0009] The above and other objects, features, and advantages of this disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. In the drawings: Figure 1 This is an explanatory diagram schematically showing the structure of the semiconductor memory device of this embodiment; Figure 2 It is an illustrative diagram that schematically shows the structure of a data storage unit; Figure 3 This is a flowchart showing the ABR process; Figure 4 This is a flowchart of the display refresh and error correction process; Figure 5 This is a flowchart showing the counting operation; Figure 6 This is a flowchart showing the PBR process; Figure 7 This is an explanatory diagram showing the first half of a process in which ABR and PBR processes are executed alternately; Figure 8 This is an explanatory diagram showing the latter half of the process in which ABR and PBR processes are executed alternately; Figure 9A It is displayed Figure 7 A diagram illustrating the corrected error areas after step S515 is completed; Figure 9B It is displayed Figure 7 A diagram illustrating the corrected error areas after step S517 is completed; Figure 9C It is displayed Figure 8 A diagram illustrating the corrected error areas after step S533; and Figure 9D It is displayed Figure 8 The diagram illustrates the corrected error areas after step S551 is completed. Detailed Implementation

[0010] A. Example: like Figure 1 As shown, the semiconductor memory device 100 of this embodiment includes a plurality of memory banks 10, an error correction code generation unit 40, an error correction unit 50, and a counter 60. In this embodiment, each functional unit can be provided by hardware and interconnected via a bus 70. The semiconductor memory device 100 is, for example, DRAM, and reads and writes data in response to requests received from external devices such as a SoC. Furthermore, the semiconductor memory device 100 has a refresh function and autonomously recovers data. In addition, the semiconductor memory device 100 performs error correction processing on all memory banks 10 during refresh.

[0011] The multiple storage units 10 include a data storage unit 20 and an error correction code storage unit 30. The data storage unit 20 stores data to be read / written in response to a request received from an external device. The error correction code storage unit 30 stores error correction codes generated by the error correction code generation unit 40 based on the input data. In this embodiment, the data storage unit 20 and the error correction code storage unit 30 are composed of different storage units.

[0012] like Figure 2 As shown, in this embodiment, the data storage unit 20 includes a storage bank B0 and a storage bank B1. Each of the storage banks B0 and B1 includes a storage cell array 21, a row decoder 23, a column decoder 24, and a sense amplifier 25.

[0013] Memory cells B0 and B1 are connected to bus 26, and data is read from / written to the semiconductor memory device 100 via external devices through bus 26. Data is read from / written to the memory cell array 21 via sense amplifier 25. Bus 26 is connected to... Figure 1 The bus shown is 70.

[0014] The memory cell array 21 is constructed in the same way as a typical DRAM. More specifically, the memory cell array 21 is formed by arranging a plurality of 1-transistor 1-capacitor type memory cells 22 in a matrix. Word lines and bit lines (not shown) are connected to each memory cell 22.

[0015] Row decoder 23 activates any one of the multiple word lines in memory cell array 21 based on the row address. Column decoder 24 activates any one of the multiple bit lines in memory cell array 21 based on the column address. In this way, the memory cell 22 to be accessed is selected by the combination of word lines and bit lines activated by row decoder 23 and column decoder 24.

[0016] When data is written to data storage unit 20 Figure 1 The error correction code generation unit 40 generates error correction codes based on the written data. For example, Huffman code can be used as an error correction code.

[0017] When data is read from the data storage unit 20 to an external device and during a refresh, the error correction unit 50 uses the error correction code read from the error correction code storage unit 30 to correct errors in the data read by the readout amplifier 25. For example, by using Huffman code as described above for error correction processing, a 1-bit error in the read data can be corrected.

[0018] Counter 60 includes a row counter 61, a column counter 62, and a memory counter 63. Counter 60 performs a predetermined counting operation and determines the address of the data to be accessed based on the counter value indicated by counter 60. The counting operation of counter 60 will be described later.

[0019] The refresh and error correction processing of this embodiment will be described. In this embodiment, the semiconductor memory device 100 performs refresh and error correction processing upon receiving either an ALL Bank Refresh (hereinafter also referred to as "ABR") command or a Per Bank Refresh (hereinafter also referred to as "PBR") command issued from an external device. The external device sends an ABR command or a PBR command to the semiconductor memory device 100 to instruct the execution of refresh and error correction processing, regardless of the processing state of the semiconductor memory device 100. The ABR command and PBR command are issued on a page-by-page basis. A page refers to a memory cell 22 belonging to a common row address in a memory bank.

[0020] will describe Figure 3The ABR process is shown in the diagram. The ABR process is a process that refreshes and corrects errors in all of the multiple memory banks 10. In this embodiment, the semiconductor memory device 100 performs the ABR process upon receiving an ABR command from an external device. In this embodiment, the ABR command corresponds to a "first refresh command".

[0021] In the ABR process, all of the multiple memory banks 10 are designated as refresh target memory banks (in step S110). A refresh target memory bank is the memory bank on which a refresh is performed.

[0022] In step S120, the semiconductor memory device 100 determines the refresh target page, the error correction target memory, and the error correction target memory cell based on the row counter value Cr, the memory bank counter value Cb, and the column counter value Cc at the time the ABR command is issued. The refresh target page refers to the page in the refresh target memory where refresh is performed, and is specified by the row address defined by the row counter 61. The error correction target memory refers to the memory bank in which error correction is performed, and is specified by the memory bank address defined by the memory bank counter 63. The error correction target memory cell refers to the memory cell 22 in the error correction target memory where error correction is performed, and is specified by the column address defined by the column counter 62. In this embodiment, the error correction target memory and the error correction target memory cell correspond to the "error correction target address". The time of issuing the ABR command is not limited to the time of issuing the ABR command, but also includes, for example, the time when the semiconductor memory device 100 receives the ABR command.

[0023] In step S130, the semiconductor memory device 100 performs refresh and error correction processing. (Refer to...) Figure 4 Describe the detailed process of refresh and error correction handling.

[0024] exist Figure 4 In step S210, the semiconductor memory device 100 reads the data of the refresh target page in the refresh target memory into the readout amplifier 25.

[0025] In step S220, the semiconductor memory device 100 reads data corresponding to the bank address and column address from the sense amplifier 25 into the error correction unit 50, wherein the data corresponding to the bank address and column address is the data of the error correction target memory cell in the data read from the sense amplifier 25 of the error correction target memory bank.

[0026] In step S230, the error correction unit 50 corrects the data read through it. In this embodiment, Huffman code as described above is used for error correction.

[0027] In step S240, the error correction unit 50 writes the data from the error correction unit 50 back to the read amplifier 25 of the error correction target memory.

[0028] In step S250, the semiconductor memory device 100 writes the data from the read amplifier 25 of the refresh target memory back to the refresh target page. Afterwards, the refresh and error correction process ends.

[0029] like Figure 3 As shown, in the ABR process, counter 60 performs a predetermined counting operation (in step S140) each time an ABR command is issued. More specifically, in this embodiment, counter 60 performs the counting operation after the refresh and error correction processes are completed. (Refer to...) Figure 5 Describe the counting operation.

[0030] like Figure 5 As shown, in step S310, when the row counter value Cr is less than the row counter maximum value Crmax, the row counter 61 increments the row counter value Cr by 1 (in step S311), and the counting operation ends.

[0031] In step S310, when the row counter value Cr is equal to the row counter maximum value Crmax, the row counter 61 resets the row counter value Cr to 0 (in step S312).

[0032] In step S320, when the bank counter value Cb is less than the bank counter maximum value Cbmax, the bank counter 63 increments the bank counter value Cb by 1 (in step S321), and the counting operation ends. In other words, each time the row counter value Cr is reset from the row counter maximum value Crmax to 0, the bank counter 63 increments the bank counter value Cb by 1. More specifically, in this embodiment, when the row counter value Cr is reset from the row counter maximum value Crmax to 0, the bank counter 63 increments the bank counter value Cb by 1.

[0033] In step S320, when the memory counter value Cb is equal to the maximum value Cbmax of the memory counter, the memory counter 63 resets the memory counter value Cb to 0 (in step S322).

[0034] In step S330, when the column counter value Cc is less than the column counter maximum value Ccmax, column counter 62 increments the column counter value Cc by 1 (in step S331), and the counting operation ends. In other words, each time the bank counter value Cb is reset from the bank counter maximum value Cbmax to 0, column counter 62 increments the column counter value Cc by 1. More specifically, in this embodiment, while resetting the bank counter value Cb from the bank counter maximum value Cbmax to 0, column counter 62 increments the column counter value Cc by 1.

[0035] In step S330, when the column counter value Cc equals the column counter maximum value Ccmax, column counter 62 resets the column counter value Cc to 0 (in step S332). After this, the counting operation ends.

[0036] As described above, by performing an ABR process once, the data recorded on the refresh target page can be refreshed, and error correction processing can be performed on the data recorded in the error correction target storage unit. Furthermore, in response to ABR commands issued one after another from an external device, the ABR process is repeatedly executed until all counters 60 have cycled, thereby performing refresh and error correction processing on all data recorded in the data storage unit 20.

[0037] will describe Figure 6 The PBR process is illustrated. The PBR process is a process that performs refresh and error correction processing on one or more specified memory banks 10. In this embodiment, the semiconductor memory device 100 performs the PBR process upon receiving a PBR command from an external device. In this embodiment, the PBR command corresponds to a "second refresh command".

[0038] In the PBR process, the memory bank specified by the PBR command is designated as the refresh target memory bank and the error correction target memory bank. In step S410, memory bank B0 is designated as both the refresh target memory bank and the error correction target memory bank.

[0039] In step S420, the semiconductor memory device 100 determines the refresh target page and the error correction target memory cell based on the row counter value Cr and the column counter value Cc when the PBR command is issued. The time of issuing the PBR command is not limited to the time when the PBR command is issued, but also includes, for example, the time when the semiconductor memory device 100 receives the PBR command.

[0040] In step S430, the semiconductor memory device 100 performs refresh and error correction processing. The refresh and error correction processing in this step is the same as that in the ABR process described above.

[0041] After refreshing and correcting errors in memory bank B0, Figure 6 In the example, semiconductor memory device 100 receives a PBR command again from an external device. In this case, similar to step S410, the memory bank specified by the PBR command is designated as both the refresh target memory bank and the error correction target memory bank. In step S440, memory bank B1 is designated as both the refresh target memory bank and the error correction target memory bank.

[0042] In step S450, the semiconductor memory device 100 determines the refresh target page and the error correction target memory cell in the same manner as in step S420.

[0043] In step S460, the semiconductor memory device 100 performs refresh and error correction processing. The refresh and error correction processing in this step is the same as that in the ABR process described above.

[0044] like Figure 6 As shown, in the PBR process, counter 60 performs a predetermined counting operation for each PBR command issued to all specified memory banks (in step S470). More specifically, in this embodiment, counter 60 performs the counting operation after completing the refresh and error correction processing for all specified memory banks. The counting operation in the PBR process is the same as the counting operation in the ABR process, but the memory bank counter value Cb is not used when determining the error correction target address in the PBR process.

[0045] As described above, by performing a PBR process once, data recorded on the refresh target page of the specified memory can be refreshed, and error correction processing can be performed on data recorded in the error correction target memory unit. Furthermore, by repeatedly performing the PBR process in response to PBR commands issued one after another from an external device until the row counter 61 and column counter 62 have cycled once, refresh and error correction processing are performed on all data in the data storage unit 20.

[0046] Reference Figure 7 , Figure 8 and Figures 9A to 9D This describes a processing example when a PBR command is issued during ABR processing and a scenario where an ABR command is issued during PBR processing. It's important to note that although in Figure 7 and Figure 8 There are reset and increment steps, but for ease of illustration, these steps are represented only by extracting the operation performed when any one of the counters 60 cycles once. It is not a counting operation performed separately from the counting operations performed in the ABR or PBR processes.

[0047] In step S501, the semiconductor memory device 100 in Figure 9A ABR processing is performed on region MC01. When the processing of the final row address of region MC01 is completed, row counter 61 resets the row counter value Cr (in step S503), and memory counter 63 increments the memory counter value Cb (in step S505).

[0048] In step S507, the semiconductor memory device 100 performs ABR processing on region MC11. When the ABR processing is completed up to the final row address of region MC11, row counter 61 resets the row counter value Cr (in step S509), and the bank counter value Cb equals 1, which is the maximum bank counter value Cbmax, thereby resetting the bank counter value Cb by bank counter 63 (in step S511). Furthermore, since the bank counter value Cb is reset from the maximum bank counter value Cbmax to 0, column counter 62 increments the column counter value Cc (in step S513).

[0049] In step S515, ABR processing is performed on region MC02, but... Figure 9A In the example, the PBR command is issued before reaching the final row address of memory bank B0. In this process, memory banks B0 and B1 are specified in the PBR command.

[0050] Figure 9A The area where the error has been corrected is shown at the end of step S515. Figure 9A The profile area (hatchedarea) represents the area where an error correction process was performed.

[0051] In step S517, the semiconductor memory device 100 in Figure 9B PBR processing is performed on regions MC03 and MC13. PBR processing is performed alternately on regions MC03 and MC13.

[0052] Figure 9B The area where the error has been corrected is shown at the end of step S517.

[0053] The processes performed in steps S519 and S521 after the PBR processing of memory cell 22 at the final row address of region MC13 are the same as those in steps S503 and S505. In step S521, the bank counter 63 increments the bank counter value Cb, but the column counter value Cc does not change because the change is from 0 to 1.

[0054] In step S523, since the refresh target column has not changed since step S517, the semiconductor memory device 100 performs PBR processing on regions MC02 and MC12. Although ABR processing has already been performed on region MC02, there is no problem in performing error correction processing again on the same region.

[0055] In step S525, the semiconductor memory device 100 again performs PBR processing on regions MC03 and MC13. This is after the PBR processing of the memory cell 22 at the final row address of region MC13. Figure 8 The processing in steps S527 to S531 shown is... Figure 7 The processes in steps S509 to S513 shown are the same.

[0056] In step S533, the semiconductor memory device 100 in Figure 9C PBR processing is performed on regions MC04 and MC14, but Figure 9C In the example, the ABR command is issued before reaching the final row address of memory B1.

[0057] Figure 9C The corrected error area is shown at the end of step S533. Figure 9C The area with cross-hatching grid lines indicates an area that has undergone two error corrections.

[0058] In step S535, the semiconductor memory device 100 in Figure 9D ABR processing is performed on region MC05. The processing in steps S537 and S539, performed after the ABR processing of memory cell 22 at the final row address of region MC05, is similar to... Figure 7 The processes in steps S503 and S505 shown are the same.

[0059] In step S541, the semiconductor memory device 100 performs ABR processing on region MC14. Since PBR processing has already been performed on region MC14, the ABR processing in this step is a second error correction. Subsequently, the semiconductor memory device 100 performs ABR processing on region MC15 (in step S543). After the ABR processing of memory cell 22 at the final row address of region MC15, the processing in steps S545 to S549 is similar to... Figure 7 The processes shown in steps S509 to S513 are the same.

[0060] When the ABR processing of region MC06 is completed in step S551, no ABR command or PBR command is issued from the external device, and the processing is terminated. Figure 9DThis shows the area where error correction is completed after this process ends. For example... Figure 9D As shown, even when ABR and PBR processes are executed alternately, refresh and error correction processes can be performed without omissions while a refresh command is issued. If ABR commands are issued continuously after step S551, refresh and error correction processes can be performed on all data recorded in the data storage unit 20.

[0061] According to the semiconductor memory device 100 of the above embodiment, even in a semiconductor memory device 100 including multiple memory banks 10, error correction processing can be performed on all data recorded in the data storage unit 20 during refresh. Therefore, it is possible to suppress the degradation of data reliability in the semiconductor memory device 100 including multiple memory banks 10. Furthermore, even if ABR processing and PBR processing are performed alternately, refresh and error correction processing can be performed on all data without omission, thereby suppressing the deterioration of data reliability.

[0062] B. Other embodiments: (B1) In the above embodiment, the semiconductor memory device 100 includes a plurality of memory cells 10, which are memory cells B0 and memory cells B1, but this embodiment is not limited to this. The number of the plurality of memory cells 10 may be more than two.

[0063] (B2) In the above embodiment, the row counter 61, column counter 62, and memory counter 63 increment their counter values, but this embodiment is not limited to this. For example, the row counter 61, column counter 62, and memory counter 63 can decrement their counter values.

[0064] (B3) In the above embodiment, the counting operation of counter 60 is performed after the refresh and error correction processing is completed. However, this embodiment is not limited to this feature. For example, the counting operation of counter 60 may be performed after the refresh command is issued or after the correction data is written back.

[0065] (B4) In the above embodiment, while resetting the row counter value Cr from the row counter maximum value Crmax to 0, the memory counter 63 increments the memory counter value Cb by 1. However, this embodiment is not limited to this feature. For example, the memory counter 63 may increment the memory counter value Cb by 1 after the row counter value Cr is reset from the row counter maximum value Crmax to 0.

[0066] (B5) In the above embodiment, while resetting the bank counter value Cb from the maximum bank counter value Cbmax to 0, the column counter 62 increments the column counter value Cc by 1. However, this embodiment is not limited to this feature. For example, the column counter 62 may increment the column counter value Cc by 1 after resetting the bank counter value Cb from the maximum bank counter value Cbmax to 0.

[0067] This disclosure should not be limited to the above embodiments, and various other embodiments can be implemented without departing from the scope of this disclosure. For example, the technical features corresponding to the forms described in the inventive summary in each embodiment can be used to solve some or all of the above problems, or to provide one of the above effects. To achieve some or all of them, appropriate substitutions or combinations can be made. In addition, some technical features can be appropriately omitted.

[0068] The controllers and methods described in this disclosure can be implemented by a special-purpose computer created by configuring memory and a processor programmed to perform one or more specific functions embodied in a computer program. Alternatively, the controllers and methods described in this disclosure can be implemented by a special-purpose computer created by configuring a processor provided by one or more special-purpose hardware logic circuits. Alternatively, the controllers and methods described in this disclosure can be implemented by one or more special-purpose computers created by a combination of a processor configured with memory and a processor programmed to perform one or more specific functions and a processor provided by one or more hardware logic circuits. The computer program can be stored as instructions executable by the computer in a tangible, non-transitory computer-readable medium.

[0069] It should be noted that the processing of the flowcharts or diagrams in this application includes sections (also called steps), each section being, for example, S110. Furthermore, each section can be divided into several sub-sections, and several sections can be combined into a single section. Additionally, each such configured section can also be referred to as an apparatus, module, or device.

[0070] Although this disclosure has been described with reference to embodiments thereof, it should be understood that this disclosure is not limited to these embodiments and configurations. This disclosure is intended to cover various modifications and equivalent arrangements. Furthermore, various combinations and configurations, including other combinations and configurations with more, fewer, or only a single element, are also within the spirit and scope of this disclosure.

Claims

1. A semiconductor memory device with a refresh function, the semiconductor memory device comprising: Multiple storage units, each having a data storage unit for storing data and an error correction code storage unit for storing error correction codes corresponding to the data stored in the data storage unit; Error correction code generation unit, which generates error correction codes; An error correction unit performs error correction processing on the data using the error correction code; A row counter that determines the row address as the refresh target; A memory counter that identifies memory addresses as error correction targets; and A column counter that determines the column address as the error correction target. in: When the error correction unit receives a refresh command, it performs error correction processing on the data at the error correction target address determined based on the row counter, the memory counter, and the column counter, wherein: When a first refresh command is received, indicating that all memory cells in the plurality of memory cells should be refreshed, the row counter counts each time the first refresh command is issued; when a second refresh command is received, indicating that a specified memory cell in the plurality of memory cells should be refreshed, the row counter counts all the specified memory cells each time the second refresh command is issued. For each cycle of the row counter, the memory counter performs one counting operation; For each cycle of the memory counter, the column counter performs one counting operation. The issuance of a refresh command during refresh execution is limited by the cases where the second refresh command is issued during refresh execution in response to the first refresh command and the cases where the first refresh command is issued during refresh execution in response to the second refresh command; and When a command is issued during the refresh execution, each of the row counter, the bank counter, and the column counter performs a counting operation based on each of the row counter value, bank counter value, and column counter value prior to the issuance of the command during the refresh execution.

2. The semiconductor memory device according to claim 1, further comprising: One or more processors; and A memory coupled to the one or more processors and storing program instructions, which, when executed by the one or more processors, cause the one or more processors to provide at least: the plurality of memory banks; the error correction code generation unit; the error correction unit; the line counter; and the memory bank counter; and the column counter.

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