A method for preparing a GaN-HEMT device to prevent over-etching of AlGaN

Abstract

A preparation method of a GaN-HEMT device for preventing AlGaN over-etching, comprising the following steps: S100, sequentially preparing an AlN spacer layer, an Al composition gradient buffer AlGaN layer and a C-doped high-resistance GaN layer on a substrate; S200, sequentially preparing a GaN channel layer, an AlN insertion layer and an AlGaN barrier layer on the C-doped high-resistance GaN layer; S300, sequentially preparing an AlN blocking layer and a Mg-doped P-GaN cap layer on the AlGaN barrier layer; S400, etching the Mg-doped P-GaN cap layer outside the gate region on the epitaxial wafer and depositing an isolation layer; S500, performing ISO isolation on the passive region on the epitaxial wafer; S600, preparing D-pole ohmic contact metal and S-pole ohmic contact metal on the epitaxial wafer; S700, preparing G-pole Schottky contact metal and G-pole Pad metal on the epitaxial wafer; S800, preparing S-pole field plate, G-pole, S-pole and D-pole Pad metal on the epitaxial wafer; and S900, preparing a passivation layer and G-pole, S-pole and D-pole Pad windowing on the epitaxial wafer. The present application avoids causing serious high-frequency current collapse effect.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a method for fabricating a GaN-HEMT device that prevents AlGaN over-etching. Background Technology

[0002] In the field of power electronic device technology, third-generation semiconductors, represented by GaN and SiC, are receiving increasing attention. GaN, in particular, has advantages such as a large bandgap, high critical breakdown field strength, and high electron mobility, and has strong application potential in power device markets such as fast charging, data centers, OBCs, and solar inverters.

[0003] Currently, the main application of GaN in power devices is GaNHEMT devices. Since Khan et al. fabricated the first AlGaN / GaN high electron mobility transistor (HEMT) in 1993, horizontal GaNHEMT devices have attracted widespread attention due to their superior electrical performance and lower power consumption compared to Si devices.

[0004] GaNHEMT devices exhibit superior performance compared to traditional Si devices. In the fabrication process of the most mainstream PGaN-enhanced GaNHEMT devices, P-GaN etching is the most crucial step. However, during the actual P-GaN etching process, the thickness of the Mg-doped P-GaN capping layer varies in different regions of the epitaxial wafer. This often results in incomplete P-GaN etching or over-etching of the AlGaN barrier layer beneath the P-GaN layer. Both of these phenomena lead to a decrease in the 2DEG concentration of the GaNHEMT channel layer, causing not only an increase in the device's on-resistance and a decrease in current density, but also a larger ratio of dynamic resistance to static resistance at high frequencies. This significantly impacts the device's performance and usability. Therefore, resolving the issues of incomplete P-GaN etching or over-etching of the AlGaN barrier layer beneath the P-GaN layer during the P-GaN etching process is of great significance for the commercialization and promotion of GaNHEMT devices. Summary of the Invention

[0005] To address the above problems, this invention provides a method for fabricating GaN-HEMT devices that prevents AlGaN over-etching by increasing current density and reducing high-frequency current collapse effects.

[0006] The technical solution of this invention is: a method for fabricating a GaN-HEMT device to prevent over-etching of AlGaN, comprising the following steps: S100, an AlN spacer layer, an Al composition graded buffer AlGaN layer, and a C-doped high-resistivity GaN layer are sequentially prepared on the substrate; S200, GaN channel layer, AlN insertion layer and AlGaN barrier layer are sequentially prepared on C-doped high-resistivity GaN layer; S300, an AlN barrier layer and a MgP-GaN capping layer are sequentially prepared on an AlGaN barrier layer; S400, MgP-GaN capping layer is etched and isolation layer is deposited outside the gate region on the epitaxial wafer; S500 provides ISO isolation for passive regions on epitaxial wafers; S600, fabricating D-type ohmic contact metal and S-type ohmic contact metal on epitaxial wafer; S700, fabricating G electrode Schottky contact metal and G electrode Pad metal on epitaxial wafer; S800, fabricating S-electrode field plates, G, S, and D-electrode pad metals on an epitaxial wafer; S900 is used to prepare passivation layers and G, S, and D electrode pad windows on an epitaxial wafer.

[0007] Specifically, in step S100: The average thickness of the substrate is 1mm-5mm; The average thickness of the AlN spacer layer is 100nm-1000nm; The average thickness of the Al composition gradient buffer AlGaN layer is 1000nm-5000nm; The average thickness of the C-doped high-resistivity GaN layer is 3000nm-8000nm.

[0008] Specifically, in step S200: The average thickness of the GaN channel layer is 100-500 nm; The average thickness of the AlN insertion layer is less than 2 nm; The average thickness of the AlGaN barrier layer is 10-50 nm.

[0009] Specifically, in step S300: The average thickness of the AlN barrier layer is less than 2 nm; The average thickness of the MgP-GaN capping layer is 20nm-200nm.

[0010] Specifically, step S400 includes: S410 involves epitaxial wafer cleaning, photoresist coating, photolithography, and development. The gate region is protected with photoresist, and the area outside the gate region that is not protected with photoresist is etched with a MgP-GaN capping layer. The photoresist is then cleaned off, and an isolation layer is deposited.

[0011] Specifically, in step S410, the MgP-GaN capping layer is etched using ICP dry etching, with Cl2 and BCl3 as the etching gases.

[0012] Specifically, step S500 includes: S510 uses photoresist to protect the active area of ​​the device through epitaxial wafer cleaning, coating, photolithography, and development. S520 uses high-energy ion implantation on the passive region of the epitaxial wafer to destroy the internal lattice structure of the GaN channel layer (5), AlN insertion layer (6), AlGaN barrier layer (7) and AlN blocking layer (8) in the passive region, making it into a high-resistivity ISO isolation region, and the ISO isolation region plays an electrical isolation role.

[0013] Specifically, step S600 includes: S610 involves cleaning the epitaxial wafer, applying photoresist, photolithography, and development. Photoresist is used to protect the D and S electrode areas, and the D and S electrode areas are etched. The photoresist is then cleaned off. S620, D-electrode ohmic contact metal (13) and S-electrode ohmic contact metal (12) are prepared in the D and S electrode etching regions.

[0014] Specifically, step S700 includes: S710 involves epitaxial wafer cleaning, resist coating, photolithography, and development. Photoresist is used to protect the area outside the G electrode region, the G electrode region is etched, and then the photoresist is cleaned off. S720, prepare G electrode Schottky contact metal (14) in the G electrode etching region, and prepare G electrode Pad metal in the designed G electrode Pad region.

[0015] Specifically, step S800 includes: The S810 process involves epitaxial wafer cleaning, resist coating, photolithography, and development. Photoresist is used to protect the S, D, G, S, D electrode pad areas, and etch the S, D, G, S, D electrode pad areas. The photoresist is then removed. S820 fabricates the S-electrode field plate and G, S, and D-electrode pad metals in the designed region.

[0016] Specifically, step S900 includes: S910, depositing the first passivation layer and the second passivation layer; The S920 uses photoresist to protect the designed G, S, and D electrode pad metal regions through epitaxial wafer cleaning, resist coating, photolithography, and development, and etches windows into the designed G, S, and D electrode pad metal regions.

[0017] A GaN-HEMT device for preventing AlGaN over-etching includes, from bottom to top, a substrate, an AlN spacer layer, an Al composition-gradient buffer AlGaN layer, a C-doped high-resistivity GaN layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, an AlN blocking layer, and an isolation layer. An ISO isolation zone is provided between the GaN channel layer and the AlN barrier layer, located outside the D-type ohmic contact metal and the S-type ohmic contact metal. The AlN barrier layer is provided with a MgP-GaN capping layer located within the isolation layer; The top of the MgP-GaN capping layer is connected to it and located within the isolation layer, where a G-electrode Schottky contact metal is located. The isolation layer is provided with an S-pole ohmic groove and a D-pole ohmic groove extending to the AlN barrier layer; the S-pole ohmic groove is provided with an S-pole ohmic contact metal; the D-pole ohmic groove is provided with a D-pole ohmic contact metal. Within the isolation layer, an S-electrode field plate extending horizontally to the S-electrode ohmic contact metal is located above the G-electrode Schottky contact metal.

[0018] The present invention proposes a method for fabricating GaN-HEMT devices that prevents over-etching of the AlGaN barrier layer, which has the following advantages: it avoids the problems of incomplete P-GaN etching or over-etching of the AlGaN barrier layer below the P-GaN layer during actual P-GaN etching; it avoids the problems of increased on-resistance and decreased current density caused by the decrease in 2DEG concentration in the GaNHEMT channel layer, thus improving the current carrying capacity of the device; it also avoids the serious high-frequency current collapse effect caused by the large ratio of dynamic resistance to static resistance at high frequencies due to over-etching of the AlGaN barrier layer. Attached Figure Description

[0019] Figure 1 This is a process flow diagram of the present invention. Figure 2 This is a schematic diagram of step S100. Figure 3 This is a schematic diagram of step S200. Figure 4 This is a schematic diagram of step S300. Figure 5 This is a schematic diagram of step S400. Figure 6 This is a schematic diagram of step S500. Figure 7 This is a schematic diagram of step S600. Figure 8 This is a schematic diagram of step S700. Figure 9 This is a schematic diagram of step S800. Figure 10 This is a schematic diagram of step S900. In the figure, 1 is the substrate, 2 is the AlN spacer layer, 3 is the Al composition graded buffer AlGaN layer, 4 is the C-doped high-resistivity GaN layer, 5 is the GaN channel layer, 6 is the AlN insertion layer, 7 is the AlGaN barrier layer, 8 is the AlN blocking layer, 9 is the MgP-doped GaN capping layer, 10 is the isolation layer, 11 is the ISO isolation region, 12 is the S-electrode ohmic contact metal, 13 is the D-electrode ohmic contact metal, 14 is the G-electrode Schottky contact metal, and 15 is the S-electrode field plate. Detailed Implementation

[0020] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0021] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0022] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0023] This invention refers to Figure 1-10 As shown: A method for fabricating a GaN-HEMT device to prevent AlGaN over-etching includes the following steps: S100, an AlN spacer layer 2, an Al composition-gradient buffer AlGaN layer 3, and a C-doped high-resistivity GaN layer 4 are sequentially fabricated on a Si, sapphire, or SiC substrate 1, as shown in the figure. Figure 2 As shown; Further specifying step S100: The average thickness of the substrate 1 is 1mm-5mm; The average thickness of the AlN spacer layer 2 is 100nm-1000nm; The average thickness of the Al composition gradient buffer AlGaN layer 3 is 1000nm-5000nm; The average thickness of the C-doped high-resistivity GaN layer 4 is 3000nm-8000nm; Accordingly, the specific thickness of each layer is selected while ensuring that the stress superposition of each layer is small and the lattice mismatch of each layer is small. The Al composition of each layer in the gradient buffer AlGaN layer and the C doping concentration in the high-resistivity GaN layer are also selected, allowing for errors in the thickness of each layer at different locations on the epitaxial wafer. In this case, substrate 1 has an average thickness of 1 mm, AlN spacer layer 2 has an average thickness of 200 nm, gradient buffer layer has an average thickness of 1500 nm, and high-resistivity GaN layer has an average thickness of 4000 nm. Substrate 1 is a boron-doped Si substrate with a resistivity of 10 Ω·cm, and the gradient buffer layer consists of 300 nm AlN layers. 0.7 Ga 0.3 N, 600nmAl 0.5 Ga 0.5 N, 300nmAl 0.4 Ga 0.6 N, 300nmAl 0.2 Ga 0.8 It consists of four layers, and the resistivity of the high-resistivity GaN layer after C doping is 10. 8 Ω.cm.

[0024] S200, GaN channel layer 5, AlN insertion layer 6, and AlGaN barrier layer 7 are sequentially fabricated on C-doped high-resistivity GaN layer 4, as per reference. Figure 3 As shown; Further specifying step S200: The average thickness of the GaN channel layer 5 is 100-500 nm; The average thickness of the AlN insertion layer 6 is less than 2 nm; The average thickness of the AlGaN barrier layer 7 is 10-50 nm; Accordingly, the specific thicknesses of each layer and the Al composition in the AlGaN barrier layer 7 are selected under the conditions of small stress superposition, small lattice mismatch, and appropriate 2DEG concentration, allowing for errors in the thickness of each layer at different locations on the epitaxial wafer. In this case, the average thickness of the GaN channel layer 5 is 200 nm, the average thickness of the AlN insertion layer 6 is 0.8 nm, and the average thickness of the AlGaN barrier layer 7 is 15 nm; the composition of the AlGaN barrier layer 7 is Al 0.2 Ga 0.8 N.

[0025] S300, an AlN barrier layer 8 and a MgP-GaN capping layer 9 are sequentially prepared on the AlGaN barrier layer 7, as per reference. Figure 4 As shown; Further specifying step S300: The average thickness of the AlN barrier layer 8 is less than 2 nm; The average thickness of the MgP-GaN capping layer 9 is 20nm-200nm; Accordingly, the specific thicknesses of the above layers and the Mg doping concentration in the MgP-GaN capping layer 9 are selected under the conditions of small stress superposition, small lattice mismatch of each layer and complete depletion of 2DEG at the AlN insertion layer 6 position, allowing for errors in the thickness of the above layers at different positions of the epitaxial wafer. In this case, the AlN barrier layer 8 has an average thickness of 1 nm, and the MgP-GaN capping layer 9 has an average thickness of 80 nm; the Mg doping concentration in the MgP-GaN capping layer 9 is 3e19cm³. -3 Mobility 6cm 2 / (VS).

[0026] To fabricate GaNHEMT devices on the GaNHEMT epitaxial wafer prepared in the above steps, first draw the corresponding layout and prepare a photomask. Then, use the photomask to perform the following process steps. S400, etch the MgP-GaN capping layer 9 outside the gate region on the epitaxial wafer and deposit the isolation layer 10, as per reference. Figure 5 As shown; Further specifying, step S400 includes: S410 involves cleaning the epitaxial wafer, applying photoresist, photolithography, and development. The gate region is protected with photoresist, and the area outside the gate region that is not protected with photoresist is etched with a MgP-GaN capping layer 9. The photoresist is then cleaned off, and a Si3N4 isolation layer 10 is deposited. In step S410, the MgP-GaN capping layer 9 is etched using ICP dry etching. The etching gases are Cl2 and BCl3. There are no special requirements for the flow rate and ratio of Cl2 and BCl3, as long as Cl ions play an etching role and B ions react with Al to generate AlB2. The etching rate is 0.5nm-1nm / min, and the etching time is 1.1 times the ratio of the thickness of the MgP-GaN capping layer 9 to the etching rate to ensure that the MgP-GaN capping layer 9 is completely etched. The average thickness of Si3N4 or SiO2 is 100-500nm. The specific thickness of the layer is selected under the condition of small stress superposition of each layer. Correspondingly, due to the presence of the AlN barrier layer 8, when B ions are etched into this layer, they will react with the Al component in the AlN barrier layer 8 to generate AlB2 with extremely high hardness. AlB2 can block the etching reaction from occurring and protect the AlGaN barrier layer 7 below the AlN barrier layer 8 from being etched. In this case, the flow rates of both Cl2 and BCl3 were set to 1 mT, the etching rate was 1 nm / min, the etching time was 90 min, and the average thickness of the Si3N4 isolation layer 10 was 200 nm.

[0027] S500 performs ISO isolation on passive regions on the epitaxial wafer, referencing... Figure 6 As shown; Further specifying, step S500 includes: The S510 process involves epitaxial wafer cleaning, resist coating, photolithography, and development. Photoresist is used to protect the active regions of the device, while ISO isolation is applied to the passive regions on the epitaxial wafer. The photoresist is then removed. S520, high-energy ions can use substances such as F and H to destroy the internal lattice structure of GaN channel layer (5), AlN insertion layer (6), AlGaN barrier layer (7) and AlN blocking layer (8) in the passive region, making it into a high-resistivity ISO isolation region 11. The ISO isolation region then plays an electrical isolation role. The injection energy and injection number can be set and adjusted according to the specific process.

[0028] In this case, high-energy ion F-implantation was used at an injection angle of 7 degrees, administered in three stages. The energies and doses of the three implantations were 140 keV and 1.2 eV, respectively. 14 cm -3 80 keV and 0.6e 14 cm -3 40 keV and 0.4e 14 cm -3 ; S600, D-type ohmic contact metal 13 and S-type ohmic contact metal 12 are fabricated on the epitaxial wafer, as per reference. Figure 7 As shown; Further specifying, step S600 includes: In step S610, the epitaxial wafer is cleaned, coated with photoresist, photolithographically etched, and developed. Photoresist is used to protect the D and S electrode regions. The D and S electrode regions are then etched, and the etching depth of the D and S electrode regions is not less than the thickness of the isolation layer 10 in step S400. If the Si3N4 or SiO2 isolation layer 10 is completely etched, the AlGaN barrier layer 7 can be etched or not. The photoresist is then cleaned off. S620, optionally, can use a metal stripping process, through epitaxial wafer cleaning, resist coating, photolithography, and development, to protect the D and S electrode areas with photoresist, then deposit ohmic contact metal of the corresponding thickness to prepare D and S electrode ohmic metal, and then clean off the photoresist. Optionally, a metal etching process can be used. First, an ohmic contact metal of the corresponding thickness is deposited. Then, through epitaxial wafer coating, photolithography, and development, the D and S electrode regions are protected with photoresist. ICP dry etching is used to etch away the metal outside the D and S electrode regions. The etching depth is not less than the corresponding thickness of the ohmic contact metal deposited in S750 to ensure that the metal outside the D and S electrode regions is completely etched, thus preparing the D and S electrode ohmic metal. Then, the photoresist is cleaned away. Accordingly, a high-temperature annealing process is used to form ohmic contacts and deposit a Si3N4 or SiO2 barrier layer with an average thickness of 100-500nm. The specific thickness of the layer is selected under the condition that the stress superposition of each layer is small. In this case, the etching depth of the D and S electrode regions is 200nm. A metal stripping process is used to protect the outside of the D and S electrode regions with photoresist. 20nm Ti / 130nm Ni / 50nm Ag / 50nm Al are deposited. The metal outside the D and S electrode regions is stripped together with the photoresist to form the ohmic metal of the D and S electrodes. The ohmic metal of the D and S electrodes is connected to the underlying 2DEG layer by high temperature annealing at 850℃ for 30s to form an ohmic contact. Subsequently, a 140nm thick Si3N4 isolation layer 10 is deposited.

[0029] S700, fabrication of G electrode Schottky contact metal 14 and G electrode Pad metal on epitaxial wafer, referencing... Figure 8 As shown; Further specifying, step S700 includes: S710 involves epitaxial wafer cleaning, resist coating, photolithography, and development. Photoresist is used to protect the area outside the G electrode region, the G electrode region is etched, and then the photoresist is cleaned off. Optionally, in step S710, the etching depth of the G electrode region is not less than the total thickness of the Si3N4 or SiO2 isolation layer 10, and the P-GaN layer is etched as little as possible while ensuring that the Si3N4 or SiO2 isolation layer 10 is completely etched. S720, optionally, can use a metal stripping process, through epitaxial wafer cleaning, coating, photolithography, and development, to protect the outside of the G electrode and G electrode Pad area with photoresist, deposit a Schottky contact metal of the corresponding thickness, strip the metal outside the G electrode and G electrode Pad area together with the photoresist, prepare the G electrode Schottky metal and G electrode Pad metal, and then clean off the photoresist; Optionally, a metal etching process can be used. First, a Schottky contact metal of appropriate thickness is deposited. Then, photoresist is used to protect the G electrode and G Pad area through epitaxial wafer coating, photolithography, and development. ICP dry etching is then used to etch away the metal outside the G electrode and G Pad area. The etching depth is not less than the deposited Schottky contact metal of appropriate thickness to ensure complete etching of the metal outside the G electrode and G Pad area, thus preparing the G electrode ohmic metal and G Pad metal. The photoresist is then cleaned away. The G electrode Schottky metal and the G electrode Pad metal are interconnected; Subsequently, a Si3N4 or SiO2 isolation layer 10 is deposited. The average thickness of the Si3N4 or SiO2 layer is 100-500 nm. The specific thickness of the layer is selected under the condition of minimizing the stress superposition of each layer.

[0030] In this case, the etching depth of the G electrode region is 340nm. A metal stripping process is used to protect the G electrode region and the designed G electrode Pad region with photoresist. A 50nm Ni / 150nm Au is deposited, and the metal outside the G electrode region and the designed G electrode Pad region is stripped together with the photoresist to form the G electrode Schottky contact metal and the G electrode Pad metal. Subsequently, a 140nm thick Si3N4 isolation layer 10 is deposited.

[0031] S800, fabricating the S-polar field plate 15 on the epitaxial wafer, with G, S, and D electrode pad metals, as referenced. Figure 9 As shown; Further defining the S810 process, the epitaxial wafer is cleaned, coated with photoresist, photolithographically etched, and developed. Photoresist is used to protect the S, D, G, S, D electrode pad areas, and the S, D, G, S, D electrode pad areas are etched, and then the photoresist is cleaned off. Optionally, in step S810, the etching depth is not less than the total thickness of the Si3N4 or SiO2 isolation layer 10 deposited in S600 and S700, ensuring that the Si3N4 or SiO2 isolation layer 10 is completely etched, while minimizing the etching of the underlying metal. S820, optionally, can use a metal stripping process, through epitaxial wafer cleaning, resist coating, photolithography, and development, to protect the outside of the S-polar field plate 15, S, D-polar and G, S, D-polar Pad areas with photoresist, deposit a metal layer of appropriate thickness, the metal layer can be any metal with low on-resistance, and then strip the metal outside the S-polar field plate 15 and G, S, D-polar Pad areas together with the photoresist to prepare the S-polar field plate 15 and G, S, D-polar Pad metal, and then clean off the photoresist; Optionally, a metal etching process can be used. First, a metal layer of appropriate thickness is deposited. The metal layer can be any metal with low on-resistance. After epitaxial wafer coating, photolithography, and development, photoresist is used to protect the S-field plate 15 and the G, S, and D-field Pad areas. ICP dry etching is then used to etch away the metal outside the S-field plate 15 and the G, S, and D-field Pad areas. The etching depth is not less than the deposited metal layer of appropriate thickness to ensure that the metal outside the S-field plate 15 and the G, S, and D-field Pad areas is completely etched, thus preparing the S-field plate 15 and the G, S, and D-field Pad metal. Then, the photoresist is cleaned off. Correspondingly, the S-pole field plate 15 and the S-pole via are interconnected, the G-pole Pad and the G-pole are interconnected, the S-pole Pad and the S-pole are interconnected, and the D-pole Pad and the D-pole are interconnected. Single-stage or multi-stage field plates can be fabricated according to design and requirements. Multi-stage field plates can be fabricated by repeating step S800.

[0032] In this case, the etching depth is 280nm. A metal stripping process is used to protect the outside of the S, D and G, S and D electrode pad areas of the S electrode field plate 15 with photoresist. 50nm Ti / 150nm Al is deposited. The metal outside the S, D and G, S and D electrode pad areas of the S electrode field plate 15 is stripped off along with the photoresist to prepare the S electrode field plate 15 and the G, S and D electrode pad metal.

[0033] S900, a passivation layer and G, S, and D electrode pad windows are prepared on the epitaxial wafer, referring to... Figure 10 As shown; S910, deposits Si3N4 or SiO2 of a designed thickness as the first passivation layer, and PI of a set thickness as the second passivation layer; Optionally, the average thickness of Si3N4 or SiO2 is 100-5000 nm, and the average thickness of PI is 500-5000 nm, with the specific thickness matching the design withstand voltage. The S920 process involves epitaxial wafer cleaning, resist coating, photolithography, and development. Photoresist is used to protect the G, S, and D electrode pad areas, and the G, S, and D electrode pad areas are etched. The photoresist is then removed. Accordingly, in step S920, the etching depth is not less than the sum of the thicknesses of the first and second passivation layers (6000 nm in this case), ensuring that the passivation layer is completely etched while minimizing etching of the Pad metal. In this case, 1000nm Si3N4 was deposited as the first passivation layer, 5000nm PI was deposited as the second passivation layer, and the etching depth was 6000nm.

[0034] The entire device fabrication is now complete.

[0035] Reference Figure 10 As shown, a GaN-HEMT device for preventing AlGaN over-etching includes, from bottom to top, a substrate 1, an AlN spacer layer 2, an Al composition gradient buffer AlGaN layer 3, a C-doped high-resistivity GaN layer 4, a GaN channel layer 5, an AlN insertion layer 6, an AlGaN barrier layer 7, an AlN blocking layer 8, and an isolation layer 10. An ISO isolation region 11 is provided between the GaN channel layer 5 and the AlN barrier layer 8, located outside the D-type ohmic contact metal 13 and the S-type ohmic contact metal 12. The ISO isolation region 11 is connected to the outer side of the GaN channel layer 5, the AlN insertion layer 6, the AlGaN barrier layer 7, and the AlN barrier layer 8 from bottom to top. The AlN barrier layer 8 is provided with a MgP-GaN capping layer 9 located within the isolation layer 10; The top of the MgP-GaN capping layer 9 is provided with a G electrode Schottky contact metal 14 connected thereto and located within the isolation layer 10; The isolation layer 10 is provided with an S-pole ohmic groove and a D-pole ohmic groove extending to the AlN barrier layer 8; the S-pole ohmic groove is provided with an S-pole ohmic contact metal 12; the D-pole ohmic groove is provided with a D-pole ohmic contact metal 13. The top surfaces of the S-pole ohmic contact metal 12 and the D-pole ohmic contact metal 13 are located below the top surface of the isolation layer 10, respectively. Within the isolation layer 10, an S-electrode field plate 15 is provided above the G-electrode Schottky contact metal 14, extending horizontally to the S-electrode ohmic contact metal 12.

[0036] The advantages of this GaN-HEMT device for preventing over-etching of the AlGaN barrier layer are as follows: While ensuring complete etching of the MgP-GaN capping layer 9, the etching reaction gas reacts with the AlN barrier layer 8 to generate AlB2, which has extremely high hardness. This prevents the AlGaN barrier layer 7 from being etched, significantly improving the device's current density and reducing dynamic resistance drift. Under the same process conditions, as shown in Table 1, the GaN-HEMT device for preventing over-etching of the AlGaN barrier layer 7 described herein (this device) exhibits a 30% increase in current density and a decrease in the ratio of dynamic resistance to static resistance at 100kHz from 1.8 to 1.2 compared to mainstream products on the market (Comparative Device 2). Compared to these mainstream products, the device exhibits a 20% increase in current density and a decrease in the ratio of dynamic resistance to static resistance at 100kHz from 1.5 to 1.2, as shown in Table 1. Table 1: This device 5 1.2 Comparison Device 1 3.5 1.8 Comparison Device 2 4 1.5 Regarding the information disclosed in this case, the following points need to be clarified: (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design. (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A method for fabricating a GaN-HEMT device to prevent AlGaN over-etching, characterized in that, Includes the following steps: S100, an AlN spacer layer (2), an Al composition gradient buffer AlGaN layer (3), and a C-doped high-resistivity GaN layer (4) are sequentially prepared on a substrate (1). S200, GaN channel layer (5), AlN insertion layer (6) and AlGaN barrier layer (7) are sequentially prepared on C-doped high-resistivity GaN layer (4). S300, an AlN barrier layer (8) and a MgP-GaN capping layer (9) are sequentially prepared on the AlGaN barrier layer (7). S400, a MgP-GaN capping layer (9) is formed outside the gate region on the epitaxial wafer, and the etching gases are Cl2 and BCl2; due to the presence of the AlN barrier layer (8), the B ions etched into the AlN barrier layer (8) will react with the Al component in the AlN barrier layer (8) to generate AlB2, and the barrier etching continues to protect the underlying AlGaN barrier layer (7) from over-etching; then an isolation layer (10) is deposited. S500 performs ISO isolation on the passive region on the epitaxial wafer, destroying the lattice structure of GaN channel layer (5), AlN insertion layer (6), AlGaN barrier layer (7) and AlN barrier layer (8) to form a high-resistivity ISO isolation region (11). S600, D-type ohmic contact metal (13) and S-type ohmic contact metal (12) are prepared on the epitaxial wafer. S700, G electrode Schottky contact metal (14) and G electrode Pad metal are prepared on an epitaxial wafer; S800, an S-electrode field plate (15) is prepared on an epitaxial wafer, the S-electrode field plate (15) extends horizontally to cover the G-electrode Schottky contact metal (14); and G, S, and D-electrode Pad metals are prepared. S900 is used to prepare passivation layers and G, S, and D electrode pad windows on an epitaxial wafer.

2. The method for fabricating a GaN-HEMT device to prevent AlGaN over-etching according to claim 1, characterized in that, In step S100: The average thickness of the substrate (1) is 1 mm to 5 mm; The average thickness of the AlN spacer layer (2) is 100nm-1000nm; The average thickness of the Al composition gradient buffer AlGaN layer (3) is 1000nm-5000nm; The average thickness of the C-doped high-resistivity GaN layer (4) is 3000nm-8000nm.

3. The method for fabricating a GaN-HEMT device to prevent AlGaN over-etching according to claim 1, characterized in that, In step S200: The average thickness of the GaN channel layer (5) is 100-500 nm; The average thickness of the AlN insertion layer (6) is less than 2 nm; The average thickness of the AlGaN barrier layer (7) is 10-50 nm.

4. The method for fabricating a GaN-HEMT device to prevent AlGaN over-etching according to claim 1, characterized in that, The average thickness of the AlN barrier layer (8) in step S300 is less than 2 nm; The average thickness of the MgP-GaN capping layer (9) is 20nm-200nm.

5. The method for fabricating a GaN-HEMT device to prevent AlGaN over-etching according to claim 1, characterized in that, Step S400 includes: S410, through epitaxial wafer cleaning, coating, photolithography, and development, the gate region is protected with photoresist, and the area outside the gate region that is not protected with photoresist is etched with a MgP-GaN capping layer (9). Then the photoresist is cleaned off and an isolation layer (10) is deposited.

6. The method for fabricating a GaN-HEMT device to prevent AlGaN over-etching according to claim 1, characterized in that, Step S500 includes: S510 uses photoresist to protect the active area of ​​the device through epitaxial wafer cleaning, coating, photolithography, and development. S520 uses high-energy ion implantation on the passive region of the epitaxial wafer to destroy the internal lattice structure of the GaN channel layer (5), AlN insertion layer (6), AlGaN barrier layer (7) and AlN blocking layer (8) in the passive region, so that the GaN channel layer (5), AlN insertion layer (6), AlGaN barrier layer (7) and AlN blocking layer (8) in the passive region become the high-resistivity ISO isolation region (11), and the ISO isolation region (11) plays an electrical isolation role.

7. The method for fabricating a GaN-HEMT device to prevent AlGaN over-etching according to claim 1, characterized in that, Step S600 includes: S610 involves cleaning the epitaxial wafer, applying photoresist, photolithography, and development. Photoresist is used to protect the D and S electrode areas, and the D and S electrode areas are etched. The photoresist is then cleaned off. S620, D-electrode ohmic contact metal (13) and S-electrode ohmic contact metal (12) are prepared in the D and S electrode etching regions.

8. The method for fabricating a GaN-HEMT device to prevent AlGaN over-etching according to claim 1, characterized in that, Step S700 includes: S710 involves epitaxial wafer cleaning, resist coating, photolithography, and development. Photoresist is used to protect the area outside the G electrode region, the G electrode region is etched, and then the photoresist is cleaned off. S720, prepare G electrode Schottky contact metal (14) in the G electrode etching region, and prepare G electrode Pad metal in the designed G electrode Pad region.

9. The method for fabricating a GaN-HEMT device to prevent AlGaN over-etching according to claim 1, characterized in that, Step S800 includes: The S810 process involves epitaxial wafer cleaning, resist coating, photolithography, and development. Photoresist is used to protect the S, D, G, S, D electrode pad areas, and etch the S, D, G, S, D electrode pad areas. The photoresist is then removed. S820 fabricates the S-electrode field plate and G, S, and D-electrode pad metals in the designed region.

10. The method for fabricating a GaN-HEMT device to prevent AlGaN over-etching according to claim 1, characterized in that, Step S900 includes: S910, depositing the first passivation layer and the second passivation layer; The S920 uses photoresist to protect the designed G, S, and D electrode pad metal regions through epitaxial wafer cleaning, resist coating, photolithography, and development, and etches windows into the designed G, S, and D electrode pad metal regions.

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