Semiconductor structure and method of forming the same

Abstract

The present application provides a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises: forming a first epitaxial layer on a substrate. A first recess is formed in the first epitaxial layer. A first dielectric layer is formed in the first recess. A first conductive layer is formed on the first dielectric layer. A second epitaxial layer is formed on the first epitaxial layer. Similarly, a gate dielectric layer is formed on the second epitaxial layer. A gate electrode is formed on the gate dielectric layer. The present application can reduce the aspect ratio of the trench and improve the reliability of the components.

Description

Technical Field

[0001] This invention relates to semiconductor structures and methods for forming them, and more particularly to semiconductor structures with excellent reliability and methods for forming them. Background Technology

[0002] With the evolution of technology, metal-oxide-semiconductor field-effect transistors (MOSFETs) have continuously innovated from planar MOSFETs, super-junction MOSFETs, and trench MOSFETs to shielded gate trench MOSFETs (SGT-MOSFETs) to meet more diverse needs. Trench MOSFETs have a trench structure for housing the vertical gate electrode, thus enabling a reduction in device size, resulting in a smaller device pitch and lower gate-drain capacitance (C). gd This can effectively reduce the on-resistance (R). on Furthermore, because the SGT-MOSFET includes a source electrode that serves as a shield electrode, it can achieve lower on-resistance and lower switching loss based on charge balancing technology.

[0003] However, as usage demands increase, transistors are expected to have smaller dimensions to improve integration density. But if the size of transistors needs to be reduced, the width of the trenches usually needs to be reduced accordingly, and the aspect ratio also increases as the trench width decreases, which leads to manufacturing difficulties.

[0004] Therefore, although existing semiconductor structures and their fabrication methods have gradually met their intended applications, they still do not completely meet the requirements in all aspects. Consequently, there are still some issues to be overcome regarding semiconductor structures and their fabrication methods that can be further processed into SGT-MOSFETs. Summary of the Invention

[0005] In view of the aforementioned problems, this invention reduces the aspect ratio of the trench by independently and sequentially setting the first epitaxial layer and the second epitaxial layer. Simultaneously, it improves the reliability of the conductive material filling the trench by adjusting parameters such as the thickness and doping concentration of the first and second epitaxial layers. For example, it can reduce and / or avoid one or any combination of undesirable structures such as voids, holes, seam defects, and depressions in the conductive material filling the trench, thereby improving the reliability and electrical performance of the subsequently formed SGT-MOSFET.

[0006] According to some embodiments, a method for forming a semiconductor structure is provided. The method for forming a semiconductor structure includes: forming a first epitaxial layer on a substrate; forming a first recess in the first epitaxial layer; forming a first dielectric layer in the first recess; forming a first conductive layer on the first dielectric layer; forming a second epitaxial layer on the first epitaxial layer; similarly forming a gate dielectric layer on the second epitaxial layer; and forming a gate electrode on the gate dielectric layer.

[0007] According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes: a substrate, a first epitaxial layer, a first dielectric layer, a first conductive layer, a second epitaxial layer, a gate dielectric layer, a gate electrode, and a semiconductor layer. The substrate has a first conductivity type. The first epitaxial layer has a first conductivity type. The first epitaxial layer is disposed on the substrate and includes a first recess. The first dielectric layer is disposed in the first recess. The first conductive layer is disposed on the first dielectric layer. The second epitaxial layer has a first conductivity type. The second epitaxial layer is disposed on the first epitaxial layer and includes a second recess. The gate dielectric layer is disposed in the second recess. The gate electrode is disposed on the gate dielectric layer. The semiconductor layer has a second conductivity type different from the first conductivity type. The semiconductor layer is disposed in the second epitaxial layer but not in the second recess.

[0008] The semiconductor structure of the present invention can be applied to various types of semiconductor devices. To make the components and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0009] The following detailed description, in conjunction with the accompanying drawings, will provide a better understanding of the embodiments of the present invention. It is worth noting that, according to industry standard practice, some features may not be drawn to scale. In fact, for clarity of discussion, the dimensions of different features may be increased or decreased.

[0010] Figures 1 to 14 The diagram illustrates cross-sectional views of the semiconductor structure being formed at various stages, according to some embodiments of the present invention.

[0011] Icon labels:

[0012] 1: Semiconductor structure;

[0013] 100: substrate;

[0014] 200: First epitaxial layer;

[0015] 201: first concave part;

[0016] 202: First trench;

[0017] 210: First dielectric layer;

[0018] 300: First conductive material;

[0019] 310: First conductive layer;

[0020] 400: Second epitaxial layer;

[0021] 401: second concave part;

[0022] 402: Second trench;

[0023] 410: Second dielectric layer;

[0024] 420: Gate dielectric layer;

[0025] 500: Second conductive material;

[0026] 510: Gate electrode;

[0027] 600: Semiconductor layer;

[0028] 610: First doped region;

[0029] 620: Second doped region;

[0030] 700: Interlayer dielectric layer;

[0031] 800: Contact object;

[0032] 900: Metal layer;

[0033] D1: First depth;

[0034] D2: Second depth;

[0035] D3: Third Depth;

[0036] D4: Fourth Depth;

[0037] T1: First thickness;

[0038] T2: Second thickness;

[0039] W1: First width;

[0040] W2: Second width;

[0041] W3: Third width;

[0042] W4: Fourth width. Detailed Implementation

[0043] The following provides many different embodiments or examples for implementing various components of the provided semiconductor structure. Specific examples of each component and its configuration are described below to simplify the embodiments of the invention. Of course, these are merely examples and are not intended to limit the invention. For instance, if the description mentions a first component formed on top of a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components so that they are not in direct contact. Furthermore, device symbols and / or characters may be repeated in different examples of the embodiments of the invention. Such repetition is for brevity and clarity and is not intended to indicate a relationship between the different embodiments and / or states discussed.

[0044] The following describes some variations of the embodiments. In embodiments with different figures and descriptions, similar device symbols are used to designate similar devices. It is understood that additional operations may be provided before, during, and after the method, and some described operations may be replaced or deleted for other embodiments of the foregoing method.

[0045] Furthermore, spatial terms such as "above," "below," "over," "under," and similar expressions include not only the orientation shown in the diagrams but also the different orientations of the device during use or operation. When the device is turned to another orientation (rotated 90 degrees or other orientations), the spatial relative descriptions used here can also be interpreted according to the orientation after rotation. Here, "approximately," "substantially," or similar terms generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, even without specific mention of "approximately," "substantially," or similar terms, their meaning may still be implied.

[0046] Figures 1 to 14 This is a cross-sectional schematic diagram illustrating the formation of semiconductor structure 1 at various stages according to some embodiments of the present invention.

[0047] Reference Figure 1A first epitaxial layer 200 is formed on a substrate 100. In some embodiments, the substrate 100 may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or a similar substrate. Generally, an SOI substrate includes a semiconductor film layer formed on an insulator. For example, the aforementioned insulating layer may be a silicon oxide layer, a silicon nitride layer, a polysilicon layer, or a combination thereof. The aforementioned insulating layer is provided on a substrate that is typically silicon or aluminum nitride (AlN). The substrate 100 may be a doped substrate (e.g., using p-type or n-type dopants) or an undoped substrate. The substrate 100 may also be other types of substrates, such as a multi-layered substrate or a gradient substrate.

[0048] In some embodiments, the substrate 100 may be an elemental semiconductor, and the aforementioned elemental semiconductor may include silicon and germanium; the substrate 100 may also be a compound semiconductor, and the aforementioned compound semiconductor may include, for example, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide, but is not limited thereto; the substrate 100 may also be an alloy semiconductor, and the aforementioned alloy semiconductor may include, for example, one or any combination of SiGe (silicon-germanium), GaAsP (gallium arsenide phosphide), AlInAs (aluminum indium arsenide), AlGaAs (aluminum gallium arsenide), GaInAs (indium gallium arsenide), GaInP (gallium indium phosphide), and GaInAsP (gallium arsenide phosphide), but is not limited thereto. In some embodiments, the substrate 100 is a silicon substrate.

[0049] like Figure 1As shown, in some embodiments, the first epitaxial layer 200 may include silicon, germanium, silicon-germanium, group III-V compounds (compounds of groups III and V in the periodic table), or combinations thereof. The aforementioned first epitaxial layer 200 may be formed by a deposition or epitaxial process such as metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), combinations thereof, or similar processes. In some embodiments, the first epitaxial layer 200 may have a first thickness T1. In some embodiments, the first epitaxial layer 200 may be formed directly on the substrate 100.

[0050] Reference Figure 2 A first recess 201 is formed in the first epitaxial layer 200. In some embodiments, the first recess 201 does not penetrate the first epitaxial layer 200. In some embodiments, a patterned hard mask layer with an opening is formed on the first epitaxial layer 200, and a portion of the upper surface of the first epitaxial layer 200 is exposed through the opening of the patterned hard mask layer. Then, the first epitaxial layer 200 is etched using the patterned hard mask layer as an etching mask to remove a portion of the first epitaxial layer 200, thereby forming the first recess 201. In some embodiments, the etching process may include dry etching, wet etching, or other etching processes. Dry etching may include, but is not limited to, plasma etching, plasmaless gas etching, sputter etching, ion milling, and reactive ion etching (RIE). Wet etching may include, but is not limited to, using an acidic solution, an alkaline solution, or a solvent to remove at least a portion of the structure to be removed. Afterward, the patterned hard mask layer is removed. Understandably, appropriate patterned hard mask layers, etching processes, and removal processes can be selected based on process conditions, and the dimensions of the first recess 201 can be adjusted according to subsequent electrical requirements. In some embodiments, the first recess 201 has a first width W1 and a first depth D1.

[0051] Reference Figure 3Similarly, a first dielectric layer 210 is formed in the first recess 201. In some embodiments, the first dielectric layer 210 covers the side and lower surfaces of the first recess 201 and the upper surface of the first epitaxial layer 200. In some embodiments, the first dielectric layer 210 may be formed by a deposition process or a thermal oxidation process. The deposition process may be low-pressure chemical vapor deposition (LPCVD), low-temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable deposition processes. In some embodiments, the first dielectric layer 210 may be formed by a thermal oxidation process.

[0052] In some embodiments, the first dielectric layer 210 may be silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, any other suitable dielectric material, or a combination thereof. The aforementioned high-k dielectric material may be a metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, metal oxynitride, metal aluminate, zirconium silicate, or zirconium aluminate. In some embodiments, the first dielectric layer 210 may include an oxide. In some embodiments, the first dielectric layer 210 may include silicon oxide. In some embodiments, the thickness of the first dielectric layer 210 may be adjusted according to electrical requirements. In some embodiments, the first dielectric layer 210 has a shape corresponding to the first recess 201. For example, the first dielectric layer 210 may form a first trench 202, and the shape of the first recess 201 corresponds to the shape of the first trench 202. The first trench 202 may have a second width W2 and a second depth D2. That is, the aspect ratio of the first trench 202 is the ratio of the second depth D2 to the second width W2.

[0053] Reference Figure 4A first conductive material 300 is formed in the first trench 202 formed in the first dielectric layer 210 to form the subsequent first conductive layer. The first conductive material 300 can be directly formed on the first dielectric layer 210. The first conductive material 300 can be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition process. In some embodiments, the first conductive material 300 may include polycrystalline silicon, amorphous silicon, metal, metal nitride, conductive metal oxide, other suitable materials, or combinations thereof. In some embodiments, the first conductive material 300 may be polycrystalline silicon. In some embodiments, the first conductive material 300 may be doped polycrystalline silicon to reduce the resistance of the subsequently formed first conductive layer by increasing the doping concentration of the first conductive material 300. In addition, when the first conductive material 300 is doped polycrystalline silicon, it is more conducive to its formation in the first trench 202.

[0054] Reference Figure 5 The first conductive material 300 and the first dielectric layer 210 are planarized to form the first conductive layer 310 on the first dielectric layer 210. In some embodiments, the planarization process may remove a portion of the first conductive material 300 and a portion of the first dielectric layer 210 to expose the upper surface of the first epitaxial layer 200. In some embodiments, the first conductive layer 310, the first dielectric layer 210, and the first epitaxial layer 200 are substantially coplanar. In some embodiments, the planarization process may be a chemical mechanical polishing (CMP) process. In some embodiments, since the first conductive layer 310 completely fills the first trench 202, the first conductive layer 310 has a second width W2 corresponding to the first trench 202.

[0055] Reference Figure 6 A second epitaxial layer 400 is formed on the first epitaxial layer 200. In some embodiments, the materials and processes used to form the second epitaxial layer 400 may be the same as or different from those used to form the first epitaxial layer 200. In some embodiments, the second epitaxial layer 400 is formed after the first recess 201, the first dielectric layer 210, and the first conductive layer 310 are formed. In some embodiments, the first epitaxial layer 200 and the second epitaxial layer 400 are formed independently. Therefore, since the first epitaxial layer 200 and the second epitaxial layer 400 are formed independently, the aspect ratio of the recesses and / or trenches formed in the first epitaxial layer 200 and the second epitaxial layer 400 can be significantly reduced, thereby significantly improving the reliability of the components formed in the aforementioned recesses and / or trenches. For example, voids, cavities, seam defects, and / or depressions in the material filling the recesses and / or trenches can be reduced and / or avoided.

[0056] like Figure 6As shown, in some embodiments, the second epitaxial layer 400 may have a second thickness T2. In some embodiments, the first thickness T1 of the first epitaxial layer 200 may be greater than the second thickness T2 of the second epitaxial layer 400. The dimensions of components disposed in the first epitaxial layer 200 and components disposed in the second epitaxial layer 400 can be adjusted by adjusting the thickness ratio of the first epitaxial layer 200 and the second epitaxial layer 400. For example, the length of the shielding electrode in the first epitaxial layer 200 and the length of the gate electrode subsequently formed in the second epitaxial layer 400 can be adjusted.

[0057] In detail, in some embodiments, the overall thickness of the first epitaxial layer 200 and the second epitaxial layer 400, that is, the sum of the first thickness T1 and the second thickness T2, affects the breakdown voltage capability of the subsequently formed SGT-MOSFET. The higher the sum of the first thickness T1 and the second thickness T2, the higher the breakdown voltage capability of the subsequently formed SGT-MOSFET. Furthermore, comparing SGT-MOSFETs with different breakdown voltage capabilities, the gate electrode length can be similar. Therefore, the second thickness T2 of the second epitaxial layer 400 of an SGT-MOSFET with high breakdown voltage capability and an SGT-MOSFET with low breakdown voltage capability may be similar. However, the first thickness T1 of the first epitaxial layer 200 of the SGT-MOSFET with high breakdown voltage capability will be greater than the first thickness T1 of the first epitaxial layer 200 of the SGT-MOSFET with low breakdown voltage capability, in order to achieve high breakdown voltage capability by increasing the first thickness T1 of the first epitaxial layer 200. Therefore, the embodiments of the present invention can improve the reliability of the device formed in the epitaxial layer while improving the withstand voltage capability by separately and independently forming the first epitaxial layer 200 and the second epitaxial layer 400.

[0058] In some embodiments, the second epitaxial layer 400 is made of the same material as the first epitaxial layer 200. In some embodiments, both the second epitaxial layer 400 and the first epitaxial layer 200 are monocrystalline silicon. In some embodiments, the second epitaxial layer 400 may be undoped or doped monocrystalline silicon.

[0059] In some embodiments, the doping concentration of the first epitaxial layer 200 may be greater than or equal to the doping concentration of the second epitaxial layer 400. Therefore, when the doping concentration of the first epitaxial layer 200 is greater than or equal to the doping concentration of the second epitaxial layer 400, the resistance of the first epitaxial layer 200 can be reduced, thereby reducing the on-resistance. Furthermore, since the doping concentration of the second epitaxial layer 400 may be equal to or lower than the doping concentration of the first epitaxial layer 200, it is more advantageous for other components to be subsequently formed in the second epitaxial layer 400. For example, a lower concentration of dopant can be doped into the second epitaxial layer 400, thereby forming other components such as subsequently formed semiconductor layers, first doped regions, and second doped regions. Therefore, in embodiments of the present invention, epitaxial layers with two doping concentrations can be formed more advantageously.

[0060] In some embodiments, the second epitaxial layer 400 can be formed on the first epitaxial layer 200 by a deposition process or an epitaxial process in a blanket manner. Specifically, the second epitaxial layer 400 can be formed on the first epitaxial layer 200, the first dielectric layer 210, and the first conductive layer 310 in a blanket manner. It should be particularly noted that, as Figure 6 As shown, an interface may exist between the first epitaxial layer 200 and the second epitaxial layer 400. Although the materials of the second epitaxial layer 400 and the first dielectric layer 210 are different, a slight mismatch may arise. However, since the area of ​​the first dielectric layer 210 is a small proportion of the area of ​​the aforementioned interface, it will not affect the reliability of the second epitaxial layer 400. Furthermore, although the materials of the second epitaxial layer 400 and the first conductive layer 310 are different, a slight mismatch may arise. However, since the area of ​​the first conductive layer 310 is a small proportion of the area of ​​the aforementioned interface, it will not affect the reliability of the second epitaxial layer 400. Simultaneously, in the subsequent process of forming the second recess in the second epitaxial layer 400, a portion of the second epitaxial layer 400 on the first conductive layer 310 will be removed. Therefore, the slight mismatch problem between the second epitaxial layer 400 and the first conductive layer 310 can be further reduced. In other words, the reliability of the second epitaxial layer 400 is not affected by the first conductive layer 310 and the first dielectric layer 210. Furthermore, when the first epitaxial layer 200 and the second epitaxial layer 400 are formed of the same material, there may be no interface between the first epitaxial layer 200 and the second epitaxial layer 400.

[0061] In other embodiments, a second epitaxial layer 400 may be formed first on a substrate different from the substrate 100. Then, the second epitaxial layer 400 is bonded to the first epitaxial layer 200. Specifically, the upper surface of the second epitaxial layer 400 away from the substrate and the upper surface of the first epitaxial layer 200 away from the substrate 100 are brought into contact and bonded together. Afterward, the substrate is removed. Therefore, by separately forming the second epitaxial layer 400 on the substrate and then bonding it to the first epitaxial layer 200, the reliability of the second epitaxial layer 400 can be ensured.

[0062] Reference Figure 7 A second recess 401 is formed in the second epitaxial layer 400. In some embodiments, the second recess 401 may penetrate the second epitaxial layer 400 to expose a portion of the upper surface of the first conductive layer 310. In some embodiments, the second epitaxial layer 400 covers a portion of the upper surface of the first conductive layer 310, the upper surface of the first dielectric layer 210, and the upper surface of the first epitaxial layer 200. In some embodiments, the process for forming the second recess 401 may be the same as or different from the process for forming the first recess 201. In some embodiments, the second recess 401 is formed after the second epitaxial layer 400 is formed. In some embodiments, the second recess 401 and the first recess 201 are formed in different process passes.

[0063] In some embodiments, the second recess 401 has a third width W3 and a third depth D3. In some embodiments, such as Figure 2 The first width W1 of the first recess 201 shown is greater than that shown. Figure 7 The third width W3 of the second recess 401 shown. In some embodiments, the third depth D3 of the second recess 401 is substantially equal to... Figure 6 The second thickness T2 of the second epitaxial layer 400 shown.

[0064] Reference Figure 8 A second dielectric layer 410 is formed in the second recess 401. Specifically, the second dielectric layer 410 is formed on the lower surface and side surface of the second recess 401 and on the upper surface of the second epitaxial layer 400. The formation of the second dielectric layer 410 can achieve the effect of rounding the corners. In some embodiments, the second dielectric layer 410 can be formed by a deposition process or a thermal oxidation process. In embodiments where the second dielectric layer 410 is formed by a thermal oxidation process, the second dielectric layer 410 may further include a portion extending into the second epitaxial layer 400. The aforementioned portion of the second dielectric layer 410 extending into the second epitaxial layer 400 may cover a portion of the first conductive layer 310 and a portion of the first dielectric layer 210. The aforementioned portion of the second dielectric layer 410 extending into the second epitaxial layer 400 may be formed corresponding to the first conductive layer 310.

[0065] In some embodiments, when viewed in cross-sectional view, the width of the second dielectric layer 410 is between the width of the first conductive layer 310 and the width of the first dielectric layer 210. That is, the side surface of the second dielectric layer 410 is between the side surfaces of the first conductive layer 310 and the first dielectric layer 210. In some embodiments, the projection of the first conductive layer 310 onto the substrate 100 lies within the projection of the second dielectric layer 410 onto the substrate 100, and the projection of the second dielectric layer 410 onto the substrate 100 lies within the projection of the first dielectric layer 210 onto the substrate 100. Therefore, the side surfaces of the first dielectric layer 210 and the second dielectric layer 410 may have a distance between them. In some embodiments, the thickness of the second dielectric layer 410 may be adjusted according to electrical requirements. For example, the thickness of the second dielectric layer 410 may be less than the thickness of the first dielectric layer 210.

[0066] It should be noted that, in some embodiments, the first dielectric layer 210 and the second dielectric layer 410 can be considered as a single shielded dielectric layer. The width of the second dielectric layer 410 is smaller than the width of the first dielectric layer 210, and the thickness of the second dielectric layer 410 is smaller than the thickness of the first dielectric layer 210. In cross-sectional view, the first dielectric layer 210 and the second dielectric layer 410 may have a step-shape cross-section. When the shielded dielectric layer has a step-shape cross-section, the electric field distribution can be more uniform, thereby reducing the on-resistance and / or increasing the breakdown voltage of the semiconductor structure. When the shielded dielectric layer near the lower surface of the first recess 201 has a thicker thickness, the electric field concentrated at the lower surface of the first recess 201 can be reduced, resulting in a more uniform charge distribution. In some embodiments, since the semiconductor structure of this invention can have a lower on-resistance, the figure of merit (FOM) can be improved, thus providing better electrical characteristics.

[0067] Reference Figure 9 A portion of the second dielectric layer 410 is removed. Specifically, before the subsequent formation of the gate dielectric layer, a portion of the second dielectric layer 410 is removed from the side surface of the second recess 401 and the upper surface of the second epitaxial layer 400 to expose the side surface of the second recess 401 and the upper surface of the second epitaxial layer 400. In some embodiments, the second dielectric layer 410 is retained on the first conductive layer 310 and extends into the second epitaxial layer 400.

[0068] Reference Figure 10Similarly, a gate dielectric layer 420 is formed on the second epitaxial layer 400. Specifically, in some embodiments, the gate dielectric layer 420 may be formed on the second epitaxial layer 400 and the second dielectric layer 410. In some embodiments, the gate dielectric layer 420 may be silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, a combination thereof, or other suitable dielectric materials, but is not limited thereto. In some embodiments, the gate dielectric layer 420 may include an oxide. In some embodiments, the gate dielectric layer 420 and the first dielectric layer 210 and / or the second dielectric layer 410 may be formed using the same or different processes.

[0069] In some embodiments, the thickness of the gate dielectric layer 420 can be adjusted according to electrical requirements. For example, the thickness of the gate dielectric layer 420 may be less than the thicknesses of the first dielectric layer 210 and the second dielectric layer 410. In some embodiments, the gate dielectric layer 420 may form a second trench 402. In some embodiments, the shape of the second recess 401 corresponds to the shape of the second trench 402. The second trench 402 may have a fourth width W4 and a fourth depth D4. That is, the aspect ratio of the second trench 402 is the ratio of the fourth depth D4 to the fourth width W4. In some embodiments, the aspect ratio of the first trench 202 (the ratio of the second depth D2 to the second width W2) is less than the aspect ratio of the second trench 402 (the ratio of the fourth depth D4 to the fourth width W4).

[0070] In detail, the embodiment will be described in the case where the subsequently formed shielding electrode and gate electrode have substantially similar or identical lengths. First, since the first width W1 of the first recess 201 is greater than the third width W3 of the second recess 401, and the thickness of the first dielectric layer 210 is greater than the thickness of the gate dielectric layer 420, the second width W2 of the first trench 202 is greater than the second width W2 of the second trench 402. Furthermore, since the shielding electrode and gate electrode have substantially similar or identical lengths, the second depth D2 and the fourth depth D4 are substantially the same. Therefore, the aspect ratio of the first trench 202 is smaller than that of the second trench 402. Thus, compared to sequentially forming the shielding electrode and gate electrode in the same recess and / or trench, the embodiment of the present invention can improve the reliability of the material formed in the first trench 202 and the second trench 402 by independently providing the first epitaxial layer 200 and the second epitaxial layer 400 respectively. By adjusting the first epitaxial layer 200, the first recess 201, the second epitaxial layer 400, and the second recess 401, the reliability of the material formed in the first trench 202 and the second trench 402 can be further improved.

[0071] Reference Figure 11A second conductive material 500 is formed in the second trench 402 formed in the gate dielectric layer 420 to form the subsequent gate electrode. The second conductive material 500 can be formed directly on the gate dielectric layer 420. In some embodiments, the materials and processes used to form the second conductive material 500 may be the same as or different from the materials and processes used to form the first conductive material 300. In some embodiments, the second conductive material 500 may be polycrystalline silicon.

[0072] Reference Figure 12 The second conductive material 500 and the gate dielectric layer 420 are planarized to form a gate electrode 510 on the gate dielectric layer 420. In some embodiments, the planarization process may remove a portion of the second conductive material 500 to expose the upper surface of the gate dielectric layer 420. In some embodiments, the gate electrode 510 and the gate dielectric layer 420 are substantially coplanar. In some embodiments, the planarization process may be a chemical mechanical polishing process. In some embodiments, since the gate electrode 510 completely fills the second trench 402, the gate electrode 510 has a fourth width W4 corresponding to the second trench 402. In some embodiments, the fourth width W4 of the gate electrode 510 may be smaller than the second width W2 of the first conductive layer 310. In other words, the upper surface of the first conductive layer 310 is larger than the upper surface of the gate electrode 510. In some embodiments, the first conductive layer 310 and the gate electrode 510 are respectively formed in a first recess 201 and a second recess 401 formed by different processes.

[0073] It should be noted that in some embodiments, in the SGT-MOSFET obtained after subsequent processing, the first conductive layer 310 may be disposed below the gate electrode 510, thus the first conductive layer 310 can be regarded as a shielding electrode of the gate electrode 510. In some embodiments, the shielding electrode may be connected to the source electrode of the SGT-MOSFET obtained after subsequent processing, or the shielding electrode may be regarded as part of the source electrode of the SGT-MOSFET obtained after subsequent processing. In embodiments where the second width W2 of the first conductive layer 310 is greater than the fourth width W4 of the gate electrode 510, the area of ​​the active area between adjacent gate electrodes 510 can be increased. With a larger active area, more current can flow through the active area, thereby increasing the conduction current. In addition, a larger active area can provide a larger contact landing area, thus helping to reduce the problem of misalignment when forming contacts later, thereby improving the overall process window. For example, the process window of the back-end process can be improved.

[0074] Reference Figure 13A semiconductor layer 600 and a first doped region 610 are formed in the second epitaxial layer 400. The semiconductor layer 600 and the first doped region 610 are not disposed in the second recess 401. The semiconductor layer 600 and / or the first doped region 610 can be formed by ion implantation or diffusion processes, but are not limited to these. Additionally, the implanted dopants can be activated by a rapid thermal annealing (RTA) process.

[0075] Reference Figure 14 An interlayer dielectric layer 700 can be formed on the gate electrode 510. Specifically, the interlayer dielectric layer 700 can be formed on the gate dielectric layer 420 and the gate electrode 510. In some embodiments, the interlayer dielectric layer 700 can be formed using the same or different materials and processes as the first dielectric layer 210, the second dielectric layer 410 and / or the gate dielectric layer 420.

[0076] like Figure 14 As shown, a contact via can be further formed. In some embodiments, the contact via penetrates the interlayer dielectric layer 700, the gate dielectric layer 420, and the first doped region 610 to the semiconductor layer 600, but does not penetrate the semiconductor layer 600. Next, a second doped region 620 is formed below the contact via, thus reducing the number of times a patterned hard mask is used, thereby simplifying the process and reducing process costs. The second doped region 620 has a different conductivity type than the first doped region 610.

[0077] Subsequently, via materials are filled into the contact vias to form contact 800. In some embodiments, the via material may include a metallic material, a conductive material, other suitable materials, or a combination thereof. A metal layer 900 is then formed on the interlayer dielectric layer 700, making the metal layer 900 contact the contact 800 to obtain the semiconductor structure 1. In some embodiments, the metal layer 900 may include a metallic material, a conductive material, other suitable materials, or a combination thereof. The semiconductor structure 1 may be, or may be further processed, to serve as an SGT-MOSFET. In some embodiments, other further processes may be performed. In some embodiments, the formation method of the present invention can be applied to SGT-MOSFETs with the gate electrode and shield electrode adjacent to each other, and to SGT-MOSFETs with the shield electrode disposed below the gate electrode. In particular, the formation method of the present invention is applicable to SGT-MOSFETs with the shield electrode disposed below the gate electrode.

[0078] In some embodiments, the substrate 100, the first epitaxial layer 200, the second epitaxial layer 400, and the first doped region 610 may have a first conductivity type. The doping concentration of the first doped region 610 may be higher than the doping concentration of the substrate 100, the first epitaxial layer 200, and the second epitaxial layer 400. The semiconductor layer 600 and the second doped region 620 have a second conductivity type different from the first conductivity type. The doping concentration of the second doped region 620 may be higher than the doping concentration of the semiconductor layer 600. For example, when the substrate 100, the first epitaxial layer 200, and the second epitaxial layer 400 are N-type, and the semiconductor layer 600 is P-type, then the first doped region 610 may be a heavily doped N+ type, and the second doped region 620 may be a heavily doped P+ type. In other embodiments, when the substrate 100, the first epitaxial layer 200, and the second epitaxial layer 400 are P-type, and the semiconductor layer 600 is N-type.

[0079] In some embodiments, the first conductivity type and the second conductivity type can be adjusted as needed, and the doping concentration, doping depth, and size of the doped region can also be adjusted as needed. In some embodiments, the semiconductor layer 600 can also be formed in the second epitaxial layer 400 before the gate electrode is formed.

[0080] In summary, according to some embodiments of the present invention, the present invention utilizes a two-stage formation process—first forming a first epitaxial layer and then forming a second epitaxial layer—to reduce the aspect ratio of the trenches disposed in the first and second epitaxial layers, thereby improving the reliability of components disposed in the first and second epitaxial layers respectively. This avoids or reduces undesirable structures such as voids, cavities, seam defects, and / or depressions in the components, thus improving the overall electrical performance and reliability of the semiconductor structure. Furthermore, the present invention further improves the reliability of components disposed in the first epitaxial layer by making the aspect ratio of the first recess smaller than that of the second recess. Moreover, the present invention reduces on-resistance and / or increases the breakdown voltage of the semiconductor structure by using a shielding dielectric layer with a stepped cross-section. Additionally, the present invention increases the active region area by making the width of the first conductive layer larger than the width of the gate electrode, thereby increasing the on-current and process margin.

[0081] The scope of protection of this invention is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of this specification. Any person skilled in the art can understand, from the disclosure of some embodiments of this invention, current or future developed processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. Any such processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps that can perform substantially the same function or obtain substantially the same results in the embodiments described herein can be used according to some embodiments of this invention. Therefore, the scope of protection of this invention includes the aforementioned processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. Furthermore, each claim constitutes an individual embodiment, and the scope of protection of this invention also includes combinations of various claim claims and embodiments.

[0082] The above outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art can design or modify other processes and structures based on the embodiments of the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the embodiments of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the embodiments of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A first epitaxial layer is formed on a substrate; A first recess is formed in the first epitaxial layer; A first dielectric layer is formed in the first recess; A first conductive layer is formed on the first dielectric layer; A second epitaxial layer is formed on the first epitaxial layer; A second recess is formed in the second epitaxial layer to expose the upper surface of the first conductive layer; A second dielectric layer is formed on the lower and side surfaces of the second recess and on the upper surface of the second epitaxial layer, and a portion of the second dielectric layer extends into the second epitaxial layer; Similarly, a gate dielectric layer is formed on the second epitaxial layer; and A gate electrode is formed on the gate dielectric layer. The width of the first conductive layer is greater than the width of the gate electrode.

2. The forming method as described in claim 1, characterized in that, Prior to similarly forming the gate dielectric layer on the second epitaxial layer, the method further includes: A portion of the second dielectric layer is removed to expose the side surface of the second recess and the top surface of the second epitaxial layer.

3. The forming method as described in claim 1, characterized in that, Including: A semiconductor layer is formed in the second epitaxial layer; A first doped region is formed in the semiconductor layer; A dielectric layer is formed on the gate electrode; A second doped region is formed in the semiconductor layer; A contact is formed that extends through the interlayer dielectric layer and the first doped region to contact the second doped region; and A metal layer is formed on the interlayer dielectric layer, and the metal layer is electrically connected to the second doped region through the contact.

4. A semiconductor structure, characterized in that, include: A substrate having a first conductivity type; A first epitaxial layer having the first conductivity type is disposed on the substrate and includes a first recess; A first dielectric layer is disposed in the first recess; A first conductive layer is disposed on the first dielectric layer; A second epitaxial layer having the first conductivity type is disposed on the first epitaxial layer and includes a second recess; A gate dielectric layer is disposed in the second recess; A second dielectric layer is disposed between the first conductive layer and the gate dielectric layer, and a portion of the second dielectric layer extends into the second epitaxial layer; A gate electrode is disposed on the gate dielectric layer; and A semiconductor layer having a second conductivity type different from the first conductivity type is disposed in the second epitaxial layer but not in the second recess. The width of the first conductive layer is greater than the width of the gate electrode.

5. The semiconductor structure as described in claim 4, characterized in that, The thickness of the first epitaxial layer is greater than the thickness of the second epitaxial layer.

6. The semiconductor structure as described in claim 4, characterized in that, The doping concentration of the first epitaxial layer is greater than or equal to the doping concentration of the second epitaxial layer.

Images