A semiconductor device, a manufacturing method thereof, and a storage system

Abstract

Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and a storage system, wherein the manufacturing method comprises: providing a first wafer, forming a first bonding structure on the first wafer; the first bonding structure comprises a plurality of first pads, each of the first pads comprises a first buffer layer and a first conductive layer; the first buffer layer surrounds a sidewall of the first conductive layer; providing a second wafer, forming a second bonding structure on the second wafer; the second bonding structure comprises a plurality of second pads; and bonding the first wafer and the second wafer through the first pads and the second pads.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor device and its manufacturing method, and a memory system. Background Technology

[0002] In the field of integrated circuits, according to Moore's Law, the performance of an integrated circuit doubles for every doubling of the number of semiconductor devices packaged within it. In recent years, with the development of the semiconductor industry, the applicability of Moore's Law has reached its limit. As market demands for electronic devices and products shift towards miniaturization and multifunctionality, the semiconductor field has seen the emergence of many new technologies, designs, and processes. Three-dimensional stacked semiconductor device architecture is one such example, as it can overcome the density limitations of planar semiconductor devices. Summary of the Invention

[0003] In view of this, the main objective of this disclosure is to provide a semiconductor device and a method for manufacturing the same, as well as a memory system.

[0004] To achieve the above objectives, the technical solution disclosed herein is implemented as follows: According to a first aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: A first wafer is provided, and a first bonding structure is formed on the wafer; The first bonding structure includes a plurality of first pads, each first pad including a first buffer layer and a first conductive layer; the first buffer layer surrounds the sidewall of the first conductive layer; A second wafer is provided, and a second bonding structure is formed on the second wafer; the second bonding structure includes a plurality of second pads; The first wafer and the second wafer are bonded using the first pad and the second pad.

[0005] In the above scheme, the first wafer includes a first substrate and a first interconnect structure layer formed on the first substrate, and the formation of the first bonding structure on the first wafer includes: A first dielectric layer is formed on the first interconnect structure layer; A first bonding plug and a first pad are formed in the first dielectric layer to form a plurality of electrical connections; the first bonding plug and a first interconnect structure in the first interconnect structure layer are electrically connected, and the first bonding plug and the first pad constitute the first bonding structure.

[0006] In the above scheme, the first bonding plug and the first pad forming a plurality of electrical connections in the first dielectric layer include: A first sublayer is formed on the first interconnect structure layer, and a plurality of first bonding plugs are formed in the first sublayer; A second sublayer is formed on the first sublayer, and the second sublayer is etched to form a first opening, the first opening exposing at least the first bonding plug; Forming the first buffer layer that fills the first opening; A second opening is formed in the first buffer layer, the second opening exposing the first bonding plug; The first conductive layer is formed to fill the second opening.

[0007] In the above scheme, before forming the first buffer layer that fills the first opening, the following steps are included: A first barrier layer is formed covering the inner wall of the first opening; The first barrier layer at the bottom of the first opening is etched away to expose the first bonding plug.

[0008] In the above scheme, the manufacturing process of the second bonding structure is the same as that of the first bonding structure.

[0009] In the above scheme, each second pad includes a second buffer layer and a second conductive layer; the second buffer layer surrounds the sidewall of the second conductive layer.

[0010] In the above scheme, the materials of the first buffer layer and the second buffer layer include insulating materials.

[0011] According to a second aspect of the present disclosure, a semiconductor device is provided, comprising: A first wafer has a first bonding structure; the first bonding structure includes a plurality of first pads, each first pad including a first buffer layer and a first conductive layer; the first buffer layer surrounds the sidewalls of the first conductive layer. The second wafer has a second bonding structure, which includes a plurality of second pads; the second wafer is bonded to the first wafer through the first pads and the second pads.

[0012] In the above scheme, the first wafer includes a first substrate and a first interconnect structure layer formed on the first substrate; the first bonding structure further includes a plurality of first bonding plugs electrically connected to the first pad, and the first bonding plugs are electrically connected to the first interconnect structure in the first interconnect structure layer.

[0013] In the above scheme, each of the first pads further includes: A first barrier layer surrounds the sidewalls and bottom of the first buffer layer and the portion of the bottom of the first conductive layer that is not in contact with the first bonding plug.

[0014] In the above scheme, the second bonding structure is the same as the first bonding structure.

[0015] In the above scheme, each second pad includes a second buffer layer and a second conductive layer; the second buffer layer surrounds the sidewall of the second conductive layer.

[0016] In the above scheme, the materials of the first buffer layer and the second buffer layer include insulating materials.

[0017] In the above scheme, the semiconductor device includes dynamic random access memory.

[0018] According to a third aspect of the present disclosure, a storage system is provided, the storage system comprising: At least one semiconductor device as described above; and A controller coupled to the semiconductor device and configured to control the semiconductor device.

[0019] The semiconductor device manufacturing method provided in this disclosure realizes a three-dimensional stacked semiconductor device architecture through a bonding process, effectively improving the integration density of the semiconductor device. When forming the first bonding pad, a first buffer layer is provided surrounding the sidewalls of the first conductive layer to release adverse stress generated by the first conductive layer during wafer bonding, effectively improving bonding defects and enhancing the performance and yield of the semiconductor device. Attached Figure Description

[0020] Figures 1A to 1E A partial cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of this disclosure; Figure 2 A schematic diagram illustrating the specific implementation flow of another method for forming a semiconductor device provided in this disclosure embodiment; Figures 3A to 3L A cross-sectional structural schematic diagram of the formation process of another semiconductor device provided in an embodiment of this disclosure; Figure 4 This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this disclosure. Detailed Implementation

[0021] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0022] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0023] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0025] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0026] In manufacturing semiconductor devices using 3D integration technology, separate wafers are first used to fabricate a portion of the circuitry. These wafers with the circuitry are then bonded together, and the circuits on the wafers are interconnected to form a complete circuit system. Hybrid bonding is a crucial step in realizing the architecture of 3D stacked semiconductor devices. Hybrid bonding simultaneously connects circuit leads during the wafer bonding process. Therefore, hybrid bonding technology can provide higher interconnect density, smaller and simpler circuits, greater bandwidth, and lower power consumption.

[0027] Figures 1A to 1E This is a partial cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of this disclosure.

[0028] like Figure 1A As shown, a first wafer 100 is provided, which can be an array wafer or a CMOS wafer. Exemplarily, the material of the first wafer 100 can include elemental semiconductor materials, such as silicon (Si), germanium (Ge), etc., or compound semiconductor materials, such as gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc. It should be noted that the first wafer 100 may also include other circuits or devices such as interconnect structures, control circuits, and stacked structures, which are not shown in the figure.

[0029] A first sub-dielectric layer 103 is formed on a first wafer 100. A plurality of conductive plugs 101 and wiring layers 102 are formed in the first sub-dielectric layer 103, and the conductive plugs 101 and wiring layers 102 are electrically connected. Exemplarily, the material of the first sub-dielectric layer 103 includes, but is not limited to, silicon oxide or silicon nitride. The materials of the conductive plugs 101 and wiring layers 102 include, but are not limited to, copper, aluminum, or tungsten.

[0030] A second sub-dielectric layer 104 is formed on the first sub-dielectric layer 103. The material of the second sub-dielectric layer 104 includes, but is not limited to, silicon oxide or silicon nitride. The materials of the second sub-dielectric layer 104 and the second sub-dielectric layer 103 can be the same or different. The first sub-dielectric layer 103 and the second sub-dielectric layer 104 constitute the first bonding layer 105.

[0031] A portion of the second sub-dielectric layer 104 is removed to form a groove 106, which exposes at least the top surface of the conductive plug 101. The groove 106 can be formed by photolithography and etching processes.

[0032] like Figure 1BAs shown, a metallic material layer 107 is deposited to form a metal material layer, the material of which includes, but is not limited to, copper, aluminum, or tungsten. Exemplarily, the specific steps for depositing a copper layer include: forming a copper seed layer covering the inner wall of the groove 106; and performing copper electroplating on the copper seed layer to fill the groove 106 with copper.

[0033] like Figure 1C As shown, the metal material layer 107 is planarized by chemical mechanical polishing (CMP) to remove the metal material layer 107 outside the groove 106 and form the first bonding pad 108.

[0034] like Figure 1D As shown, a second wafer 200 is provided, on which a second bonding layer 201 identical to the first bonding layer 105 is provided, and a second bonding pad 202 in the second bonding layer 201 is formed using the same fabrication process as the first bonding pad 108.

[0035] like Figure 1E As shown, a hybrid bonding method is used to bond the first wafer 100 and the second wafer 200 through the first bonding pad 108 and the second bonding pad 202, forming an interface 210. When the first wafer 100 is a memory array wafer, the second wafer 200 can be a peripheral circuit wafer. For example, the first bonding pad of the memory array wafer can be coupled to a bit line or a word line, and the second bonding pad of the peripheral circuit wafer can be coupled to a write circuit or a read circuit, etc. After the first bonding pad and the second bonding pad of the memory array wafer and the peripheral circuit wafer are bonded, the peripheral circuit can control and operate the memory array, for example, the peripheral circuit controls the memory array to write data or read data, etc.

[0036] Hybrid bonding technology has significantly improved the performance and area utilization of semiconductor devices. Because hybrid bonding involves both metal and insulating materials at the interface 210, high-temperature annealing is required to ensure stable bonding between metals and between insulating materials. However, while high-temperature annealing increases bond strength, the difference in thermal expansion coefficients between the metal and insulating materials means that the metal portion of the wafer requires more expansion space than the insulating portion after annealing. This results in insufficient thermal stress release on the first and second bonding pads in the metal portion, leading to an increase in voids 211 within the first and second bonding pads. Ultimately, this causes defects such as metal damage and unevenness at the interface 210, resulting in abnormal bonding connections, product defects, or reliability issues.

[0037] Furthermore, during the planarization process of the metal material layer using CMP to form the first bonding pad or the second bonding pad, an electrochemical reaction occurs on the surface of the first bonding pad or the second bonding pad, which inevitably causes some protrusions to form on the surface of the first bonding pad or the second bonding pad. These protrusions will cause longitudinal diffusion of adverse stress during wafer bonding, which will reduce the performance of semiconductor devices and affect the yield of semiconductor devices.

[0038] Therefore, this disclosure provides a semiconductor device and a method for manufacturing the same.

[0039] Figure 2 This is a schematic diagram illustrating the specific implementation flow of another method for forming a semiconductor device provided in this disclosure. For example... Figure 2 As shown, the specific steps of the method for forming this semiconductor device include: Step S10: Provide a first wafer and form a first bonding structure on the first wafer; The first bonding structure includes a plurality of first pads, each first pad including a first buffer layer and a first conductive layer; the first buffer layer surrounds the sidewall of the first conductive layer; Step S20: Provide a second wafer and form a second bonding structure on the second wafer; the second bonding structure includes a plurality of second pads; Step S30: Bond the first wafer and the second wafer using the first pad and the second pad.

[0040] Figures 3A to 3L This is a cross-sectional structural schematic diagram of the formation process of another semiconductor device provided in an embodiment of this disclosure. It should be understood that... Figures 3A to 3L The operations shown are not necessarily performed precisely in order. The sequence of steps can be adjusted according to the actual situation, or other operations can be added to the preparation process, or one or more steps can be removed. The following section combines... Figure 2 and Figures 3A to 3L This embodiment describes a method for manufacturing a semiconductor device.

[0041] like Figure 3A As shown, a first wafer 300 is provided, which includes a first substrate 301 and a first interconnect structure layer 302 formed on the first substrate 301. Exemplarily, the first substrate 301 can be a single-element semiconductor material substrate (e.g., a silicon substrate, germanium substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon substrate, etc.), or a silicon-on-insulator (SOI) substrate, germanium-on-insulator (GeOI) substrate, etc.

[0042] In some embodiments, the first wafer 300 may further include a first device layer (not shown) on a first substrate 301. In some embodiments, the first wafer 300 is a memory array wafer or a peripheral circuit wafer, and the first device layer includes a memory array or peripheral circuit.

[0043] In some embodiments, the first interconnect structure layer 302 is located above the first device layer. A first interconnect structure 303 is formed in the first interconnect structure layer 302 and is electrically connected to the first device layer to transmit electrical signals within the first wafer 300.

[0044] For example, the material of the first interconnect structure 303 may include conductive materials, including but not limited to tungsten, copper, cobalt, aluminum, silicides or any combination thereof.

[0045] For example, the first interconnect structure layer 302 can be a single layer or a stacked structure, and the material of the first interconnect structure layer 302 includes, but is not limited to, one or more of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride or silicon oxycarbide.

[0046] Figures 3B to 3J The process of forming the first bonding structure on the first interconnect structure layer is shown.

[0047] like Figure 3B As shown, a first sublayer 306 is formed on the first interconnect structure layer 302. The material of the first sublayer 306 includes, but is not limited to, one or more of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. Exemplarily, the first sublayer 306 can be deposited using one or more thin film deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), any other suitable process, or combinations thereof.

[0048] A plurality of first bonding plugs 304 and a plurality of first wiring layers 305 electrically connected to the first bonding plugs 304 are formed in the first sublayer 306. The materials of the first bonding plugs 304 and the first wiring layers 305 include, but are not limited to, copper, aluminum, tungsten or tin.

[0049] In some embodiments, the first bonding plug 304 and the first interconnect structure 303 in the first interconnect structure layer 302 are electrically connected. It is understood that the first bonding plug 304 is electrically connected to the first device layer via the first interconnect structure 303.

[0050] like Figure 3CAs shown, a second sublayer 307 is formed on the first sublayer 306, and the first sublayer 306 and the second sublayer 307 constitute the first dielectric layer 308. The material of the second sublayer 307 includes, but is not limited to, one or more of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide, and the materials of the first sublayer 306 and the second sublayer 307 may be the same or different. The second sublayer 307 can be deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, any other suitable process, or combinations thereof.

[0051] The second sublayer 307 is etched to form a first opening 309, which at least exposes the first bonding plug 304. Here, electron beam lithography, plasma etching, or reactive ion etching can be used to etch the second sublayer 307 to form the first opening 309, and the embodiments disclosed herein are not limited to this.

[0052] like Figure 3D As shown, a first barrier layer 310 is formed covering the inner wall of the first opening 309. In some embodiments, the material of the first barrier layer 310 includes silicon nitride, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof.

[0053] like Figure 3E As shown, etching removes the first barrier layer 310 outside the first opening 309 and a portion of the first barrier layer 310 at the bottom of the first opening 309 to expose the first bonding plug 304. The etching can be dry etching or wet etching, such as plasma etching or solution etching, etc., and the embodiments disclosed herein are not limited to these methods.

[0054] like Figure 3F As shown, a first buffer material layer 311 is deposited, and the material of the first buffer material layer 311 includes an insulating material, such as silicon oxide. The first buffer material layer 311 can be deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, any other suitable process, or combinations thereof.

[0055] like Figure 3G As shown, the first buffer material layer 311 outside the first opening 309 is removed by CMP process to form a first buffer layer 312 that fills the first opening 309. The top of the first buffer layer 312 is flush with the top of the second sub-layer 307.

[0056] like Figure 3H As shown, a second opening 313 is formed in the first buffer layer 312, exposing the first bonding plug 304. Here, electron beam lithography, plasma etching, or reactive ion etching can be used to etch the first buffer layer 312 to form the second opening 313, and this embodiment is not limited thereto.

[0057] like Figure 3I As shown, a first conductive material layer 314 is deposited to form the first conductive material layer 314. The material of the first conductive material layer 314 can be copper, aluminum, or other suitable materials. The first conductive material layer 314 can be formed by electroplating or chemical plating. In other specific embodiments, the first conductive material layer 314 can also be formed by methods other than electroplating, such as sputtering or evaporation deposition.

[0058] In this embodiment of the disclosure, when the second sub-layer is etched to form the first opening, the space for contact between the first conductive layer and the first bonding plug is predefined, so that there is sufficient contact area between the first conductive layer and the first bonding plug, thereby ensuring the electrical connection effect between the first conductive layer and the first bonding plug.

[0059] like Figure 3J As shown, the first conductive material layer 314 is planarized using a CMP process, removing the first conductive material layer 314 located outside the second opening 313, forming a first conductive layer 315 filling the second opening 313. The first barrier layer 310, the first buffer layer 312, and the first conductive layer 315 constitute the first pad 316, with the top of the first pad 316 flush with the top of the second dielectric layer 307. The electrically connected first bonding plug 304 and the first pad 316 constitute the first bonding structure 317.

[0060] Because a first buffer layer is provided surrounding the sidewalls of the first conductive layer during the formation of the first pad, adverse stress can be effectively released during subsequent wafer bonding, avoiding or reducing the formation of voids. Furthermore, by providing a first barrier layer outside the first buffer layer, the release of adverse stress is concentrated at the first pad, preventing adverse stress from affecting other areas.

[0061] In other embodiments, such as Figure 4 As shown, the first wiring layer 305 has the same structure as the first pad 316, which can further enhance the buffering effect against adverse stress.

[0062] In the embodiments disclosed herein, such as Figure 3K As shown, a second wafer 400 is provided, and a second bonding structure 413 is formed on the second wafer 400 using the same fabrication process as the first bonding structure 317. The second bonding structure 413 includes a plurality of second pads 412.

[0063] In some embodiments, the second wafer 400 includes a second substrate 401 and a second interconnect structure layer 402 formed on the second substrate 401. Exemplarily, the second substrate 401 may be a single-element semiconductor material substrate (e.g., a silicon substrate, germanium substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon substrate, etc.), or a silicon-on-insulator substrate, a germanium-on-insulator substrate, etc.

[0064] In some embodiments, the second interconnect structure 403 is formed in the second interconnect structure layer 402.

[0065] In some embodiments, the second bonding structure 413 is formed in the second dielectric layer 408, which includes a third sublayer 406 and a fourth sublayer 407. The third sublayer 406 contains a plurality of second bonding plugs 404 and a plurality of second wiring layers 405 electrically connected to the second bonding plugs 404. The fourth sublayer 407 contains a plurality of second pads 412 electrically connected to the second bonding plugs 404.

[0066] In some embodiments, each second pad 412 includes a second buffer layer 410 and a second conductive layer 411; the second buffer layer 410 surrounds the sidewall of the second conductive layer 411.

[0067] In one specific embodiment, each second pad 412 further includes a second barrier layer 409 that surrounds the sidewalls and bottom of the second buffer layer 410 and the portion of the bottom of the second conductive layer 411 that is not in contact with the second bonding plug 404. The material of the second barrier layer 409 includes silicon nitride, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof.

[0068] In some embodiments, the material of the second buffer layer 410 includes an insulating material. The material of the second buffer layer 410 may be the same as or different from the material of the first buffer layer 312. For example, the material of the second buffer layer 410 and the material of the first buffer layer 312 are both silicon oxide.

[0069] In some embodiments, the fabrication of the first bonding structure 317 and the second bonding structure 413 can be carried out simultaneously.

[0070] like Figure 3L As shown, the first wafer 300 and the second wafer 400 are bonded together via the first pad 316 and the second pad 412. Exemplarily, when the first wafer 300 is a memory array wafer, the second wafer 400 can be a peripheral circuit wafer. A first device layer is present on the first substrate 301, and a second device layer is present on the second substrate 401, wherein the first device layer is the memory array and the second device layer is the peripheral circuit. In some embodiments, the second device layer may include one or more of the following: a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver, or any active or passive component of the circuitry (e.g., a transistor, diode, resistor, or capacitor).

[0071] Electrical signal transmission between the first wafer 300 and the second wafer 400 is achieved through the first interconnect structure 303, the first bonding plug 304, the first wiring layer 305, the first pad 316 and the second pad 412, the second wiring layer 405, the second bonding plug 404, and the second interconnect structure 403.

[0072] In some embodiments, the first bonding plug 304 and the second bonding plug 404 can be through-silicon vias (TSVs) or vias. For example, when the front side of the first wafer 300 is bonded to the second wafer 400, the first bonding plug 304 and the second bonding plug 404 can be vias. Here, the front side of the first wafer 300 refers to the side of the first substrate 301 where the memory array or peripheral circuitry is formed, and the back side of the first wafer 300 is opposite to the front side.

[0073] For two wafers to be bonded, when forming the first pad on the first wafer, a first buffer layer is provided surrounding the sidewalls of the first conductive layer. This effectively mitigates the impact of post-bonding annealing on the first pad, reducing or avoiding void formation. The second wafer also uses the same manufacturing process to form the second pad with the same structure, further improving the yield of semiconductor devices without requiring additional steps or time.

[0074] This disclosure also discloses a semiconductor device, which can be found in the following embodiments. Figure 3L The following will combine Figures 3J to 3L The semiconductor device described in this embodiment includes: A first wafer 300 has a first bonding structure 317; the first bonding structure 317 includes a plurality of first pads 316, each first pad 316 including a first buffer layer 312 and a first conductive layer 315; the first buffer layer 312 surrounds the sidewall of the first conductive layer 315. The second wafer 400 has a second bonding structure 413, which includes a plurality of second pads 412. The second wafer 400 is bonded to the first wafer 300 through a first pad 316 and a second pad 412.

[0075] In this embodiment of the disclosure, the first wafer 300 includes a first substrate 301 and a first interconnect structure layer 302 formed on the first substrate 301.

[0076] The first bonding structure 317 further includes a plurality of first bonding plugs 304 electrically connected to the first pads 316, and the first bonding plugs 304 are electrically connected to the first interconnect structure 303 in the first interconnect structure layer 302. The first bonding structure 317 is located in the first dielectric layer 308, wherein the first dielectric layer 308 includes a first sublayer 306 and a second sublayer 307. The first bonding plugs 304 are located in the first sublayer 306, and the first pads 316 are located in the second sublayer 307.

[0077] In some embodiments, a plurality of first wiring layers 305 electrically connected to the first bonding plug 304 are further formed in the first sub-layer 306. The materials of the first bonding plug 304 and the first wiring layers 305 include, but are not limited to, copper, aluminum, tungsten, or tin.

[0078] In this embodiment of the disclosure, each first pad 316 further includes: The first barrier layer 310 surrounds the sidewalls and bottom of the first buffer layer 312 and the portion of the bottom of the first conductive layer 315 that is not in contact with the first bonding plug 304.

[0079] In this embodiment of the disclosure, the second wafer 400 includes a second substrate 401 and a second interconnect structure layer 402 formed on the second substrate 401.

[0080] In this embodiment of the disclosure, the second bonding structure 413 has the same structure as the first bonding structure 317.

[0081] The second bonding structure 413 further includes a plurality of second bonding plugs 404 electrically connected to the second pad 412, and the second bonding plugs 404 are electrically connected to the second interconnect structure 403 in the second interconnect structure layer 402. The second bonding structure 413 is located in the second dielectric layer 408, wherein the second dielectric layer 408 includes a third sublayer 406 and a fourth sublayer 407. The second bonding plugs 404 are located in the third sublayer 406, and the second pads 412 are located in the fourth sublayer 407.

[0082] In some embodiments, a plurality of second wiring layers 405 electrically connected to the second bonding plug 404 are also formed in the third sub-layer 406.

[0083] In this embodiment of the disclosure, each second pad 412 includes a second buffer layer 410 and a second conductive layer 411; the second buffer layer 410 surrounds the sidewall of the second conductive layer 411.

[0084] In this embodiment of the disclosure, the materials of the first buffer layer 312 and the second buffer layer 410 include insulating materials.

[0085] In some embodiments, the semiconductor device described above can be Dynamic Random Access Memory (DRAM). Of course, the semiconductor device can also be other types of memory, such as Static Random Access Memory (SRAM), 3D NAND flash memory, Phase Change Memory (PCM), Electrically Erasable Programmable Read-Only Memory (EEPROM), NOR flash memory, Phase Change Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), Ferro-electric Random Access Memory (FRAM), etc.

[0086] This disclosure also discloses a storage system, which includes: At least one semiconductor device disclosed in the above embodiments; and A controller coupled to the semiconductor device and configured to control the semiconductor device.

[0087] In some implementations, the storage system includes mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable electronic devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having semiconductor devices therein.

[0088] The controller is coupled to a semiconductor device and configured to control that semiconductor device. In some embodiments, the controller is designed for use in other media in electronic devices such as personal calculators, digital cameras, mobile phones, etc. The controller may also perform any other suitable function, such as formatting the semiconductor device. Specifically, the controller may be implemented by a microprocessor, microcontroller (also known as a microcontroller unit (MCU)), central processing unit (CPU), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic device (PLD), state machine, gated logic unit, discrete hardware circuitry, or combinations thereof, as well as other suitable hardware, firmware, and / or software configured to perform the various functions described in the above description.

[0089] In some implementations, the semiconductor device may include an interface for communicating with a controller. For example, the semiconductor device may include a DRAM interface.

[0090] The semiconductor device manufacturing method provided in this disclosure realizes a three-dimensional stacked semiconductor device architecture through a bonding process, effectively improving the integration density of the semiconductor device. When forming the first bonding pad, a first buffer layer is provided surrounding the sidewalls of the first conductive layer to release adverse stress generated by the first conductive layer during wafer bonding, effectively improving bonding defects and enhancing the performance and yield of the semiconductor device.

[0091] It should be understood that the phrases "an embodiment" or "some embodiments" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in an embodiment" or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0092] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A first wafer is provided, the first wafer including a first substrate and a first interconnect structure layer formed on the first substrate; A first bonding structure is formed in a first dielectric layer on the first interconnect structure layer; The first bonding structure includes a plurality of first pads, a plurality of first bonding plugs, and a plurality of first wiring layers electrically connected to the first bonding plugs. The first bonding plugs are electrically connected to the first interconnect structure in the first interconnect structure layer. The first wiring layer has the same structure as the first pad. Each first pad includes a first buffer layer and a first conductive layer. The first buffer layer surrounds the sidewall of the first conductive layer. A second wafer is provided, the second wafer including a second substrate and a second interconnect structure layer formed on the second substrate; A second bonding structure is formed in a second dielectric layer on the second interconnect structure layer; the second bonding structure includes a plurality of second pads, a plurality of second bonding plugs, and a plurality of second wiring layers electrically connected to the second bonding plugs, the second bonding plugs being electrically connected to the second interconnect structure in the second interconnect structure layer; the second wiring layers have the same structure as the second pads; each second pad includes a second buffer layer and a second conductive layer; the second buffer layer surrounds the sidewall of the second conductive layer. The first wafer and the second wafer are bonded using the first pad and the second pad.

2. The manufacturing method according to claim 1, characterized in that, The formation of a first bonding structure in a first dielectric layer on the first interconnect structure layer includes: A first sublayer is formed on the first interconnect structure layer, and a plurality of first bonding plugs are formed in the first sublayer; A second sublayer is formed on the first sublayer, and the second sublayer is etched to form a first opening, the first opening exposing at least the first bonding plug; Forming the first buffer layer that fills the first opening; A second opening is formed in the first buffer layer, the second opening exposing the first bonding plug; The first conductive layer is formed to fill the second opening.

3. The manufacturing method according to claim 2, characterized in that, Before forming the first buffer layer that fills the first opening, the process includes: A first barrier layer is formed covering the inner wall of the first opening; The first barrier layer at the bottom of the first opening is etched away to expose the first bonding plug.

4. The manufacturing method according to claim 3, characterized in that, The second bonding structure is manufactured using the same process as the first bonding structure.

5. The manufacturing method according to claim 1, characterized in that, The materials of the first buffer layer and the second buffer layer include insulating materials.

6. A semiconductor device, characterized in that, include: The first wafer includes a first substrate and a first interconnect structure layer formed on the first substrate; The first dielectric layer on the first interconnect structure layer has a first bonding structure; the first bonding structure includes a plurality of first pads, a plurality of first bonding plugs, and a plurality of first wiring layers electrically connected to the first bonding plugs, the first bonding plugs being electrically connected to the first interconnect structure in the first interconnect structure layer; the first wiring layers have the same structure as the first pads; each first pad includes a first buffer layer and a first conductive layer; the first buffer layer surrounds the sidewall of the first conductive layer. The second wafer includes a second substrate and a second interconnect structure layer formed on the second substrate; The second dielectric layer on the second interconnect structure layer has a second bonding structure, which includes a plurality of second pads, a plurality of second bonding plugs, and a plurality of second wiring layers electrically connected to the second bonding plugs. The second bonding plugs are electrically connected to the second interconnect structure in the second interconnect structure layer. The second wiring layer has the same structure as the second pad. Each second pad includes a second buffer layer and a second conductive layer. The second buffer layer surrounds the sidewall of the second conductive layer. The second wafer is bonded to the first wafer through the first pad and the second pad.

7. The semiconductor device according to claim 6, characterized in that, Each of the first pads also includes: A first barrier layer surrounds the sidewalls and bottom of the first buffer layer and the portion of the bottom of the first conductive layer that is not in contact with the first bonding plug.

8. The semiconductor device according to claim 6, characterized in that, The second bonding structure is identical to the first bonding structure.

9. The semiconductor device according to claim 6, characterized in that, The materials of the first buffer layer and the second buffer layer include insulating materials.

10. The semiconductor device according to claim 8, characterized in that, The semiconductor device includes dynamic random access memory.

11. A storage system, characterized in that, The storage system includes: At least one semiconductor device as described in any one of claims 6-10; and A controller coupled to the semiconductor device and configured to control the semiconductor device.

Images