Parallel packaging structure of semiconductor device and manufacturing method thereof

Abstract

The application relates to the field of gallium nitride power devices, in particular to a parallel packaging structure of a semiconductor device and a manufacturing method. A plurality of gallium nitride power device dies are selected, a die packaging structure is formed after a fan-out packaging process, the plurality of gallium nitride power device dies in the die packaging structure are connected in parallel through a redistribution layer, the source, the drain and the gate of the gallium nitride power device dies are connected in parallel, double-chip parallel connection is realized, the resistance of the gallium nitride power device is reduced, and the performance of the gallium nitride power device is improved. Meanwhile, an electrical design is added to the layout of the redistribution layer, the length of a power loop is reduced, the electromagnetic interference between the power loops of the source, the gate and the drain is reduced, the resistance in the circuit is reduced, the parasitic inductance is reduced, the electric energy is reduced, the gallium nitride power device is used as a high-frequency switching device, the loss in switching is greatly reduced, and the working efficiency of a commutation loop is increased.

Description

Technical Field

[0001] This invention relates to the field of gallium nitride power devices, and particularly to a parallel packaging structure and fabrication method for a semiconductor device. Background Technology

[0002] Gallium nitride (GaN) is a mature third-generation semiconductor material, also known as a wide-bandgap semiconductor. It possesses advantages such as a large bandgap, high breakdown electric field, high saturation electron velocity, high thermal conductivity, stable chemical properties, and strong radiation resistance, making it one of the preferred materials for high-temperature, high-frequency, and high-power microwave devices. Currently, it is mainly used in the field of gallium nitride power devices, and it also has great potential for future applications in high-frequency communications.

[0003] With the rapid development of electronic information technology and the continuous improvement of people's consumption level, the functions of individual electronic devices are becoming more diversified and their size is becoming smaller. This has led to an increase in the density of chips and functional components in the internal structure of electronic devices, while the critical dimensions are decreasing. This poses a great challenge to the semiconductor packaging industry.

[0004] Please refer to Figure 1 Currently, the main packaging method for gallium nitride (GaN) power devices is the packaging of single-transistor GaN power devices, with surface mount technology being the most common. This packaging method involves attaching the bottom of the GaN power device die to a frame substrate island using silver paste. Then, the source, drain, and gate regions on the GaN power device die are electrically connected via metal leads and pins on the lead frame. Finally, the GaN power device die and lead frame are encapsulated and fixed using materials such as epoxy resin molding compound.

[0005] This method ultimately encapsulates most of the structure of the gallium nitride power device, including the die, metal leads, and lead frame, using a specific molding die, exposing the pins of the lead frame and the bottom heat sink. Then, through a final cutting process, the entire frame is divided into an independent gallium nitride power device, which is then sent to the testing process for functional testing and screening.

[0006] Currently, gallium nitride (GaN) power devices are pursuing miniaturization, high performance, and higher integration in applications to meet the development needs of modern devices. One approach is to redesign higher-performance GaN power chips. However, the current process for producing higher-performance GaN wafers faces the technical problem of ultra-low yield, which greatly increases the overall cost. Another approach is to package two GaN power devices and connect them in parallel. However, the traditional dual-chip parallel connection scheme faces packaging problems such as increased packaging area, large parasitic inductance, and cross-bonding. Summary of the Invention

[0007] To address the technical problem of packaging defects in traditional gallium nitride power devices, this invention provides a parallel packaging structure for semiconductor devices and a method for fabricating them.

[0008] To achieve the above objectives, the present invention provides a parallel packaging structure for a semiconductor device, comprising:

[0009] Die-to-die packaging structure, lead frame; The die packaging structure is formed by multiple gallium nitride power device dies through a fan-out packaging process. The multiple gallium nitride power device dies have a parallel structure, and the die packaging structure has a source pin structure, a drain pin structure, and a gate pin structure. The lead frame includes a frame base island and pins; The die package structure is bonded to the frame base island, and the source pin structure, drain pin structure, gate pin structure of the die package structure are electrically connected to the pins of the lead frame.

[0010] Optionally, the plurality of gallium nitride power device chips may be two gallium nitride power device chips.

[0011] Optionally, the on-resistance of the die-package structure is equal to R, where R is the on-resistance of a single gallium nitride power device die.

[0012] Optionally, the die packaging structure specifically includes: a redistribution layer, multiple gallium nitride power device dies located on the surface of the redistribution layer, and a molding compound encapsulating the multiple gallium nitride power device dies; The gallium nitride power device die includes a front side with a functional layer and a back side with an opposite functional layer. The front side of the multiple gallium nitride power device dies is disposed opposite to the redistribution layer, and the gate, source, and drain of the front side of the gallium nitride power device die are electrically connected to the gate pin structure, source pin structure, and drain pin structure of the redistribution layer through the redistribution layer.

[0013] Optionally, the redistribution layer encloses and isolates the gates of multiple gallium nitride power device dies within the sources of the multiple gallium nitride power device dies, and the redistribution layer between the sources of the multiple gallium nitride power device dies has multiple openings.

[0014] Optionally, the spacing between the drain and source of the multiple gallium nitride power device chips is greater than 350 micrometers.

[0015] Optionally, the redistribution layer on one side of the drain pin structure of the die package structure has a concave-convex structure, which has a recessed portion and a raised portion, and the recessed portion is the welding area of ​​the drain of the gallium nitride power device die.

[0016] This invention also provides a method for fabricating a parallel packaging structure for a semiconductor device, comprising: Provide multiple gallium nitride power device dies, the multiple gallium nitride power device dies including a front side having a functional layer and a back side having a relative functional layer; The front sides of the multiple gallium nitride power device chips are attached to the surface of the carrier board, with the gates of the multiple gallium nitride power device chips facing each other and the sources facing each other, and the front sides of the multiple gallium nitride power device chips are in the same plane. The back of the multiple gallium nitride power device chips is filled with a molding compound for encapsulation. Remove the carrier plate; A redistribution layer is formed on the front side of the multiple gallium nitride power device dies. The redistribution layer has a gate pin structure, a source pin structure, and a drain pin structure. The gate, source, and drain on the front side of the multiple gallium nitride power device dies are electrically connected to the gate pin structure, source pin structure, and drain pin structure of the redistribution layer. The multiple gallium nitride power device dies after the redistribution layer is formed are cut to the target size to form a die package structure of the target size; The die package structure is attached to the frame base island, and the source pin structure, drain pin structure, gate pin structure of the die package structure and the pins of the lead frame are electrically connected. The die packaging structure and lead frame are then packaged.

[0017] Optionally, the die packaging structure is formed by fan-out packaging of the two gallium nitride power device dies. The parallel packaging structure formed by the gallium nitride power device dies after fan-out packaging is applied to one of the following packaging types: DFN packaging, TO220, TO247, BGA, LGA, PLP, and ECP.

[0018] Optionally, it also includes: thinning the back side of the plurality of gallium nitride power device dies after the redistribution layer is formed to the target thickness of the die package structure.

[0019] In summary, the advantages and beneficial effects of the present invention are as follows: This invention provides a parallel packaging structure and fabrication method for semiconductor devices. Multiple gallium nitride (GaN) power device dies are selected and formed into a die-package structure through a fan-out packaging process. The multiple GaN power device dies in the die-package structure are connected in parallel via a redistribution layer, connecting their source, drain, and gate in parallel. This allows for dual-chip parallel connection of the GaN power devices without changing the package area, reducing the resistance of the GaN power devices and thus improving their performance. Furthermore, compared to traditional GaN parallel packaging structures, this significantly reduces the parasitic inductance of the GaN packaging structure, solves packaging problems such as cross-wiring, and improves both the device's performance and the effective utilization rate at the application end.

[0020] By utilizing fan-out packaging technology and redistribution technology, electrical design is added to the layout of the redistribution layer, reducing the length of the power loop and reducing electromagnetic interference between the source, gate, and drain power loops of the multiple gallium nitride power device chips. This results in reduced resistance, parasitic inductance, and power loss in the circuit. As a high-frequency switching device, gallium nitride power devices significantly reduce switching losses and increase the efficiency of the commutation circuit. Attached Figure Description

[0021] Figure 1 The diagram shows a schematic of the packaging process for traditional gallium nitride power devices. Figure 2 The diagram shown is a schematic diagram of a parallel packaging structure of a semiconductor device according to an embodiment of the present invention; Figure 3 The diagram shown is a flowchart illustrating a method for fabricating a parallel packaging structure of a semiconductor device according to an embodiment of the present invention. Figure 4 The diagram shown is a schematic diagram of the bonding structure between a gallium nitride power device die and a carrier plate in a method for fabricating a parallel packaging structure of a semiconductor device according to an embodiment of the present invention. Figure 5 The diagram shown is a schematic diagram of the back-side molding of a gallium nitride power device die, which is a method for fabricating a parallel packaging structure of a semiconductor device according to an embodiment of the present invention. Figure 6 The diagram shown is a schematic representation of the structure of a gallium nitride power device after removing the carrier plate from the die, according to a method for fabricating a parallel packaging structure of a semiconductor device in an embodiment of the present invention. Figure 7 The diagram shown is a schematic diagram of the redistribution layer on the front side of a gallium nitride power device die in a method for fabricating a parallel packaging structure of a semiconductor device according to an embodiment of the present invention. Figure 8The diagram shown is a cross-sectional view of the redistribution layer of the functional layer of a gallium nitride power device die in a method for fabricating a parallel packaging structure of a semiconductor device according to an embodiment of the present invention. Figure 9 The diagram shown is a schematic diagram of the die thinning structure of a gallium nitride power device according to a method for fabricating a parallel packaging structure of a semiconductor device in an embodiment of the present invention. Detailed Implementation

[0022] To facilitate understanding by those skilled in the art, the present invention will be further described in detail below with reference to specific embodiments.

[0023] This invention provides a parallel packaging structure for a semiconductor device. Please refer to [link / reference]. Figure 2 ,include: Die-to-die packaging structure 30, lead frame 10; The die package structure 30 is formed by multiple gallium nitride power device dies 101 through a fan-out packaging process. The multiple gallium nitride power device dies 101 have a parallel structure, and the die package structure 30 has a source pin structure 31, a drain pin structure 32, and a gate pin structure 33. The lead frame 10 includes a frame base island 12 and pins 11; The die package structure 30 is attached to the frame base island 12, and the source pin structure 31, drain pin structure 32, gate pin structure 33 of the die package structure 30 are electrically connected to the pins 11 of the lead frame.

[0024] In this embodiment of the invention, the multiple gallium nitride power device chips 101 are two gallium nitride power device chips 101.

[0025] In this embodiment of the invention, the on-resistance of the die packaging structure 30 is equal to R, where R is the on-resistance of a single gallium nitride power device die 101.

[0026] The parallel structure formed by the multiple gallium nitride power device dies 101 reduces the resistance of the die packaging structure 30 to almost half the resistance of a single gallium nitride power device die 101, thereby lowering the resistance of the gallium nitride power device and doubling its performance.

[0027] The die packaging structure 30 consists of multiple gallium nitride power device dies 101 with a certain spacing, the spacing being greater than or equal to the diameter of the molding compound 300 particles, so that the molding compound 300 can fill the spaces between the multiple gallium nitride power device dies 101.

[0028] In this embodiment of the invention, the die packaging structure 30 specifically includes: a redistribution layer 500, multiple gallium nitride power device dies 101 located on the surface of the redistribution layer 500, and a molding compound 300 encapsulating the multiple gallium nitride power device dies; The gallium nitride power device die 101 includes a front side with a functional layer and a back side with an opposite functional layer. The front side of the multiple gallium nitride power device dies is disposed opposite to the redistribution layer 500, and the gate, source, and drain of the front side of the gallium nitride power device die are electrically connected to the gate pin structure 33, source pin structure 31, and drain pin structure 32 of the redistribution layer through the redistribution layer 500.

[0029] The multiple gallium nitride power device chips 101 are arranged opposite each other, that is, the sources of the multiple gallium nitride power device chips 101 are arranged opposite each other, so that there is a certain gap between the sources and drains of the multiple gallium nitride power device chips 101. This avoids the phenomenon of electrical breakdown when current is passed because the distance between the source and drain is too close. At the same time, the opposite arrangement of the sources makes the current transmission path shorter, which is more conducive to improving the yield of gallium nitride power devices.

[0030] In this embodiment of the invention, the redistribution layer 500 wraps around the gates of multiple gallium nitride power device dies 101 and isolates them within the sources of the multiple gallium nitride power device dies 101, preventing the drains of the multiple gallium nitride power device dies 101 from electrically breaking down the gates of the multiple gallium nitride power device dies 101.

[0031] In this embodiment of the invention, the redistribution layer 500 between the sources of the multiple gallium nitride power device dies 101 has multiple openings.

[0032] In this embodiment of the invention, the plurality of openings are square in shape; in other embodiments, the plurality of openings are circular, rectangular, triangular, trapezoidal, or other suitable shapes.

[0033] The multiple openings serve to release stress in the redistribution layer 500, preventing problems such as warping, delamination, bubbling, and easy breakage at stress concentration points caused by excessively large redistribution layer 500 areas between the sources of multiple gallium nitride power device chips 101, thus affecting the quality of semiconductor devices.

[0034] In this embodiment of the invention, the distance between the drain of the plurality of gallium nitride power device chips and the source of the plurality of gallium nitride power device chips is greater than 350 micrometers.

[0035] Experiments have shown that when the distance between the drain and source of the multiple gallium nitride power device chips is greater than 350 micrometers, leakage breakdown can be effectively prevented.

[0036] In this embodiment of the invention, the drain pin structure 32 on one side of the die packaging structure has a concave-convex structure, which has a recessed portion and a raised portion. The recessed portion is the welding area of ​​the drain of the gallium nitride power device die.

[0037] In this embodiment of the invention, the concave-convex structure is serrated.

[0038] The source, gate, and drain of the multiple gallium nitride power device dies 101 are electrically connected using a redistribution layer 500, so that the multiple gallium nitride power device dies 101 have a parallel structure. This results in a low on-resistance in the final die package structure 30, which improves the yield of semiconductor devices and avoids the cross-influence between metal leads that occurs when metal leads are used to electrically connect the dies of traditional gallium nitride power devices.

[0039] The die packaging structure 30 employs a rewiring process to rearrange the current path of the parallel packaging structure of semiconductor devices, reducing the use of metal leads when the multiple gallium nitride power device dies 101 and the lead frame pins 11 are electrically connected. This significantly reduces the trace distance of the parallel packaging structure of semiconductor devices, avoids interference from the potential difference generated between the source and drain of the multiple gallium nitride power device dies 101 when current flows, and also reduces the parasitic inductance of the gallium nitride power devices.

[0040] Without changing the existing gallium nitride wafer process, the fan-out packaging process makes the multiple gallium nitride power device dies 101 in the die packaging structure 30 more compact, improves the utilization rate of the frame base island 12 area, and effectively reduces the overall packaging area of ​​the gallium nitride power device.

[0041] By utilizing fan-out packaging technology and redistribution technology, the length of the entire circuit loop of gallium nitride power devices is reduced, resulting in a decrease in resistance and parasitic inductance in the circuit. This significantly reduces switching losses when gallium nitride power devices are used as high-frequency switching devices.

[0042] This invention also provides a method for fabricating a parallel packaging structure for semiconductor devices; please refer to [link / reference]. Figure 3 ,include: Step S10: Provide multiple gallium nitride power device dies, wherein the multiple gallium nitride power device dies include a front side having a functional layer and a back side having a relative functional layer; Step S20: The front sides of the multiple gallium nitride power device chips are attached to the surface of the carrier board. The gates of the multiple gallium nitride power device chips are placed opposite each other, and the sources are placed opposite each other. The front sides of the multiple gallium nitride power device chips are in the same plane. Step S30: The back of the plurality of gallium nitride power device dies is filled with molding compound to encapsulate them; Step S40: Remove the carrier plate; Step S50: A redistribution layer is formed on the front side of the plurality of gallium nitride power device dies. The redistribution layer has a gate pin structure, a source pin structure and a drain pin structure. The gate, source and drain on the front side of the plurality of gallium nitride power device dies are electrically connected to the gate pin structure, source pin structure and drain pin structure of the redistribution layer. Step S60: The multiple gallium nitride power device dies after the redistribution layer is formed are cut to the target size to form a die package structure of the target size; Step S70: Attach the die package structure to the frame base island and electrically connect the source pin structure, drain pin structure, gate pin structure of the die package structure and the pins of the lead frame. Step S80: The die packaging structure and lead frame are packaged.

[0043] Specifically, in step S10, multiple gallium nitride power device dies 101 are provided, the multiple gallium nitride power device dies 101 including a front side having a functional layer and a back side having a relative functional layer.

[0044] The specific steps for forming the multiple gallium nitride power device dies 101 are as follows: providing a gallium nitride wafer, the gallium nitride wafer integrating multiple tested gallium nitride power device chips, the side of the gallium nitride wafer with the chips being the front side of the gallium nitride wafer, and the gallium nitride wafer back side relative to the front side of the gallium nitride wafer; thinning the back side of the gallium nitride wafer, the thickness of the thinned gallium nitride wafer being greater than the target thickness of the die packaging structure 30; then cutting the gallium nitride wafer to form independent gallium nitride power device dies 101; finally selecting multiple gallium nitride power device dies 101 with complete functions.

[0045] Please refer to step S20 for execution instructions. Figure 4 The front sides of the plurality of gallium nitride power device chips 101 are attached to the surface of the carrier plate 100. The gates of the plurality of gallium nitride power device chips 101 are arranged opposite each other, and the sources are arranged opposite each other. The front sides of the plurality of gallium nitride power device chips 101 are in the same plane.

[0046] In this embodiment of the invention, the bonding step includes: preparing a carrier board 100 and an adhesive tape 200, attaching the adhesive tape 200 to the surface of the carrier board 100, and then attaching the front sides of the plurality of gallium nitride power device chips 101 to the surface of the adhesive tape 200.

[0047] In this embodiment of the invention, the multiple gallium nitride power device chips 101 are gallium nitride power device chips 101 with complete structure and good quality selected from adjacent regions according to the wafer pattern, so as to ensure the stability of the performance of the final gallium nitride power device.

[0048] In this embodiment of the invention, the carrier plate 100 is a metal carrier plate.

[0049] When the front sides of the multiple gallium nitride power device chips 101 are attached to the carrier plate 100, there is a certain gap, so that when the back sides of the multiple gallium nitride power device chips 101 are subsequently filled with molding compound 300 for molding, the molding compound 300 can fill the gaps between the multiple gallium nitride power device chips 101.

[0050] The spacing is greater than the diameter of the molding compound 300 particles, so that the molding compound 300 can fill the spaces between the multiple gallium nitride power device chips 101.

[0051] In this embodiment of the invention, the specified spacing is 75 micrometers or more.

[0052] Please refer to step S30 for execution. Figure 5 The back of the plurality of gallium nitride power device chips 101 is filled with molding compound 300 for molding.

[0053] In this embodiment of the invention, the molding material 300 is epoxy resin.

[0054] Please refer to step S40 for execution. Figure 6 Remove the carrier plate 100.

[0055] Please refer to step S50 for execution. Figures 7-8 A redistribution layer 500 is formed on the front side of the plurality of gallium nitride power device dies. The redistribution layer 500 has a gate pin structure 33, a source pin structure 31 and a drain pin structure 32. The gate, source and drain of the plurality of gallium nitride power device dies 101 are electrically connected to the gate pin structure 33, the source pin structure 31 and the drain pin structure 32 of the redistribution layer.

[0056] In this embodiment of the invention, the formation of the redistribution layer 500 specifically includes: Photoresist is applied to the functional layer of the plurality of gallium nitride power device chips 101 to form a first photoresist layer.

[0057] The first photoresist layer is exposed and developed to expose the source, gate, and drain on the front side of the multiple gallium nitride power device chips 101, forming trenches.

[0058] In this embodiment of the invention, a mask with a first window is used for the first exposure and development. The pattern of the first window corresponds to the source, gate and drain on the front side of the multiple gallium nitride power device dies 101, reserving an electroplating area for the subsequent formation of the redistribution layer 500.

[0059] Seed layers are formed on the surface of the first photoresist layer and the surface of the trench.

[0060] In this embodiment of the invention, the seed layer is formed by a sputtering process, and the material of the seed layer is TiCu. In other embodiments, the seed layer is TiWCu.

[0061] The seed layer reduces the lateral stress of gallium nitride power devices, which is beneficial for the growth of redistribution layers in subsequent processes.

[0062] Photoresist is coated on the surface of the seed layer to form a second photoresist layer.

[0063] The second photoresist layer is subjected to a second exposure and development, which exposes the seed layer corresponding to the trench, forming an opening.

[0064] In this embodiment of the invention, a mask with a second window is used for a second exposure and development. The pattern of the second window corresponds to the trench, the pattern between the sources of the multiple gallium nitride power device dies 101, and the concave-convex structure on one side of the drain pin structure 32 of the die package structure.

[0065] In this embodiment of the invention, by designing a mask pattern with a second window, the distance between the drain and source of the multiple gallium nitride power device dies, and the distance between the source and gate of the multiple gallium nitride power device dies 101 are controlled.

[0066] Electroplating is performed on the surface of the opening and the second photoresist layer to form a redistribution metal layer, which makes the source and source, drain and drain, and gate and gate of the multiple gallium nitride power device dies 101 electrically connected. The redistribution metal layer that electrically connects the source, drain and gate is the source pin structure 31, drain pin structure 32 and gate pin structure 33 of the die package structure 30.

[0067] In this embodiment of the invention, the electroplating material is CuNiAu.

[0068] Remove the second photoresist layer and the redistribution metal layer on the surface of the second photoresist layer.

[0069] The seed layer is removed, and the redistribution layer 500 is finally formed.

[0070] In this embodiment of the invention, the redistribution layer 500 that is finally formed wraps around the gates of the plurality of gallium nitride power device dies 101 and isolates them within the sources of the plurality of gallium nitride power device dies 101, preventing the drains of the plurality of gallium nitride power device dies 101 from electrically breaking down the gates of the plurality of gallium nitride power device dies 101.

[0071] The distance between the drain and source of the multiple gallium nitride power device chips 101 is greater than 350 micrometers. Experiments have shown that when the distance is greater than 350 micrometers, leakage breakdown can be effectively prevented.

[0072] In this embodiment of the invention, a redistribution layer 500 is formed using a redistribution process. The redistribution layer 500 electrically connects the source, drain, and gate of the multiple gallium nitride power device dies 101, thereby forming a parallel structure of the multiple gallium nitride power device dies 101. This reduces the resistance of the formed die package structure 30 and improves the performance of the final gallium nitride power device.

[0073] In this embodiment of the invention, the source pin structure 31, drain pin structure 32 and gate pin structure 33 of the die package structure 30 are the soldering areas of the die package structure 30, and are electrically connected to the pins of the lead frame in subsequent processes.

[0074] In this embodiment of the invention, the multiple gallium nitride power device dies 101 are two gallium nitride power device dies, so that the resistance of the die packaging structure 30 is almost half the resistance of a single gallium nitride power die 101, thereby doubling the performance of the final gallium nitride power device.

[0075] The redistribution layer 500 optimizes the staggered layout design of current loops and the interference between power loops in the traditional parallel structure, reduces the switching losses of gallium nitride power devices, increases the working efficiency of the commutation circuit, and improves the performance and working stability of the module.

[0076] Without changing the existing gallium nitride wafer process, the fan-out packaging process makes the die package structure 30 more compact, improves the utilization rate of the frame base island 12 area, and effectively reduces the overall package area of ​​gallium nitride power devices compared with the traditional parallel connection method of metal leads, while improving the performance of gallium nitride power devices.

[0077] In step S60, the multiple gallium nitride power device dies 101 after the redistribution layer 500 is formed are cut to the target size to form a die package structure 30 of the target size.

[0078] In the embodiments of this invention, please refer to Figure 9It also includes: thinning the back side of the multiple gallium nitride power device dies after the redistribution layer is formed to the target thickness of the die packaging structure, and then cutting it to the target size to form a die packaging structure 30 of the target size.

[0079] In this embodiment of the invention, the back side of the die packaging structure 30 is thinned using a grinding process, which is an EMC grinding process, so that the gallium nitride power device die 101 reaches the target thickness of the die packaging structure 30.

[0080] In step S70, the die package structure 30 is attached to the frame base island 12, and the source pin structure 31, drain pin structure 32, gate pin structure 33 of the die package structure are electrically connected to the pins 11 of the lead frame.

[0081] In this embodiment of the invention, the die packaging structure 30 is bonded to the frame base island 12 using silver paste through a bonding process, and the source pin structure 31, drain pin structure 32, gate pin structure 33 and the pins 11 of the lead frame are electrically connected using metal leads.

[0082] Step S80 is performed to encapsulate the die packaging structure 30 and the lead frame 10.

[0083] In this embodiment of the invention, the die encapsulation structure 30 and the lead frame 10 are encapsulated and cured using an epoxy resin injection molding process.

[0084] In this embodiment of the invention, the parallel packaging structure formed by the gallium nitride power device die 101 through the fan-out packaging process is applied to one of the following packaging types: DFN packaging, TO220, TO247, BGA, LGA, PLP, and ECP.

[0085] Finally, it should be noted that any modification or equivalent substitution of some or all of the technical features based on the technical solutions of the structure, method and embodiments of the present invention, without departing from the corresponding technical solutions of the present invention, shall fall within the patent scope of the structure, method and embodiments of the present invention.

Claims

1. A parallel package structure of semiconductor devices, characterized by, include: Die-to-die packaging structure, lead frame; The die packaging structure is formed by multiple gallium nitride (GaN) power device dies through a fan-out packaging process. The multiple GaN power device dies have a parallel structure, and the die packaging structure has a source pin structure, a drain pin structure, and a gate pin structure. Specifically, the die packaging structure includes: a redistribution layer, multiple GaN power device dies located on the surface of the redistribution layer, and a molding compound encapsulating the multiple GaN power device dies. The GaN power device dies include a front side with a functional layer and a back side with an opposite functional layer. The front side of the multiple GaN power device dies is positioned opposite to the redistribution layer, and the gate, source, and drain pins of the front side of the GaN power device dies are electrically connected to the gate pin structure, source pin structure, and drain pin structure of the redistribution layer using the redistribution layer. The lead frame includes a frame base island and pins; The die package structure is bonded to the frame base island, and the source pin structure, drain pin structure, gate pin structure of the die package structure are electrically connected to the pins of the lead frame.

2. A parallel package structure of semiconductor devices as claimed in claim 1, wherein, The multiple gallium nitride power device chips are two gallium nitride power device chips.

3. The parallel packaging structure of a semiconductor device as described in claim 2, characterized in that, The on-resistance of the die package structure is equal to R, the on-resistance of a single gallium nitride power device die.

4. The parallel package structure of a semiconductor device according to claim 1, wherein The redistribution layer encloses and isolates the gates of multiple gallium nitride power device dies within the sources of the multiple gallium nitride power device dies, and the redistribution layer between the sources of the multiple gallium nitride power device dies has multiple openings.

5. The parallel package structure of a semiconductor device according to claim 1, wherein The spacing between the drain and source of the multiple gallium nitride power device chips is greater than 350 micrometers.

6. The parallel packaging structure of a semiconductor device as described in claim 1, characterized in that, The drain pin structure on one side of the die packaging structure has a concave-convex structure, which has a recessed portion and a raised portion. The recessed portion is the welding area of ​​the drain of the gallium nitride power device die.

7. A method for fabricating a parallel packaging structure of a semiconductor device as described in claim 1, characterized in that, include: Provide multiple gallium nitride power device dies, the multiple gallium nitride power device dies including a front side having a functional layer and a back side having a relative functional layer; The front sides of the multiple gallium nitride power device chips are attached to the surface of the carrier board, with the gates of the multiple gallium nitride power device chips facing each other and the sources facing each other, and the front sides of the multiple gallium nitride power device chips are in the same plane. The back of the multiple gallium nitride power device chips is filled with a molding compound for encapsulation. Remove the carrier plate; A redistribution layer is formed on the front side of the multiple gallium nitride power device dies. The redistribution layer has a gate pin structure, a source pin structure, and a drain pin structure. The gate, source, and drain on the front side of the multiple gallium nitride power device dies are electrically connected to the gate pin structure, source pin structure, and drain pin structure of the redistribution layer. The multiple gallium nitride power device dies after the redistribution layer is formed are cut to the target size to form a die package structure of the target size; The die package structure is attached to the frame base island, and the source pin structure, drain pin structure, gate pin structure of the die package structure and the pins of the lead frame are electrically connected. The die packaging structure and lead frame are then packaged.

8. The method for fabricating a parallel packaging structure of a semiconductor device as described in claim 7, characterized in that, The die packaging structure is formed by fan-out packaging of two gallium nitride power device dies. The parallel packaging structure formed by fan-out packaging of the gallium nitride power device dies is applied to one of the following packaging types: DFN packaging, TO220, TO247, BGA, LGA, PLP, and ECP.

9. The method for fabricating a parallel packaging structure for a semiconductor device as described in claim 7, characterized in that, Also includes: The back side of the multiple gallium nitride power device dies after the redistribution layer is formed is thinned to the target thickness of the die packaging structure.

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