A packaging structure

Abstract

This invention provides a packaging structure comprising: a cap wafer and a device wafer, and further comprising a first wiring layer and / or a second wiring layer; the device wafer includes a device layer, and the cap wafer is located on the side of the device wafer where the device layer is disposed; the first wiring layer is located on the side of the device wafer away from the cap wafer, and the second wiring layer is located on the side of the cap wafer away from the device wafer; the first wiring layer includes at least one inductor, and the second wiring layer includes at least one inductor; the device layer is electrically connected to the inductor. In this embodiment, the inductor can be directly disposed on the side of the device wafer away from the cap wafer and / or the side of the cap wafer away from the device wafer, eliminating the need to place the inductor on the PCB board, thereby reducing the size of the packaging structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and in particular to a packaging structure. Background Technology

[0002] With the rapid development of various mobile consumer electronics products, miniaturization and performance improvement have become increasingly important.

[0003] Inductors play a crucial role in electronic products and are indispensable components. Currently, inductors are typically installed on PCBs (Printed Circuit Boards), and a large number of inductors occupy significant space on the PCB, leading to an excessively large PCB size and ultimately, an excessively large packaged electronic product. Summary of the Invention

[0004] In this embodiment, the inductor can be directly placed on the side of the device wafer away from the cap wafer and / or on the side of the cap wafer away from the device wafer, eliminating the need to place the inductor on the PCB board, thereby reducing the size of the package structure.

[0005] This invention provides a packaging structure comprising: a cap wafer and a device wafer, and further comprising a first wiring layer and / or a second wiring layer;

[0006] The device wafer includes a device layer, and the cap wafer is located on the side of the device wafer where the device layer is disposed;

[0007] The first wiring layer is located on the side of the device wafer away from the cap wafer, and the second wiring layer is located on the side of the cap wafer away from the device wafer;

[0008] The first wiring layer includes at least one inductor, the second wiring layer includes at least one inductor, and the device layer is electrically connected to the inductor.

[0009] Optionally, the first wiring layer includes at least two first sub-wiring layers, and a second insulating layer is disposed between two adjacent first sub-wiring layers; each first sub-wiring layer includes at least one inductor.

[0010] The second wiring layer includes at least two second sub-wiring layers, and a second insulating layer is disposed between two adjacent second sub-wiring layers; each second sub-wiring layer includes at least one inductor.

[0011] Optionally, at least one of the width, number of turns, and total length of the traces corresponding to different inductors in the first wiring layer is different;

[0012] In the second wiring layer, at least one of the width, number of turns, and total length of the traces corresponding to different inductors is different.

[0013] Optionally, the packaging structure provided in this embodiment also includes a first circuit board;

[0014] When the package structure includes a first wiring layer, the first circuit board is located on the side of the first wiring layer away from the device wafer; when the package structure includes a second wiring layer, the first circuit board is located on the side of the second wiring layer away from the cap wafer.

[0015] When the package structure includes a first wiring layer and a second wiring layer, the first circuit board is located on the side of the first wiring layer away from the device wafer, or the first circuit board is located on the side of the second wiring layer away from the cap wafer.

[0016] Optionally, the first circuit board and the first wiring layer include a plurality of conductive pillars, which are multiplexed as inductors;

[0017] The first circuit board and the second wiring layer include a plurality of conductive pillars, which are multiplexed as inductors.

[0018] Optionally, the base area of ​​at least one of the conductive pillars is different from the base areas of the other conductive pillars.

[0019] Optionally, the first circuit board and the first wiring layer include a plurality of conductive pillars;

[0020] The first circuit board and the second wiring layer include a plurality of conductive pillars.

[0021] Optionally, the packaging structure provided in this embodiment also includes a second circuit board;

[0022] The first circuit board is located on the side of the first wiring layer away from the device wafer, and the second circuit board is located on the side of the second wiring layer away from the cap wafer; or

[0023] The second circuit board is located on the side of the first wiring layer away from the device wafer, and the first circuit board is located on the side of the second wiring layer away from the cap wafer.

[0024] Optionally, the packaging structure provided in this embodiment further includes a packaging layer;

[0025] The encapsulation layer is used to enclose the cap wafer, the device wafer, the first wiring layer, and the first circuit board, and exposes the surface of the first circuit board away from the first wiring layer; or,

[0026] The encapsulation layer is used to enclose the cap wafer, the device wafer, the second wiring layer, and the first circuit board, and exposes the surface of the first circuit board away from the second wiring layer.

[0027] Optionally, when the packaging structure includes a first wiring layer, the device wafer includes a plurality of first vias, and the first wiring layer is electrically connected to the device layer through the first vias;

[0028] When the packaging structure includes the second wiring layer, the cap wafer includes a plurality of second vias, and the second wiring layer is electrically connected to the device layer through the second vias.

[0029] This invention provides a packaging structure in which a first wiring layer is located on the side of the device wafer away from the cap wafer, and / or a second wiring layer is located on the side of the cap wafer away from the device wafer. The device wafer includes a device layer, and both the first and second wiring layers include at least one inductor, which is electrically connected to the device layer. In this embodiment, the inductor can be directly disposed on the side of the device wafer away from the cap wafer and / or the side of the cap wafer away from the device wafer, eliminating the need to place the inductor on the PCB board, thereby reducing the size of the packaging structure. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of a packaging structure provided in an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention;

[0033] Figure 4 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention;

[0034] Figure 5 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention;

[0035] Figure 6 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention;

[0036] Figure 7 A schematic diagram of the structure of an inductor provided in an embodiment of the present invention;

[0037] Figure 8 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention;

[0038] Figure 9 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention;

[0039] Figure 10This is a schematic diagram of another packaging structure provided in an embodiment of the present invention;

[0040] Figure 11 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention;

[0041] Figure 12 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention;

[0042] Figure 13 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention;

[0043] Figure 14 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention;

[0044] Figure 15 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention;

[0045] Figure 16 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention;

[0046] Figure 17 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention;

[0047] Figure 18 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention;

[0048] Figure 19 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention. Detailed Implementation

[0049] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and not intended to limit the scope of the invention. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the embodiments of the present invention, and not all structures.

[0050] Figure 1 This is a schematic diagram of a packaging structure provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention, with reference to... Figures 1-3The packaging structure provided in this embodiment includes a cap wafer 110 and a device wafer 120, and also includes a first wiring layer 130 and / or a second wiring layer 140; the device wafer 120 includes a device layer 121, and the cap wafer 110 is located on the side of the device wafer 120 where the device layer 121 is disposed; the first wiring layer 130 is located on the side of the device wafer 120 away from the cap wafer 110, and the second wiring layer 140 is located on the side of the cap wafer 110 away from the device wafer 120; the first wiring layer 130 includes at least one inductor, and the second wiring layer 140 includes at least one inductor; the device layer 121 is electrically connected to the inductor.

[0051] Specifically, the device wafer 120 and the cap wafer 110 are bonded together by a bonding layer 111, and a cavity may be included between the device wafer 120 and the cap wafer 110. Figure 1 The package structure shown includes a first wiring layer 130. Figure 2 The package structure shown includes a second wiring layer 140. Figure 3The package structure shown includes a first wiring layer 130 and a second wiring layer 140. Device layer 121 includes electronic components such as resistors and capacitors. Device wafer 120 also includes a substrate 122. The first wiring layer 130 is located on the side of substrate 122 away from device layer 121. The substrate 122 is located between the first wiring layer 130 and device layer 121. The substrate 122 is relatively thick, which can keep the inductors in the first wiring layer 130 away from device layer 121, thereby reducing the parasitic effect of the inductors in the first wiring layer 130 on device layer 121. A cap wafer 110 is located between the second wiring layer 140 and device layer 121. The cap wafer 110 has a certain thickness. The inductors in the second wiring layer 130 are not directly adjacent to device layer 121, thereby reducing the parasitic effect of the inductors in the second wiring layer 140 on device layer 121. Since other components need to be placed on the PCB board, the positional relationship between the inductor and other components, as well as electrical interference, must be considered when setting the inductor. Placing the inductor within the PCB board results in a larger PCB board size. In this embodiment, the first wiring layer 130 can be directly placed on the surface of the device wafer 120 away from the cap wafer 110, and the second wiring layer 140 can be directly placed on the surface of the cap wafer 110 away from the device wafer 120. No other components besides the inductor can be placed in the first wiring layer 130 and the second wiring layer 140. The inductor's placement does not need to consider interference with other components, and the total length, width, and number of turns of the inductor can be set according to actual needs. Therefore, the first wiring layer 130 and the second wiring layer 140 have a smaller thickness, which can reduce the package size of the package structure. The substrate 122 can be etched using photolithography, and then the first wiring layer 130 can be placed in the photolithographically etched groove, so that the inductor is placed inside the device wafer 120. Alternatively, the cap wafer 110 can be etched using photolithography, and then the second wiring layer 140 can be placed in the photolithographically etched groove. Therefore, compared to placing the inductor in the PCB board, placing the inductor in the first wiring layer 130 and / or the second wiring layer 140 can reduce the size of the package structure. The device layer 121 is electrically connected to the inductor, thereby realizing information exchange between the device layer 121 and the inductor.

[0052] This invention provides a packaging structure in which a first wiring layer is located on the side of the device wafer away from the cap wafer, and / or a second wiring layer is located on the side of the cap wafer away from the device wafer. The device wafer includes a device layer, and both the first and second wiring layers include at least one inductor, which is electrically connected to the device layer. In this embodiment, the inductor can be directly disposed on the side of the device wafer away from the cap wafer and / or the side of the cap wafer away from the device wafer, eliminating the need to place the inductor on the PCB board, thereby reducing the size of the packaging structure.

[0053] Optional, Figure 4 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention, with reference to... Figures 4-6 The first wiring layer 130 includes at least two first sub-wiring layers 131, and a first insulating layer 132 is disposed between two adjacent first sub-wiring layers 131; each first sub-wiring layer 131 includes at least one inductor; the second wiring layer 140 includes at least two second sub-wiring layers 141, and a second insulating layer 142 is disposed between two adjacent second sub-wiring layers 141; each second sub-wiring layer 141 includes at least one inductor.

[0054] Specifically, Figure 4 The package structure shown includes a first wiring layer 130. Figure 5 The package structure shown includes a second wiring layer 140. Figure 6 The package structure shown includes a first wiring layer 130 and a second wiring layer 140. In practical applications, the number of first sub-wiring layers 131 in the first wiring layer 130 and the number of second sub-wiring layers 141 in the second wiring layer 140 can be set according to actual needs, thereby determining the total inductance value in the package structure.

[0055] Optional, Figure 7 This is a schematic diagram of the structure of an inductor provided in an embodiment of the present invention, with reference to... Figure 7 In the first wiring layer, at least one of the width, number of turns, and total length of the traces corresponding to different inductors is different; in the second wiring layer, at least one of the width, number of turns, and total length of the traces corresponding to different inductors is different.

[0056] Specifically, Figure 7 The structure shown is a schematic diagram of the inductor structure in the first wiring layer. (Refer to...) Figure 7 The first wiring layer includes three inductors, all of which are electrically connected to the device layer. In practical applications, the number of inductors, the material of the inductors, the thickness of the inductors, the dielectric constant of the inductors, the width, number of turns and length of each inductor, and the connection relationship between the inductors can be set according to actual needs in the first wiring layer and / or the second wiring layer.

[0057] It should be noted that, Figure 7 The illustration of the first wiring layer including three inductors is merely illustrative and is not intended to limit the scope of the invention.

[0058] Optional, Figure 8 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention. Figure 9 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention. Figure 10 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention. Figure 11 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention, with reference to... Figures 8-11 The packaging structure provided in this embodiment also includes a first circuit board 150; when the packaging structure includes a first wiring layer 130, the first circuit board 150 is located on the side of the first wiring layer 130 away from the device wafer 120 (see reference). Figure 8 When the package structure includes a second wiring layer 140, the first circuit board 150 is located on the side of the second wiring layer 140 away from the cap wafer 110 (see reference). Figure 9 When the package structure includes a first wiring layer 130 and a second wiring layer 140, the first circuit board 150 is located on the side of the first wiring layer 130 away from the device wafer 120 (see reference). Figure 10 Alternatively, the first circuit board 150 is located on the side of the second wiring layer 140 away from the cap wafer 110 (see reference). Figure 11 ).

[0059] Specifically, the first circuit board 150 can be a PCB board. In this embodiment, the first wiring layer 130 is disposed on one side of the device wafer 120 and / or the second wiring layer 140 is disposed on one side of the cap wafer 110, eliminating the need for an inductor in the first circuit board 150, thereby reducing the size of the first circuit board 150. If an inductor is disposed in the first circuit board 150, the size of the first circuit board 150 will increase, and will be larger than the package structure with inductors disposed on both sides of the device wafer 120. Therefore, in this embodiment, the inductor is disposed outside the first circuit board 150, which can reduce the size of the package structure.

[0060] Optional, continue to refer to Figures 8-11 The first circuit board 150 and the first wiring layer 130 include a plurality of conductive pillars 151, and the first circuit board 150 and the second wiring layer 140 include a plurality of conductive pillars 151, and the conductive pillars 151 are reused as inductors.

[0061] Specifically, the conductive post 151 is used for signal transmission between the first circuit board 150 and the inductor.

[0062] Optionally, the conductive post 151 can be reused as an inductor. The conductive post 151 can also be reused as an inductor. Reusing the conductive post 151 as an inductor can reduce the number of inductors in the first wiring layer 130 and the second wiring layer 140, thereby reducing the volume of the first wiring layer 130 and the second wiring layer 140, and further reducing the volume of the package structure.

[0063] Optionally, the base area of ​​at least one conductive post is different from the base areas of the other conductive posts.

[0064] Specifically, if the conductive pillars only serve the function of transmitting signals, then all conductive pillars can be set to have the same shape. If the conductive pillars are reused as inductors, since the total inductance in the package structure is set according to actual needs, and the size of the bottom area of ​​the conductive pillars affects the size of the inductance, once the actual required total inductance value is determined, the required total inductance value can be matched by controlling the bottom area of ​​the conductive pillars.

[0065] Optionally, different inductance values ​​can be obtained by changing the shape of the conductive pillars. For example, the shape of the conductive pillars can be set to resemble a cylinder, cuboid, or semi-cylinder.

[0066] Optional, Figure 12 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention. Figure 13 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention, with reference to... Figure 12 and Figure 13 The packaging structure provided in this embodiment also includes a second circuit board 160. The first circuit board 150 is located on the side of the first wiring layer 130 away from the device wafer 120, and the second circuit board 160 is located on the side of the second wiring layer 140 away from the cap wafer 110 (see reference). Figure 12 Alternatively, the second circuit board 160 may be located on the side of the first wiring layer 130 away from the device wafer 120, and the first circuit board 150 may be located on the side of the second wiring layer 140 away from the cap wafer 110 (see reference). Figure 13 ).

[0067] Specifically, neither the first circuit board 150 nor the second circuit board 160 may contain inductors, thereby reducing their size. Given the same number of inductors, the package structure with both the first wiring layer 130 and the second wiring layer 140 is smaller than the package structure with only the first wiring layer 130 or only the second wiring layer 140. Furthermore, the absence of inductors in both the first circuit board 150 and the second circuit board 160 further reduces the overall package size.

[0068] Figure 14 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention. Figure 15 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention, with reference to... Figure 14 and Figure 15 The packaging structure provided in this embodiment further includes a packaging layer 170; the packaging layer 170 is used to encapsulate the cap wafer 110, the device wafer 120, the first wiring layer 130, and the first circuit board 150, and exposes the surface of the first circuit board 150 away from the first wiring layer 130 (see reference). Figure 14Alternatively, the encapsulation layer 170 is used to enclose the cap wafer 110, the device wafer 120, the second wiring layer 140, and the first circuit board 150, and exposes the surface of the first circuit board 150 away from the second wiring layer 140 (see reference). Figure 15 ).

[0069] Specifically, the encapsulation layer 170 protects the cap wafer 110, device wafer 120, first wiring layer 130, second wiring layer 140, and first circuit board 150 from external moisture, dust, and other contaminants, thereby improving the lifespan of the encapsulation structure. The encapsulation layer 170 exposes the surface of the first circuit board 150 away from the first wiring layer 130, allowing the surface of the first circuit board 150 away from the first wiring layer 130 to connect with other devices. The encapsulation layer 170 also exposes the surface of the first circuit board 150 away from the second wiring layer 140, allowing the surface of the first circuit board 150 away from the second wiring layer 140 to connect with other devices. When the encapsulation structure includes the first circuit board 150 and the second circuit board 160, the encapsulation layer encapsulates the wafer 110, device wafer 120, first wiring layer 130, second wiring layer 140, first circuit board 150, and second circuit board 160, wherein the encapsulation layer 170 exposes the surface of the first circuit board 150 away from the first wiring layer 130 or the surface of the second circuit board 160 away from the second wiring layer 140. Figure 16 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention, with reference to... Figure 16 , Figure 16 In the package structure shown, the package layer 170 is exposed on the surface of the first circuit board 150 away from the first wiring layer 130.

[0070] Optional, Figure 17 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention. Figure 18 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention. Figure 19 This is a schematic diagram of another packaging structure provided in an embodiment of the present invention, with reference to... Figures 17-19 When the package structure includes a first wiring layer 130, the device wafer 120 includes a plurality of first vias 123, and the first wiring layer 130 is electrically connected to the device layer 121 through the first vias 123; when the package structure includes a second wiring layer 140, the cap wafer 110 includes a plurality of second vias 124, and the second wiring layer 140 is electrically connected to the device layer 121 through the second vias 124.

[0071] Specifically, Figure 17 The package structure shown includes a first wiring layer 130. Figure 18 The package structure shown includes a second wiring layer 140. Figure 19The package structure shown includes a first wiring layer 130 and a second wiring layer 140. Conductive strips are disposed within both the first via 123 and the second via 124. These conductive strips are used for signal transmission between device layer 121 and the first wiring layer 130 and / or between device layer 121 and the second wiring layer 140. The first via 123 is disposed within device wafer 120, electrically connecting device layer 121 to the first wiring layer 130. The second via 124 is disposed within cap wafer 110, electrically connecting device layer 121 to the second wiring layer 140. This eliminates the need for external leads on device wafer 120 to achieve electrical connection between device layer 121 and the first wiring layer 130, and also eliminates the need for external leads on cap wafer 110 to achieve electrical connection between device layer 121 and the second wiring layer 140, thereby further reducing the size of the package structure.

[0072] Note that the above are merely preferred embodiments and the technical principles applied in this invention. Those skilled in the art will understand that the embodiments of this invention are not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the protection scope of this invention. Therefore, although the embodiments of this invention have been described in detail above, the embodiments of this invention are not limited to the above embodiments. More other equivalent embodiments may be included without departing from the concept of the embodiments of this invention, and the scope of the embodiments of this invention is determined by the scope of the appended claims.

Claims

1. A package structure, characterized by, include: The cap wafer and the device wafer also include a first wiring layer and / or a second wiring layer; The device wafer includes a device layer, and the cap wafer is located on the side of the device wafer where the device layer is disposed; The first wiring layer is located on the side of the device wafer away from the cap wafer, and the second wiring layer is located on the side of the cap wafer away from the device wafer; The first wiring layer includes at least one inductor, and the second wiring layer includes at least one inductor; the device layer is electrically connected to the inductor; wherein, no other devices besides inductors are provided in the first wiring layer and the second wiring layer.

2. The package structure of claim 1, wherein, The first wiring layer includes at least two first sub-wiring layers, and a second insulating layer is disposed between two adjacent first sub-wiring layers; each first sub-wiring layer includes at least one inductor; The second wiring layer includes at least two second sub-wiring layers, and a second insulating layer is disposed between two adjacent second sub-wiring layers; each second sub-wiring layer includes at least one inductor.

3. The package structure of claim 1, wherein, In the first wiring layer, at least one of the width, number of turns, and total length of the traces corresponding to different inductors is different; In the second wiring layer, at least one of the width, number of turns, and total length of the traces corresponding to different inductors is different.

4. The package structure of claim 1, wherein, It also includes the first circuit board; When the package structure includes a first wiring layer, the first circuit board is located on the side of the first wiring layer away from the device wafer; when the package structure includes a second wiring layer, the first circuit board is located on the side of the second wiring layer away from the cap wafer. When the package structure includes a first wiring layer and a second wiring layer, the first circuit board is located on the side of the first wiring layer away from the device wafer, or the first circuit board is located on the side of the second wiring layer away from the cap wafer.

5. The package structure of claim 4, wherein, The first circuit board and the first wiring layer include a plurality of conductive pillars, which are multiplexed as inductors; The first circuit board and the second wiring layer include a plurality of conductive pillars, which are multiplexed as inductors.

6. The package structure of claim 5, wherein, At least one of the conductive pillars has a different base area than the other conductive pillars.

7. The package structure of claim 4, wherein, The first circuit board and the first wiring layer include a plurality of conductive pillars; The first circuit board and the second wiring layer include a plurality of conductive pillars.

8. The package structure of claim 4, wherein, It also includes a second circuit board; The first circuit board is located on the side of the first wiring layer away from the device wafer, and the second circuit board is located on the side of the second wiring layer away from the cap wafer; or The second circuit board is located on the side of the first wiring layer away from the device wafer, and the first circuit board is located on the side of the second wiring layer away from the cap wafer.

9. The package structure of claim 4, wherein, It also includes a packaging layer; The encapsulation layer is used to enclose the cap wafer, the device wafer, the first wiring layer, and the first circuit board, and exposes the surface of the first circuit board away from the first wiring layer; or, The encapsulation layer is used to enclose the cap wafer, the device wafer, the second wiring layer, and the first circuit board, and exposes the surface of the first circuit board away from the second wiring layer.

10. The package structure of claim 1, wherein, When the packaging structure includes a first wiring layer, the device wafer includes a plurality of first vias, and the first wiring layer is electrically connected to the device layer through the first vias; When the packaging structure includes the second wiring layer, the cap wafer includes a plurality of second vias, and the second wiring layer is electrically connected to the device layer through the second vias.

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